Merge tag 'sunxi-core-for-3.16-2' of https://github.com/mripard/linux into next/soc
Merge "Allwinner Core additions for 3.16, take 2" from Maxime Ripard: - Convert the A31 SMP operations to the CPU_METHOD_OF_DECLARE mechanism - Remove the reset code from the machine definition, that removes pretty much all the code left in mach-sunxi * tag 'sunxi-core-for-3.16-2' of https://github.com/mripard/linux: ARM: sunxi: Remove init_machine callback ARM: sunxi: Remove reset code from the platform ARM: sun6i: Retire the smp field in A31 machine Documentation: dt: bindings: Document Allwinner A31 enable method ARM: sun6i: Use CPU_METHOD_OF_DECLARE Documentation: dt: bindings: Document ARM PSCI enable method Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
3c2580173e
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@ -182,6 +182,8 @@ nodes to be present and contain the properties described below.
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"psci"
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"psci"
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# On ARM 32-bit systems this property is optional and
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# On ARM 32-bit systems this property is optional and
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can be one of:
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can be one of:
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"arm,psci"
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"allwinner,sun6i-a31"
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"qcom,gcc-msm8660"
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"qcom,gcc-msm8660"
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"qcom,kpss-acc-v1"
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"qcom,kpss-acc-v1"
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"qcom,kpss-acc-v2"
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"qcom,kpss-acc-v2"
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@ -1,19 +0,0 @@
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/*
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* Core functions for Allwinner SoCs
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*
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* Copyright (C) 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ARCH_SUNXI_COMMON_H_
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#define __ARCH_SUNXI_COMMON_H_
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void sun6i_secondary_startup(void);
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extern struct smp_operations sun6i_smp_ops;
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#endif /* __ARCH_SUNXI_COMMON_H_ */
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@ -21,8 +21,6 @@
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#include <linux/of_address.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <linux/smp.h>
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#include "common.h"
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#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
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#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
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#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
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#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
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#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
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#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
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@ -122,3 +120,4 @@ struct smp_operations sun6i_smp_ops __initdata = {
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.smp_prepare_cpus = sun6i_smp_prepare_cpus,
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.smp_prepare_cpus = sun6i_smp_prepare_cpus,
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.smp_boot_secondary = sun6i_smp_boot_secondary,
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.smp_boot_secondary = sun6i_smp_boot_secondary,
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};
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};
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CPU_METHOD_OF_DECLARE(sun6i_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
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@ -12,111 +12,8 @@
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#include <linux/clk-provider.h>
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#include <linux/clk-provider.h>
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#include <linux/clocksource.h>
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#include <linux/clocksource.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#include <linux/reboot.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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#include "common.h"
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#define SUN4I_WATCHDOG_CTRL_REG 0x00
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#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
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#define SUN4I_WATCHDOG_MODE_REG 0x04
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#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0)
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#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1)
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#define SUN6I_WATCHDOG1_IRQ_REG 0x00
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#define SUN6I_WATCHDOG1_CTRL_REG 0x10
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#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0)
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#define SUN6I_WATCHDOG1_CONFIG_REG 0x14
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#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0)
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#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1)
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#define SUN6I_WATCHDOG1_MODE_REG 0x18
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#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
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static void __iomem *wdt_base;
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static void sun4i_restart(enum reboot_mode mode, const char *cmd)
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{
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if (!wdt_base)
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return;
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/* Enable timer and set reset bit in the watchdog */
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writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
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wdt_base + SUN4I_WATCHDOG_MODE_REG);
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/*
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* Restart the watchdog. The default (and lowest) interval
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* value for the watchdog is 0.5s.
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*/
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writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
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while (1) {
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mdelay(5);
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writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
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wdt_base + SUN4I_WATCHDOG_MODE_REG);
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}
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}
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static void sun6i_restart(enum reboot_mode mode, const char *cmd)
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{
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if (!wdt_base)
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return;
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/* Disable interrupts */
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writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG);
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/* We want to disable the IRQ and just reset the whole system */
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writel(SUN6I_WATCHDOG1_CONFIG_RESTART,
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wdt_base + SUN6I_WATCHDOG1_CONFIG_REG);
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/* Enable timer. The default and lowest interval value is 0.5s */
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writel(SUN6I_WATCHDOG1_MODE_ENABLE,
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wdt_base + SUN6I_WATCHDOG1_MODE_REG);
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/* Restart the watchdog. */
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writel(SUN6I_WATCHDOG1_CTRL_RESTART,
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wdt_base + SUN6I_WATCHDOG1_CTRL_REG);
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while (1) {
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mdelay(5);
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writel(SUN6I_WATCHDOG1_MODE_ENABLE,
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wdt_base + SUN6I_WATCHDOG1_MODE_REG);
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}
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}
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static struct of_device_id sunxi_restart_ids[] = {
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{ .compatible = "allwinner,sun4i-a10-wdt" },
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{ .compatible = "allwinner,sun6i-a31-wdt" },
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{ /*sentinel*/ }
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};
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static void sunxi_setup_restart(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, sunxi_restart_ids);
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if (WARN(!np, "unable to setup watchdog restart"))
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return;
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wdt_base = of_iomap(np, 0);
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WARN(!wdt_base, "failed to map watchdog base address");
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}
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static void __init sunxi_dt_init(void)
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{
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sunxi_setup_restart();
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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static const char * const sunxi_board_dt_compat[] = {
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static const char * const sunxi_board_dt_compat[] = {
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"allwinner,sun4i-a10",
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"allwinner,sun4i-a10",
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};
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};
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DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
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DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
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.init_machine = sunxi_dt_init,
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.dt_compat = sunxi_board_dt_compat,
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.dt_compat = sunxi_board_dt_compat,
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.restart = sun4i_restart,
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MACHINE_END
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MACHINE_END
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static const char * const sun6i_board_dt_compat[] = {
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static const char * const sun6i_board_dt_compat[] = {
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}
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}
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DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
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DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
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.init_machine = sunxi_dt_init,
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.init_time = sun6i_timer_init,
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.init_time = sun6i_timer_init,
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.dt_compat = sun6i_board_dt_compat,
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.dt_compat = sun6i_board_dt_compat,
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.restart = sun6i_restart,
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.smp = smp_ops(sun6i_smp_ops),
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MACHINE_END
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MACHINE_END
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static const char * const sun7i_board_dt_compat[] = {
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static const char * const sun7i_board_dt_compat[] = {
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};
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};
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DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
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DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
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.init_machine = sunxi_dt_init,
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.dt_compat = sun7i_board_dt_compat,
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.dt_compat = sun7i_board_dt_compat,
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.restart = sun4i_restart,
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MACHINE_END
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MACHINE_END
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