ARM: LPC32XX: System suspend support
Support for system suspend and resume Signed-off-by: Kevin Wells <wellsk40@gmail.com>
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Kevin Wells
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/*
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* arch/arm/mach-lpc32xx/pm.c
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*
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* Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
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* Modified by Kevin Wells <kevin.wells@nxp.com>
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* LPC32XX CPU and system power management
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*
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* The LCP32XX has three CPU modes for controlling system power: run,
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* direct-run, and halt modes. When switching between halt and run modes,
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* the CPU transistions through direct-run mode. For Linux, direct-run
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* mode is not used in normal operation. Halt mode is used when the
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* system is fully suspended.
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*
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* Run mode:
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* The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
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* derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
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* the HCLK_PLL rate. Linux runs in this mode.
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*
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* Direct-run mode:
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* The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
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* SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
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* source or the frequency of the main oscillator. In this mode, the
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* HCLK_PLL can be safely enabled, changed, or disabled.
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*
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* Halt mode:
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* SYSCLK is gated off and the CPU and system clocks are halted.
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* Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
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* key scanner, etc.) still operate if enabled. In this state, an enabled
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* system event (ie, GPIO state change, RTC match, key press, etc.) will
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* wake the system up back into direct-run mode.
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*
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* DRAM refresh
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* DRAM clocking and refresh are slightly different for systems with DDR
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* DRAM or regular SDRAM devices. If SDRAM is used in the system, the
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* SDRAM will still be accessible in direct-run mode. In DDR based systems,
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* a transistion to direct-run mode will stop all DDR accesses (no clocks).
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* Because of this, the code to switch power modes and the code to enter
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* and exit DRAM self-refresh modes must not be executed in DRAM. A small
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* section of IRAM is used instead for this.
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*
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* Suspend is handled with the following logic:
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* Backup a small area of IRAM used for the suspend code
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* Copy suspend code to IRAM
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* Transfer control to code in IRAM
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* Places DRAMs in self-refresh mode
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* Enter direct-run mode
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* Save state of HCLK_PLL PLL
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* Disable HCLK_PLL PLL
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* Enter halt mode - CPU and buses will stop
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* System enters direct-run mode when an enabled event occurs
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* HCLK PLL state is restored
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* Run mode is entered
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* DRAMS are placed back into normal mode
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* Code execution returns from IRAM
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* IRAM code are used for suspend is restored
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* Suspend mode is exited
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*/
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#include <linux/suspend.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <asm/cacheflush.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include "common.h"
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#include "clock.h"
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#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
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/*
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* Both STANDBY and MEM suspend states are handled the same with no
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* loss of CPU or memory state
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*/
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static int lpc32xx_pm_enter(suspend_state_t state)
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{
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int (*lpc32xx_suspend_ptr) (void);
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void *iram_swap_area;
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/* Allocate some space for temporary IRAM storage */
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iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_KERNEL);
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if (!iram_swap_area) {
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printk(KERN_ERR
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"PM Suspend: cannot allocate memory to save portion "
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"of SRAM\n");
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return -ENOMEM;
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}
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/* Backup a small area of IRAM used for the suspend code */
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memcpy(iram_swap_area, (void *) TEMP_IRAM_AREA,
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lpc32xx_sys_suspend_sz);
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/*
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* Copy code to suspend system into IRAM. The suspend code
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* needs to run from IRAM as DRAM may no longer be available
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* when the PLL is stopped.
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*/
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memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
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lpc32xx_sys_suspend_sz);
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flush_icache_range((unsigned long)TEMP_IRAM_AREA,
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(unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
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/* Transfer to suspend code in IRAM */
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lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
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flush_cache_all();
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(void) lpc32xx_suspend_ptr();
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/* Restore original IRAM contents */
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memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
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lpc32xx_sys_suspend_sz);
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kfree(iram_swap_area);
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return 0;
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}
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static struct platform_suspend_ops lpc32xx_pm_ops = {
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.valid = suspend_valid_only_mem,
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.enter = lpc32xx_pm_enter,
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};
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#define EMC_DYN_MEM_CTRL_OFS 0x20
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#define EMC_SRMMC (1 << 3)
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#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
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static int __init lpc32xx_pm_init(void)
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{
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/*
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* Setup SDRAM self-refresh clock to automatically disable o
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* start of self-refresh. This only needs to be done once.
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*/
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__raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
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suspend_set_ops(&lpc32xx_pm_ops);
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return 0;
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}
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arch_initcall(lpc32xx_pm_init);
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@ -0,0 +1,151 @@
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/*
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* arch/arm/mach-lpc32xx/suspend.S
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*
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* Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
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* Modified by Kevin Wells <kevin.wells@nxp.com>
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/platform.h>
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#include <mach/hardware.h>
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/* Using named register defines makes the code easier to follow */
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#define WORK1_REG r0
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#define WORK2_REG r1
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#define SAVED_HCLK_DIV_REG r2
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#define SAVED_HCLK_PLL_REG r3
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#define SAVED_DRAM_CLKCTRL_REG r4
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#define SAVED_PWR_CTRL_REG r5
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#define CLKPWRBASE_REG r6
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#define EMCBASE_REG r7
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#define LPC32XX_EMC_STATUS_OFFS 0x04
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#define LPC32XX_EMC_STATUS_BUSY 0x1
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#define LPC32XX_EMC_STATUS_SELF_RFSH 0x4
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#define LPC32XX_CLKPWR_PWR_CTRL_OFFS 0x44
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#define LPC32XX_CLKPWR_HCLK_DIV_OFFS 0x40
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#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
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#define CLKPWR_PCLK_DIV_MASK 0xFFFFFE7F
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.text
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ENTRY(lpc32xx_sys_suspend)
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@ Save a copy of the used registers in IRAM, r0 is corrupted
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adr r0, tmp_stack_end
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stmfd r0!, {r3 - r7, sp, lr}
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@ Load a few common register addresses
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adr WORK1_REG, reg_bases
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ldr CLKPWRBASE_REG, [WORK1_REG, #0]
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ldr EMCBASE_REG, [WORK1_REG, #4]
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ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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orr WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
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@ Wait for SDRAM busy status to go busy and then idle
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@ This guarantees a small windows where DRAM isn't busy
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1:
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ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
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and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
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cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
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bne 1b @ Branch while idle
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2:
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ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
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and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
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cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
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beq 2b @ Branch until idle
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@ Setup self-refresh with support for manual exit of
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@ self-refresh mode
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str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
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str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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@ Wait for self-refresh acknowledge, clocks to the DRAM device
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@ will automatically stop on start of self-refresh
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3:
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ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
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and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
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cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
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bne 3b @ Branch until self-refresh mode starts
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@ Enter direct-run mode from run mode
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bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
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str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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@ Safe disable of DRAM clock in EMC block, prevents DDR sync
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@ issues on restart
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ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_HCLK_DIV_OFFS]
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and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
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str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
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@ Save HCLK PLL state and disable HCLK PLL
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ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
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bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
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str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
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@ Enter stop mode until an enabled event occurs
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orr WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
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str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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.rept 9
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nop
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.endr
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@ Clear stop status
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bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
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@ Restore original HCLK PLL value and wait for PLL lock
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str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
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4:
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ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
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and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
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bne 4b
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@ Re-enter run mode with self-refresh flag cleared, but no DRAM
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@ update yet. DRAM is still in self-refresh
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str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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@ Restore original DRAM clock mode to restore DRAM clocks
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str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_HCLK_DIV_OFFS]
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@ Clear self-refresh mode
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orr WORK1_REG, SAVED_PWR_CTRL_REG,\
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#LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
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str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
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#LPC32XX_CLKPWR_PWR_CTRL_OFFS]
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@ Wait for EMC to clear self-refresh mode
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5:
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ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
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and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
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bne 5b @ Branch until self-refresh has exited
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@ restore regs and return
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adr r0, tmp_stack
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ldmfd r0!, {r3 - r7, sp, pc}
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reg_bases:
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.long IO_ADDRESS(LPC32XX_CLK_PM_BASE)
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.long IO_ADDRESS(LPC32XX_EMC_BASE)
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tmp_stack:
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.long 0, 0, 0, 0, 0, 0, 0
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tmp_stack_end:
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ENTRY(lpc32xx_sys_suspend_sz)
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.word . - lpc32xx_sys_suspend
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