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Blackfin arch: to do some consolidation of common code and common name spaces 

now all BLKFIN should be BFIN, should be no functional changes.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Robin Getz 2007-10-10 23:55:26 +08:00 committed by Bryan Wu
parent a298049180
commit 3bebca2d20
31 changed files with 289 additions and 391 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
arch/blackfin/Kconfig
View File

@ -722,22 +722,22 @@ endchoice
comment "Cache Support" comment "Cache Support"
config BLKFIN_CACHE config BFIN_ICACHE
bool "Enable ICACHE" bool "Enable ICACHE"
config BLKFIN_DCACHE config BFIN_DCACHE
bool "Enable DCACHE" bool "Enable DCACHE"
config BLKFIN_DCACHE_BANKA config BFIN_DCACHE_BANKA
bool "Enable only 16k BankA DCACHE - BankB is SRAM" bool "Enable only 16k BankA DCACHE - BankB is SRAM"
depends on BLKFIN_DCACHE && !BF531 depends on BFIN_DCACHE && !BF531
default n default n
config BLKFIN_CACHE_LOCK config BFIN_ICACHE_LOCK
bool "Enable Cache Locking" bool "Enable Instruction Cache Locking"
choice choice
prompt "Policy" prompt "Policy"
depends on BLKFIN_DCACHE depends on BFIN_DCACHE
default BLKFIN_WB default BFIN_WB
config BLKFIN_WB config BFIN_WB
bool "Write back" bool "Write back"
help help
Write Back Policy: Write Back Policy:
@ -754,7 +754,7 @@ config BLKFIN_WB
If you are unsure of the options and you want to be safe, If you are unsure of the options and you want to be safe,
then go with Write Through. then go with Write Through.
config BLKFIN_WT config BFIN_WT
bool "Write through" bool "Write through"
help help
Write Back Policy: Write Back Policy:

12
arch/blackfin/configs/BF533-EZKIT_defconfig
View File

@ -243,12 +243,12 @@ CONFIG_DMA_UNCACHED_1M=y
# #
# Cache Support # Cache Support
# #
CONFIG_BLKFIN_CACHE=y CONFIG_BFIN_ICACHE=y
CONFIG_BLKFIN_DCACHE=y CONFIG_BFIN_DCACHE=y
# CONFIG_BLKFIN_DCACHE_BANKA is not set # CONFIG_BFIN_DCACHE_BANKA is not set
# CONFIG_BLKFIN_CACHE_LOCK is not set # CONFIG_BFIN_ICACHE_LOCK is not set
# CONFIG_BLKFIN_WB is not set # CONFIG_BFIN_WB is not set
CONFIG_BLKFIN_WT=y CONFIG_BFIN_WT=y
CONFIG_L1_MAX_PIECE=16 CONFIG_L1_MAX_PIECE=16
# #

12
arch/blackfin/configs/BF533-STAMP_defconfig
View File

@ -255,12 +255,12 @@ CONFIG_DMA_UNCACHED_1M=y
# #
# Cache Support # Cache Support
# #
CONFIG_BLKFIN_CACHE=y CONFIG_BFIN_ICACHE=y
CONFIG_BLKFIN_DCACHE=y CONFIG_BFIN_DCACHE=y
# CONFIG_BLKFIN_DCACHE_BANKA is not set # CONFIG_BFIN_DCACHE_BANKA is not set
# CONFIG_BLKFIN_CACHE_LOCK is not set # CONFIG_BFIN_ICACHE_LOCK is not set
# CONFIG_BLKFIN_WB is not set # CONFIG_BFIN_WB is not set
CONFIG_BLKFIN_WT=y CONFIG_BFIN_WT=y
CONFIG_L1_MAX_PIECE=16 CONFIG_L1_MAX_PIECE=16
# #

12
arch/blackfin/configs/BF537-STAMP_defconfig
View File

@ -258,12 +258,12 @@ CONFIG_DMA_UNCACHED_1M=y
# #
# Cache Support # Cache Support
# #
CONFIG_BLKFIN_CACHE=y CONFIG_BFIN_ICACHE=y
CONFIG_BLKFIN_DCACHE=y CONFIG_BFIN_DCACHE=y
# CONFIG_BLKFIN_DCACHE_BANKA is not set # CONFIG_BFIN_DCACHE_BANKA is not set
# CONFIG_BLKFIN_CACHE_LOCK is not set # CONFIG_BFIN_ICACHE_LOCK is not set
# CONFIG_BLKFIN_WB is not set # CONFIG_BFIN_WB is not set
CONFIG_BLKFIN_WT=y CONFIG_BFIN_WT=y
CONFIG_L1_MAX_PIECE=16 CONFIG_L1_MAX_PIECE=16
# #

12
arch/blackfin/configs/BF548-EZKIT_defconfig
View File

@ -306,12 +306,12 @@ CONFIG_DMA_UNCACHED_1M=y
# #
# Cache Support # Cache Support
# #
CONFIG_BLKFIN_CACHE=y CONFIG_BFIN_ICACHE=y
CONFIG_BLKFIN_DCACHE=y CONFIG_BFIN_DCACHE=y
# CONFIG_BLKFIN_DCACHE_BANKA is not set # CONFIG_BFIN_DCACHE_BANKA is not set
# CONFIG_BLKFIN_CACHE_LOCK is not set # CONFIG_BFIN_ICACHE_LOCK is not set
# CONFIG_BLKFIN_WB is not set # CONFIG_BFIN_WB is not set
CONFIG_BLKFIN_WT=y CONFIG_BFIN_WT=y
CONFIG_L1_MAX_PIECE=16 CONFIG_L1_MAX_PIECE=16
# #

12
arch/blackfin/configs/BF561-EZKIT_defconfig
View File

@ -288,12 +288,12 @@ CONFIG_DMA_UNCACHED_1M=y
# #
# Cache Support # Cache Support
# #
CONFIG_BLKFIN_CACHE=y CONFIG_BFIN_ICACHE=y
CONFIG_BLKFIN_DCACHE=y CONFIG_BFIN_DCACHE=y
# CONFIG_BLKFIN_DCACHE_BANKA is not set # CONFIG_BFIN_DCACHE_BANKA is not set
# CONFIG_BLKFIN_CACHE_LOCK is not set # CONFIG_BFIN_ICACHE_LOCK is not set
# CONFIG_BLKFIN_WB is not set # CONFIG_BFIN_WB is not set
CONFIG_BLKFIN_WT=y CONFIG_BFIN_WT=y
CONFIG_L1_MAX_PIECE=16 CONFIG_L1_MAX_PIECE=16
# #

12
arch/blackfin/configs/PNAV-10_defconfig
View File

@ -257,12 +257,12 @@ CONFIG_DMA_UNCACHED_1M=y
# #
# Cache Support # Cache Support
# #
CONFIG_BLKFIN_CACHE=y CONFIG_BFIN_ICACHE=y
CONFIG_BLKFIN_DCACHE=y CONFIG_BFIN_DCACHE=y
# CONFIG_BLKFIN_DCACHE_BANKA is not set # CONFIG_BFIN_DCACHE_BANKA is not set
# CONFIG_BLKFIN_CACHE_LOCK is not set # CONFIG_BFIN_ICACHE_LOCK is not set
CONFIG_BLKFIN_WB=y CONFIG_BFIN_WB=y
# CONFIG_BLKFIN_WT is not set # CONFIG_BFIN_WT is not set
CONFIG_L1_MAX_PIECE=16 CONFIG_L1_MAX_PIECE=16
# #

5
arch/blackfin/kernel/cacheinit.c
View File

@ -21,9 +21,10 @@
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/blackfin.h> #include <asm/blackfin.h>
#include <asm/cplb.h>
#include <asm/cplbinit.h> #include <asm/cplbinit.h>
#if defined(CONFIG_BLKFIN_CACHE) #if defined(CONFIG_BFIN_ICACHE)
void bfin_icache_init(void) void bfin_icache_init(void)
{ {
unsigned long *table = icplb_table; unsigned long *table = icplb_table;
@ -44,7 +45,7 @@ void bfin_icache_init(void)
} }
#endif #endif
#if defined(CONFIG_BLKFIN_DCACHE) #if defined(CONFIG_BFIN_DCACHE)
void bfin_dcache_init(void) void bfin_dcache_init(void)
{ {
unsigned long *table = dcplb_table; unsigned long *table = dcplb_table;

5
arch/blackfin/kernel/cplbinit.c
View File

@ -23,6 +23,7 @@
#include <linux/module.h> #include <linux/module.h>
#include <asm/blackfin.h> #include <asm/blackfin.h>
#include <asm/cplb.h>
#include <asm/cplbinit.h> #include <asm/cplbinit.h>
u_long icplb_table[MAX_CPLBS+1]; u_long icplb_table[MAX_CPLBS+1];
@ -56,7 +57,7 @@ struct s_cplb {
struct cplb_tab switch_d; struct cplb_tab switch_d;
}; };
#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
static struct cplb_desc cplb_data[] = { static struct cplb_desc cplb_data[] = {
{ {
.start = 0, .start = 0,
@ -230,7 +231,7 @@ static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_en
cplb_data[i].psize, cplb_data[i].psize,
cplb_data[i].i_conf); cplb_data[i].i_conf);
} else { } else {
#if defined(CONFIG_BLKFIN_CACHE) #if defined(CONFIG_BFIN_ICACHE)
if (ANOMALY_05000263 && i == SDRAM_KERN) { if (ANOMALY_05000263 && i == SDRAM_KERN) {
fill_cplbtab(t, fill_cplbtab(t,
cplb_data[i].start, cplb_data[i].start,

2
arch/blackfin/kernel/process.c
View File

@ -136,7 +136,7 @@ void cpu_idle(void)
void machine_restart(char *__unused) void machine_restart(char *__unused)
{ {
#if defined(CONFIG_BLKFIN_CACHE) #if defined(CONFIG_BFIN_ICACHE)
bfin_write_IMEM_CONTROL(0x01); bfin_write_IMEM_CONTROL(0x01);
SSYNC(); SSYNC();
#endif #endif

29
arch/blackfin/kernel/setup.c
View File

@ -39,6 +39,7 @@
#include <linux/cramfs_fs.h> #include <linux/cramfs_fs.h>
#include <linux/romfs_fs.h> #include <linux/romfs_fs.h>
#include <asm/cplb.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/blackfin.h> #include <asm/blackfin.h>
#include <asm/cplbinit.h> #include <asm/cplbinit.h>
@ -66,21 +67,21 @@ char __initdata command_line[COMMAND_LINE_SIZE];
void __init bf53x_cache_init(void) void __init bf53x_cache_init(void)
{ {
#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
generate_cpl_tables(); generate_cpl_tables();
#endif #endif
#ifdef CONFIG_BLKFIN_CACHE #ifdef CONFIG_BFIN_ICACHE
bfin_icache_init(); bfin_icache_init();
printk(KERN_INFO "Instruction Cache Enabled\n"); printk(KERN_INFO "Instruction Cache Enabled\n");
#endif #endif
#ifdef CONFIG_BLKFIN_DCACHE #ifdef CONFIG_BFIN_DCACHE
bfin_dcache_init(); bfin_dcache_init();
printk(KERN_INFO "Data Cache Enabled" printk(KERN_INFO "Data Cache Enabled"
# if defined CONFIG_BLKFIN_WB # if defined CONFIG_BFIN_WB
" (write-back)" " (write-back)"
# elif defined CONFIG_BLKFIN_WT # elif defined CONFIG_BFIN_WT
" (write-through)" " (write-through)"
# endif # endif
"\n"); "\n");
@ -262,7 +263,7 @@ void __init setup_arch(char **cmdline_p)
&& ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
mtd_size = mtd_size =
PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
# if (defined(CONFIG_BLKFIN_CACHE) && ANOMALY_05000263) # if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
/* Due to a Hardware Anomaly we need to limit the size of usable /* Due to a Hardware Anomaly we need to limit the size of usable
* instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
* 05000263 - Hardware loop corrupted when taking an ICPLB exception * 05000263 - Hardware loop corrupted when taking an ICPLB exception
@ -291,7 +292,7 @@ void __init setup_arch(char **cmdline_p)
_ebss = memory_mtd_start; /* define _ebss for compatible */ _ebss = memory_mtd_start; /* define _ebss for compatible */
#endif /* CONFIG_MTD_UCLINUX */ #endif /* CONFIG_MTD_UCLINUX */
#if (defined(CONFIG_BLKFIN_CACHE) && ANOMALY_05000263) #if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
/* Due to a Hardware Anomaly we need to limit the size of usable /* Due to a Hardware Anomaly we need to limit the size of usable
* instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
* 05000263 - Hardware loop corrupted when taking an ICPLB exception * 05000263 - Hardware loop corrupted when taking an ICPLB exception
@ -535,9 +536,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "I-CACHE:\tOFF\n"); seq_printf(m, "I-CACHE:\tOFF\n");
if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE)) if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
seq_printf(m, "D-CACHE:\tON" seq_printf(m, "D-CACHE:\tON"
#if defined CONFIG_BLKFIN_WB #if defined CONFIG_BFIN_WB
" (write-back)" " (write-back)"
#elif defined CONFIG_BLKFIN_WT #elif defined CONFIG_BFIN_WT
" (write-through)" " (write-through)"
#endif #endif
"\n"); "\n");
@ -566,15 +567,15 @@ static int show_cpuinfo(struct seq_file *m, void *v)
} }
seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024); seq_printf(m, "I-CACHE Size:\t%dKB\n", BFIN_ICACHESIZE / 1024);
seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size); seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size);
seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n", seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n",
BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES); BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
seq_printf(m, seq_printf(m,
"D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS, dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
BLKFIN_DLINES); BFIN_DLINES);
#ifdef CONFIG_BLKFIN_CACHE_LOCK #ifdef CONFIG_BFIN_ICACHE_LOCK
switch (read_iloc()) { switch (read_iloc()) {
case WAY0_L: case WAY0_L:
seq_printf(m, "Way0 Locked-Down\n"); seq_printf(m, "Way0 Locked-Down\n");

5
arch/blackfin/mach-common/arch_checks.c
View File

@ -53,3 +53,8 @@
# endif # endif
#endif /* CONFIG_BFIN_KERNEL_CLOCK */ #endif /* CONFIG_BFIN_KERNEL_CLOCK */
#if (CONFIG_MEM_SIZE % 4)
#error "SDRAM mem size must be multible of 4MB"
#endif

8
arch/blackfin/mach-common/cacheinit.S
View File

@ -39,7 +39,7 @@
.text .text
#if ANOMALY_05000125 #if ANOMALY_05000125
#if defined(CONFIG_BLKFIN_CACHE) #if defined(CONFIG_BFIN_ICACHE)
ENTRY(_bfin_write_IMEM_CONTROL) ENTRY(_bfin_write_IMEM_CONTROL)
/* Enable Instruction Cache */ /* Enable Instruction Cache */
@ -58,10 +58,10 @@ ENTRY(_bfin_write_IMEM_CONTROL)
ENDPROC(_bfin_write_IMEM_CONTROL) ENDPROC(_bfin_write_IMEM_CONTROL)
#endif #endif
#if defined(CONFIG_BLKFIN_DCACHE) #if defined(CONFIG_BFIN_DCACHE)
ENTRY(_bfin_write_DMEM_CONTROL) ENTRY(_bfin_write_DMEM_CONTROL)
P0.l = (DMEM_CONTROL & 0xFFFF); P0.l = LO(DMEM_CONTROL);
P0.h = (DMEM_CONTROL >> 16); P0.h = HI(DMEM_CONTROL);
CLI R1; CLI R1;
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */

8
arch/blackfin/mach-common/cplbhdlr.S
View File

@ -69,14 +69,14 @@ ENTRY(__cplb_hdr)
.Lis_icplb_miss: .Lis_icplb_miss:
#if defined(CONFIG_BLKFIN_CACHE) || defined(CONFIG_BLKFIN_DCACHE) #if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
# if defined(CONFIG_BLKFIN_CACHE) && !defined(CONFIG_BLKFIN_DCACHE) # if defined(CONFIG_BFIN_ICACHE) && !defined(CONFIG_BFIN_DCACHE)
R1 = CPLB_ENABLE_ICACHE; R1 = CPLB_ENABLE_ICACHE;
# endif # endif
# if !defined(CONFIG_BLKFIN_CACHE) && defined(CONFIG_BLKFIN_DCACHE) # if !defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
R1 = CPLB_ENABLE_DCACHE; R1 = CPLB_ENABLE_DCACHE;
# endif # endif
# if defined(CONFIG_BLKFIN_CACHE) && defined(CONFIG_BLKFIN_DCACHE) # if defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
# endif # endif
#else #else

2
arch/blackfin/mach-common/cplbmgr.S
View File

@ -565,7 +565,7 @@ ENTRY(_cplb_mgr)
* cost of first-write exceptions to mark the page as dirty. * cost of first-write exceptions to mark the page as dirty.
*/ */
#ifdef CONFIG_BLKFIN_WT #ifdef CONFIG_BFIN_WT
BITSET(R6, 14); /* Set WT*/ BITSET(R6, 14); /* Set WT*/
#endif #endif

4
arch/blackfin/mach-common/lock.S
View File

@ -33,7 +33,7 @@
.text .text
#ifdef CONFIG_BLKFIN_CACHE_LOCK #ifdef CONFIG_BFIN_ICACHE_LOCK
/* When you come here, it is assumed that /* When you come here, it is assumed that
* R0 - Which way to be locked * R0 - Which way to be locked
@ -189,7 +189,7 @@ ENTRY(_cache_lock)
RTS; RTS;
ENDPROC(_cache_lock) ENDPROC(_cache_lock)
#endif /* BLKFIN_CACHE_LOCK */ #endif /* BFIN_ICACHE_LOCK */
/* Return the ILOC bits of IMEM_CONTROL /* Return the ILOC bits of IMEM_CONTROL
*/ */

14
include/asm-blackfin/cacheflush.h
View File

@ -48,9 +48,9 @@ extern void blackfin_dflush_page(void *);
static inline void flush_icache_range(unsigned start, unsigned end) static inline void flush_icache_range(unsigned start, unsigned end)
{ {
#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_CACHE) #if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE)
# if defined(CONFIG_BLKFIN_WT) # if defined(CONFIG_BFIN_WT)
blackfin_icache_flush_range((start), (end)); blackfin_icache_flush_range((start), (end));
# else # else
blackfin_icache_dcache_flush_range((start), (end)); blackfin_icache_dcache_flush_range((start), (end));
@ -58,10 +58,10 @@ static inline void flush_icache_range(unsigned start, unsigned end)
#else #else
# if defined(CONFIG_BLKFIN_CACHE) # if defined(CONFIG_BFIN_ICACHE)
blackfin_icache_flush_range((start), (end)); blackfin_icache_flush_range((start), (end));
# endif # endif
# if defined(CONFIG_BLKFIN_DCACHE) # if defined(CONFIG_BFIN_DCACHE)
blackfin_dcache_flush_range((start), (end)); blackfin_dcache_flush_range((start), (end));
# endif # endif
@ -74,12 +74,12 @@ do { memcpy(dst, src, len); \
} while (0) } while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) #define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
#if defined(CONFIG_BLKFIN_DCACHE) #if defined(CONFIG_BFIN_DCACHE)
# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end)) # define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
#else #else
# define invalidate_dcache_range(start,end) do { } while (0) # define invalidate_dcache_range(start,end) do { } while (0)
#endif #endif
#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_WB) #if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB)
# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) # define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
# define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) # define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
#else #else
@ -87,4 +87,4 @@ do { memcpy(dst, src, len); \
# define flush_dcache_page(page) do { } while (0) # define flush_dcache_page(page) do { } while (0)
#endif #endif
#endif /* _BLACKFIN_CACHEFLUSH_H */ #endif /* _BLACKFIN_ICACHEFLUSH_H */

89
include/asm-blackfin/cplb.h
View File

@ -1,18 +1,93 @@
/************************************************************************ /*
* File: include/asm-blackfin/cplb.h
* Based on: include/asm-blackfin/mach-bf537/bf537.h
* Author: Robin Getz <rgetz@blackfin.uclinux.org>
* *
* cplb.h * Created: 2000
* Description: Common CPLB definitions for CPLB init
* *
* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. * Modified:
* Copyright 2004-2007 Analog Devices Inc.
* *
************************************************************************/ * Bugs: Enter bugs at http://blackfin.uclinux.org/
*
/* Defines necessary for cplb initialisation routines. */ * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _CPLB_H #ifndef _CPLB_H
#define _CPLB_H #define _CPLB_H
# include <asm/blackfin.h> # include <asm/blackfin.h>
#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
#if ANOMALY_05000158
#define ANOMALY_05000158_WORKAROUND 0x200
#else
#define ANOMALY_05000158_WORKAROUND 0x0
#endif
#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#ifdef CONFIG_BFIN_WB /*Write Back Policy */
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
#else /*Write Through */
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
#endif
#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
#define SDRAM_DNON_CHBL (CPLB_COMMON)
#define SDRAM_EBIU (CPLB_COMMON)
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
#define SIZE_1K 0x00000400 /* 1K */
#define SIZE_4K 0x00001000 /* 4K */
#define SIZE_1M 0x00100000 /* 1M */
#define SIZE_4M 0x00400000 /* 4M */
#define MAX_CPLBS (16 * 2)
/*
* Number of required data CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Data Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
* 1 for ASYNC Memory
*/
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
/*
* Number of required instruction CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Instruction Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
*/
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
#define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_ICACHE_P 0
#define CPLB_ENABLE_DCACHE_P 1 #define CPLB_ENABLE_DCACHE_P 1
#define CPLB_ENABLE_DCACHE2_P 2 #define CPLB_ENABLE_DCACHE2_P 2
@ -39,8 +114,6 @@
#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID

16
include/asm-blackfin/mach-bf533/bf533.h
View File

@ -52,12 +52,12 @@
/***************************/ /***************************/
#define BLKFIN_DSUBBANKS 4 #define BFIN_DSUBBANKS 4
#define BLKFIN_DWAYS 2 #define BFIN_DWAYS 2
#define BLKFIN_DLINES 64 #define BFIN_DLINES 64
#define BLKFIN_ISUBBANKS 4 #define BFIN_ISUBBANKS 4
#define BLKFIN_IWAYS 4 #define BFIN_IWAYS 4
#define BLKFIN_ILINES 32 #define BFIN_ILINES 32
#define WAY0_L 0x1 #define WAY0_L 0x1
#define WAY1_L 0x2 #define WAY1_L 0x2
@ -167,10 +167,10 @@
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ /*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
#define ANOMALY_05000158_WORKAROUND 0x200 #define ANOMALY_05000158_WORKAROUND 0x200
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ #ifdef CONFIG_BFIN_WB /*Write Back Policy */
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#else /*Write Through */ #else /*Write Through */

56
include/asm-blackfin/mach-bf533/mem_map.h
View File

@ -51,10 +51,10 @@
/* Level 1 Memory */ /* Level 1 Memory */
#ifdef CONFIG_BLKFIN_CACHE #ifdef CONFIG_BFIN_ICACHE
#define BLKFIN_ICACHESIZE (16*1024) #define BFIN_ICACHESIZE (16*1024)
#else #else
#define BLKFIN_ICACHESIZE (0*1024) #define BFIN_ICACHESIZE (0*1024)
#endif #endif
/* Memory Map for ADSP-BF533 processors */ /* Memory Map for ADSP-BF533 processors */
@ -64,35 +64,35 @@
#define L1_DATA_A_START 0xFF800000 #define L1_DATA_A_START 0xFF800000
#define L1_DATA_B_START 0xFF900000 #define L1_DATA_B_START 0xFF900000
#ifdef CONFIG_BLKFIN_CACHE #ifdef CONFIG_BFIN_ICACHE
#define L1_CODE_LENGTH (0x14000 - 0x4000) #define L1_CODE_LENGTH (0x14000 - 0x4000)
#else #else
#define L1_CODE_LENGTH 0x14000 #define L1_CODE_LENGTH 0x14000
#endif #endif
#ifdef CONFIG_BLKFIN_DCACHE #ifdef CONFIG_BFIN_DCACHE
#ifdef CONFIG_BLKFIN_DCACHE_BANKA #ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000
#define BLKFIN_DCACHESIZE (16*1024) #define BFIN_DCACHESIZE (16*1024)
#define BLKFIN_DSUPBANKS 1 #define BFIN_DSUPBANKS 1
#else #else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000)
#define BLKFIN_DCACHESIZE (32*1024) #define BFIN_DCACHESIZE (32*1024)
#define BLKFIN_DSUPBANKS 2 #define BFIN_DSUPBANKS 2
#endif #endif
#else #else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_A_LENGTH 0x8000
#define L1_DATA_B_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000
#define BLKFIN_DCACHESIZE (0*1024) #define BFIN_DCACHESIZE (0*1024)
#define BLKFIN_DSUPBANKS 0 #define BFIN_DSUPBANKS 0
#endif /*CONFIG_BLKFIN_DCACHE*/ #endif /*CONFIG_BFIN_DCACHE*/
#endif #endif
/* Memory Map for ADSP-BF532 processors */ /* Memory Map for ADSP-BF532 processors */
@ -102,36 +102,36 @@
#define L1_DATA_A_START 0xFF804000 #define L1_DATA_A_START 0xFF804000
#define L1_DATA_B_START 0xFF904000 #define L1_DATA_B_START 0xFF904000
#ifdef CONFIG_BLKFIN_CACHE #ifdef CONFIG_BFIN_ICACHE
#define L1_CODE_LENGTH (0xC000 - 0x4000) #define L1_CODE_LENGTH (0xC000 - 0x4000)
#else #else
#define L1_CODE_LENGTH 0xC000 #define L1_CODE_LENGTH 0xC000
#endif #endif
#ifdef CONFIG_BLKFIN_DCACHE #ifdef CONFIG_BFIN_DCACHE
#ifdef CONFIG_BLKFIN_DCACHE_BANKA #ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_A_LENGTH (0x4000 - 0x4000)
#define L1_DATA_B_LENGTH 0x4000 #define L1_DATA_B_LENGTH 0x4000
#define BLKFIN_DCACHESIZE (16*1024) #define BFIN_DCACHESIZE (16*1024)
#define BLKFIN_DSUPBANKS 1 #define BFIN_DSUPBANKS 1
#else #else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_A_LENGTH (0x4000 - 0x4000)
#define L1_DATA_B_LENGTH (0x4000 - 0x4000) #define L1_DATA_B_LENGTH (0x4000 - 0x4000)
#define BLKFIN_DCACHESIZE (32*1024) #define BFIN_DCACHESIZE (32*1024)
#define BLKFIN_DSUPBANKS 2 #define BFIN_DSUPBANKS 2
#endif #endif
#else #else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x4000 #define L1_DATA_A_LENGTH 0x4000
#define L1_DATA_B_LENGTH 0x4000 #define L1_DATA_B_LENGTH 0x4000
#define BLKFIN_DCACHESIZE (0*1024) #define BFIN_DCACHESIZE (0*1024)
#define BLKFIN_DSUPBANKS 0 #define BFIN_DSUPBANKS 0
#endif /*CONFIG_BLKFIN_DCACHE*/ #endif /*CONFIG_BFIN_DCACHE*/
#endif #endif
/* Memory Map for ADSP-BF531 processors */ /* Memory Map for ADSP-BF531 processors */
@ -144,16 +144,16 @@
#define L1_DATA_B_LENGTH 0x0000 #define L1_DATA_B_LENGTH 0x0000
#ifdef CONFIG_BLKFIN_DCACHE #ifdef CONFIG_BFIN_DCACHE
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_A_LENGTH (0x4000 - 0x4000)
#define BLKFIN_DCACHESIZE (16*1024) #define BFIN_DCACHESIZE (16*1024)
#define BLKFIN_DSUPBANKS 1 #define BFIN_DSUPBANKS 1
#else #else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x4000 #define L1_DATA_A_LENGTH 0x4000
#define BLKFIN_DCACHESIZE (0*1024) #define BFIN_DCACHESIZE (0*1024)
#define BLKFIN_DSUPBANKS 0 #define BFIN_DSUPBANKS 0
#endif #endif
#endif #endif

1
include/asm-blackfin/mach-bf537/anomaly.h
View File

@ -133,6 +133,7 @@
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0) #define ANOMALY_05000125 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000183 (0) #define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000266 (0) #define ANOMALY_05000266 (0)

67
include/asm-blackfin/mach-bf537/bf537.h
View File

@ -62,12 +62,12 @@
/***************************/ /***************************/
#define BLKFIN_DSUBBANKS 4 #define BFIN_DSUBBANKS 4
#define BLKFIN_DWAYS 2 #define BFIN_DWAYS 2
#define BLKFIN_DLINES 64 #define BFIN_DLINES 64
#define BLKFIN_ISUBBANKS 4 #define BFIN_ISUBBANKS 4
#define BLKFIN_IWAYS 4 #define BFIN_IWAYS 4
#define BLKFIN_ILINES 32 #define BFIN_ILINES 32
#define WAY0_L 0x1 #define WAY0_L 0x1
#define WAY1_L 0x2 #define WAY1_L 0x2
@ -138,59 +138,4 @@
#define CPUID 0x0 #define CPUID 0x0
#endif #endif
#if (CONFIG_MEM_SIZE % 4)
#error "SDRAM mem size must be multible of 4MB"
#endif
#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
#define ANOMALY_05000158_WORKAROUND 0x200
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#else /*Write Through */
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
#endif
#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
#define SIZE_1K 0x00000400 /* 1K */
#define SIZE_4K 0x00001000 /* 4K */
#define SIZE_1M 0x00100000 /* 1M */
#define SIZE_4M 0x00400000 /* 4M */
#define MAX_CPLBS (16 * 2)
/*
* Number of required data CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Data Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
* 1 for ASYNC Memory
*/
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
/*
* Number of required instruction CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Instruction Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
*/
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
#endif /* __MACH_BF537_H__ */ #endif /* __MACH_BF537_H__ */

60
include/asm-blackfin/mach-bf537/mem_map.h
View File

@ -52,10 +52,10 @@
/* Memory Map for ADSP-BF537 processors */ /* Memory Map for ADSP-BF537 processors */
#ifdef CONFIG_BLKFIN_CACHE #ifdef CONFIG_BFIN_ICACHE
#define BLKFIN_ICACHESIZE (16*1024) #define BFIN_ICACHESIZE (16*1024)
#else #else
#define BLKFIN_ICACHESIZE (0*1024) #define BFIN_ICACHESIZE (0*1024)
#endif #endif
@ -66,29 +66,29 @@
#define L1_CODE_LENGTH 0xC000 #define L1_CODE_LENGTH 0xC000
#ifdef CONFIG_BLKFIN_DCACHE #ifdef CONFIG_BFIN_DCACHE
#ifdef CONFIG_BLKFIN_DCACHE_BANKA #ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000
#define BLKFIN_DCACHESIZE (16*1024) #define BFIN_DCACHESIZE (16*1024)
#define BLKFIN_DSUPBANKS 1 #define BFIN_DSUPBANKS 1
#else #else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000)
#define BLKFIN_DCACHESIZE (32*1024) #define BFIN_DCACHESIZE (32*1024)
#define BLKFIN_DSUPBANKS 2 #define BFIN_DSUPBANKS 2
#endif #endif
#else #else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_A_LENGTH 0x8000
#define L1_DATA_B_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000
#define BLKFIN_DCACHESIZE (0*1024) #define BFIN_DCACHESIZE (0*1024)
#define BLKFIN_DSUPBANKS 0 #define BFIN_DSUPBANKS 0
#endif /*CONFIG_BLKFIN_DCACHE*/ #endif /*CONFIG_BFIN_DCACHE*/
#endif /*CONFIG_BF537*/ #endif /*CONFIG_BF537*/
@ -102,30 +102,30 @@
#define L1_CODE_LENGTH 0xC000 #define L1_CODE_LENGTH 0xC000
#ifdef CONFIG_BLKFIN_DCACHE #ifdef CONFIG_BFIN_DCACHE
#ifdef CONFIG_BLKFIN_DCACHE_BANKA #ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_A_LENGTH (0x4000 - 0x4000)
#define L1_DATA_B_LENGTH 0x4000 #define L1_DATA_B_LENGTH 0x4000
#define BLKFIN_DCACHESIZE (16*1024) #define BFIN_DCACHESIZE (16*1024)
#define BLKFIN_DSUPBANKS 1 #define BFIN_DSUPBANKS 1
#else #else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_A_LENGTH (0x4000 - 0x4000)
#define L1_DATA_B_LENGTH (0x4000 - 0x4000) #define L1_DATA_B_LENGTH (0x4000 - 0x4000)
#define BLKFIN_DCACHESIZE (32*1024) #define BFIN_DCACHESIZE (32*1024)
#define BLKFIN_DSUPBANKS 2 #define BFIN_DSUPBANKS 2
#endif #endif
#else #else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x4000 #define L1_DATA_A_LENGTH 0x4000
#define L1_DATA_B_LENGTH 0x4000 #define L1_DATA_B_LENGTH 0x4000
#define BLKFIN_DCACHESIZE (0*1024) #define BFIN_DCACHESIZE (0*1024)
#define BLKFIN_DSUPBANKS 0 #define BFIN_DSUPBANKS 0
#endif /*CONFIG_BLKFIN_DCACHE*/ #endif /*CONFIG_BFIN_DCACHE*/
#endif #endif
@ -138,30 +138,30 @@
#define L1_CODE_LENGTH 0xC000 #define L1_CODE_LENGTH 0xC000
#ifdef CONFIG_BLKFIN_DCACHE #ifdef CONFIG_BFIN_DCACHE
#ifdef CONFIG_BLKFIN_DCACHE_BANKA #ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000
#define BLKFIN_DCACHESIZE (16*1024) #define BFIN_DCACHESIZE (16*1024)
#define BLKFIN_DSUPBANKS 1 #define BFIN_DSUPBANKS 1
#else #else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000)
#define BLKFIN_DCACHESIZE (32*1024) #define BFIN_DCACHESIZE (32*1024)
#define BLKFIN_DSUPBANKS 2 #define BFIN_DSUPBANKS 2
#endif #endif
#else #else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_A_LENGTH 0x8000
#define L1_DATA_B_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000
#define BLKFIN_DCACHESIZE (0*1024) #define BFIN_DCACHESIZE (0*1024)
#define BLKFIN_DSUPBANKS 0 #define BFIN_DSUPBANKS 0
#endif /*CONFIG_BLKFIN_DCACHE*/ #endif /*CONFIG_BFIN_DCACHE*/
#endif #endif

67
include/asm-blackfin/mach-bf548/bf548.h
View File

@ -52,12 +52,12 @@
/***************************/ /***************************/
#define BLKFIN_DSUBBANKS 4 #define BFIN_DSUBBANKS 4
#define BLKFIN_DWAYS 2 #define BFIN_DWAYS 2
#define BLKFIN_DLINES 64 #define BFIN_DLINES 64
#define BLKFIN_ISUBBANKS 4 #define BFIN_ISUBBANKS 4
#define BLKFIN_IWAYS 4 #define BFIN_IWAYS 4
#define BLKFIN_ILINES 32 #define BFIN_ILINES 32
#define WAY0_L 0x1 #define WAY0_L 0x1
#define WAY1_L 0x2 #define WAY1_L 0x2
@ -126,59 +126,4 @@
#define CPUID 0x0 #define CPUID 0x0
#endif #endif
#if (CONFIG_MEM_SIZE % 4)
#error "SDRAM mem size must be multible of 4MB"
#endif
#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
#define ANOMALY_05000158_WORKAROUND 0x200
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#else /*Write Through */
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
#endif
#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
#define SIZE_1K 0x00000400 /* 1K */
#define SIZE_4K 0x00001000 /* 4K */
#define SIZE_1M 0x00100000 /* 1M */
#define SIZE_4M 0x00400000 /* 4M */
#define MAX_CPLBS (16 * 2)
/*
* Number of required data CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Data Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
* 1 for ASYNC Memory
*/
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
/*
* Number of required instruction CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Instruction Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
*/
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
#endif /* __MACH_BF48_H__ */ #endif /* __MACH_BF48_H__ */

24
include/asm-blackfin/mach-bf548/mem_map.h
View File

@ -51,10 +51,10 @@
/* Level 1 Memory */ /* Level 1 Memory */
/* Memory Map for ADSP-BF548 processors */ /* Memory Map for ADSP-BF548 processors */
#ifdef CONFIG_BLKFIN_ICACHE #ifdef CONFIG_BFIN_ICACHE
#define BLKFIN_ICACHESIZE (16*1024) #define BFIN_ICACHESIZE (16*1024)
#else #else
#define BLKFIN_ICACHESIZE (0*1024) #define BFIN_ICACHESIZE (0*1024)
#endif #endif
#define L1_CODE_START 0xFFA00000 #define L1_CODE_START 0xFFA00000
@ -63,29 +63,29 @@
#define L1_CODE_LENGTH 0xC000 #define L1_CODE_LENGTH 0xC000
#ifdef CONFIG_BLKFIN_DCACHE #ifdef CONFIG_BFIN_DCACHE
#ifdef CONFIG_BLKFIN_DCACHE_BANKA #ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000
#define BLKFIN_DCACHESIZE (16*1024) #define BFIN_DCACHESIZE (16*1024)
#define BLKFIN_DSUPBANKS 1 #define BFIN_DSUPBANKS 1
#else #else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000)
#define BLKFIN_DCACHESIZE (32*1024) #define BFIN_DCACHESIZE (32*1024)
#define BLKFIN_DSUPBANKS 2 #define BFIN_DSUPBANKS 2
#endif #endif
#else #else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_A_LENGTH 0x8000
#define L1_DATA_B_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000
#define BLKFIN_DCACHESIZE (0*1024) #define BFIN_DCACHESIZE (0*1024)
#define BLKFIN_DSUPBANKS 0 #define BFIN_DSUPBANKS 0
#endif /*CONFIG_BLKFIN_DCACHE*/ #endif /*CONFIG_BFIN_DCACHE*/
/* Scratch Pad Memory */ /* Scratch Pad Memory */

91
include/asm-blackfin/mach-bf561/bf561.h
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@ -73,13 +73,13 @@
*/ */
#define BLKFIN_ISUBBANKS 4 #define BFIN_ISUBBANKS 4
#define BLKFIN_IWAYS 4 #define BFIN_IWAYS 4
#define BLKFIN_ILINES 32 #define BFIN_ILINES 32
#define BLKFIN_DSUBBANKS 4 #define BFIN_DSUBBANKS 4
#define BLKFIN_DWAYS 2 #define BFIN_DWAYS 2
#define BLKFIN_DLINES 64 #define BFIN_DLINES 64
#define WAY0_L 0x1 #define WAY0_L 0x1
#define WAY1_L 0x2 #define WAY1_L 0x2
@ -239,83 +239,4 @@
#define CPUID 0x0 #define CPUID 0x0
#endif #endif
#if (CONFIG_MEM_SIZE % 4)
#error "SDRAM memory size must be a multiple of 4MB!"
#endif
#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
#define ANOMALY_05000158_WORKAROUND 0x200
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#else /*Write Through */
#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
| CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#endif
#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
#define L2_MEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
#define SIZE_1K 0x00000400 /* 1K */
#define SIZE_4K 0x00001000 /* 4K */
#define SIZE_1M 0x00100000 /* 1M */
#define SIZE_4M 0x00400000 /* 4M */
#define MAX_CPLBS (16 * 2)
/*
* Number of required data CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Data Memory
* 1 for L2 Data Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
* 64 for ASYNC Memory
*/
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 + 64) * 2)
/*
* Number of required instruction CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Instruction Memory
* 1 for L2 Instruction Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
*/
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
#if 0 /* comment by mhfan */
/* Event Vector Table Address */
#define EVT_EMULATION_ADDR 0xffe02000
#define EVT_RESET_ADDR 0xffe02004
#define EVT_NMI_ADDR 0xffe02008
#define EVT_EXCEPTION_ADDR 0xffe0200c
#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
#define EVT_TIMER_ADDR 0xffe02018
#define EVT_IVG7_ADDR 0xffe0201c
#define EVT_IVG8_ADDR 0xffe02020
#define EVT_IVG9_ADDR 0xffe02024
#define EVT_IVG10_ADDR 0xffe02028
#define EVT_IVG11_ADDR 0xffe0202c
#define EVT_IVG12_ADDR 0xffe02030
#define EVT_IVG13_ADDR 0xffe02034
#define EVT_IVG14_ADDR 0xffe02038
#define EVT_IVG15_ADDR 0xffe0203c
#define EVT_OVERRIDE_ADDR 0xffe02100
#endif /* comment by mhfan */
#endif /* __MACH_BF561_H__ */ #endif /* __MACH_BF561_H__ */

24
include/asm-blackfin/mach-bf561/mem_map.h
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@ -21,10 +21,10 @@
/* Level 1 Memory */ /* Level 1 Memory */
#ifdef CONFIG_BLKFIN_CACHE #ifdef CONFIG_BFIN_ICACHE
#define BLKFIN_ICACHESIZE (16*1024) #define BFIN_ICACHESIZE (16*1024)
#else #else
#define BLKFIN_ICACHESIZE (0*1024) #define BFIN_ICACHESIZE (0*1024)
#endif #endif
/* Memory Map for ADSP-BF561 processors */ /* Memory Map for ADSP-BF561 processors */
@ -36,29 +36,29 @@
#define L1_CODE_LENGTH 0x4000 #define L1_CODE_LENGTH 0x4000
#ifdef CONFIG_BLKFIN_DCACHE #ifdef CONFIG_BFIN_DCACHE
#ifdef CONFIG_BLKFIN_DCACHE_BANKA #ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000
#define BLKFIN_DCACHESIZE (16*1024) #define BFIN_DCACHESIZE (16*1024)
#define BLKFIN_DSUPBANKS 1 #define BFIN_DSUPBANKS 1
#else #else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000)
#define BLKFIN_DCACHESIZE (32*1024) #define BFIN_DCACHESIZE (32*1024)
#define BLKFIN_DSUPBANKS 2 #define BFIN_DSUPBANKS 2
#endif #endif
#else #else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_A_LENGTH 0x8000
#define L1_DATA_B_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000
#define BLKFIN_DCACHESIZE (0*1024) #define BFIN_DCACHESIZE (0*1024)
#define BLKFIN_DSUPBANKS 0 #define BFIN_DSUPBANKS 0
#endif /*CONFIG_BLKFIN_DCACHE*/ #endif /*CONFIG_BFIN_DCACHE*/
#endif #endif
/* Level 2 Memory */ /* Level 2 Memory */

4
include/asm-blackfin/mach-common/clocks.h
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@ -27,7 +27,8 @@
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef _BFIN_CLOCKS_H
#define _BFIN_CLOCKS_H
#ifdef CONFIG_CCLK_DIV_1 #ifdef CONFIG_CCLK_DIV_1
# define CONFIG_CCLK_ACT_DIV CCLK_DIV1 # define CONFIG_CCLK_ACT_DIV CCLK_DIV1
@ -66,3 +67,4 @@
# define CONFIG_VCO_MULT 0 # define CONFIG_VCO_MULT 0
#endif #endif
#endif

3
include/asm-blackfin/mach-common/def_LPBlackfin.h
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@ -639,6 +639,7 @@
#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access #define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
* allowed (user mode) * allowed (user mode)
*/ */
#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ #define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
@ -671,6 +672,8 @@
*/ */
#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ #define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
/* TBUFCTL Masks */ /* TBUFCTL Masks */
#define TBUFPWR 0x0001 #define TBUFPWR 0x0001
#define TBUFEN 0x0002 #define TBUFEN 0x0002

2
include/asm-blackfin/pgtable.h
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@ -4,7 +4,7 @@
#include <asm-generic/4level-fixup.h> #include <asm-generic/4level-fixup.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/cplb.h> #include <asm/mach-common/def_LPBlackfin.h>
typedef pte_t *pte_addr_t; typedef pte_t *pte_addr_t;
/* /*

2
include/asm-blackfin/system.h
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@ -60,7 +60,7 @@ extern unsigned long irq_flags;
); \ ); \
} while (0) } while (0)
#if ANOMALY_05000244 && defined(CONFIG_BLKFIN_CACHE) #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
# define NOP_PAD_ANOMALY_05000244 "nop; nop;" # define NOP_PAD_ANOMALY_05000244 "nop; nop;"
#else #else
# define NOP_PAD_ANOMALY_05000244 # define NOP_PAD_ANOMALY_05000244