drm/amd/powerplay: add profiling mode in dpm level
In some case, App need to run under max stable clock. so export profiling mode: GFX CG was disabled. and user can select the max stable clock of the device. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -124,6 +124,7 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
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(level & AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
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(level & AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
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(level & AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
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(level & AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
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(level & AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
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(level & AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
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(level & AMD_DPM_FORCED_LEVEL_PROFILING) ? "profiling" :
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"unknown"));
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"unknown"));
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}
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}
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@ -135,6 +136,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = ddev->dev_private;
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struct amdgpu_device *adev = ddev->dev_private;
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enum amd_dpm_forced_level level;
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enum amd_dpm_forced_level level;
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enum amd_dpm_forced_level current_level;
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int ret = 0;
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int ret = 0;
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/* Can't force performance level when the card is off */
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/* Can't force performance level when the card is off */
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@ -142,6 +144,8 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
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(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
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(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
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return -EINVAL;
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return -EINVAL;
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current_level = amdgpu_dpm_get_performance_level(adev);
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if (strncmp("low", buf, strlen("low")) == 0) {
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if (strncmp("low", buf, strlen("low")) == 0) {
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level = AMD_DPM_FORCED_LEVEL_LOW;
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level = AMD_DPM_FORCED_LEVEL_LOW;
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} else if (strncmp("high", buf, strlen("high")) == 0) {
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} else if (strncmp("high", buf, strlen("high")) == 0) {
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@ -150,11 +154,24 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
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level = AMD_DPM_FORCED_LEVEL_AUTO;
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level = AMD_DPM_FORCED_LEVEL_AUTO;
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} else if (strncmp("manual", buf, strlen("manual")) == 0) {
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} else if (strncmp("manual", buf, strlen("manual")) == 0) {
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level = AMD_DPM_FORCED_LEVEL_MANUAL;
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level = AMD_DPM_FORCED_LEVEL_MANUAL;
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} else if (strncmp("profile", buf, strlen("profile")) == 0) {
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level = AMD_DPM_FORCED_LEVEL_PROFILING;
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} else {
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} else {
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count = -EINVAL;
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count = -EINVAL;
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goto fail;
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goto fail;
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}
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}
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if (current_level == level)
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return 0;
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if (level == AMD_DPM_FORCED_LEVEL_PROFILING)
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amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_UNGATE);
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else if (level != AMD_DPM_FORCED_LEVEL_PROFILING &&
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current_level == AMD_DPM_FORCED_LEVEL_PROFILING)
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amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_GATE);
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if (adev->pp_enabled)
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if (adev->pp_enabled)
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amdgpu_dpm_force_performance_level(adev, level);
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amdgpu_dpm_force_performance_level(adev, level);
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else {
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else {
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@ -6571,8 +6571,8 @@ static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
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{
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{
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struct ci_power_info *pi = ci_get_pi(adev);
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struct ci_power_info *pi = ci_get_pi(adev);
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if (adev->pm.dpm.forced_level
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if (!(adev->pm.dpm.forced_level &
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!= AMD_DPM_FORCED_LEVEL_MANUAL)
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(AMD_DPM_FORCED_LEVEL_MANUAL | AMD_DPM_FORCED_LEVEL_PROFILING)))
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return -EINVAL;
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return -EINVAL;
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switch (type) {
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switch (type) {
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@ -85,6 +85,7 @@ enum amd_dpm_forced_level {
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AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
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AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
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AMD_DPM_FORCED_LEVEL_LOW = 0x4,
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AMD_DPM_FORCED_LEVEL_LOW = 0x4,
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AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
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AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
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AMD_DPM_FORCED_LEVEL_PROFILING = 0x10,
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};
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};
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enum amd_powergating_state {
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enum amd_powergating_state {
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@ -1644,7 +1644,8 @@ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
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static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
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static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, uint32_t mask)
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enum pp_clock_type type, uint32_t mask)
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{
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{
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if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
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if (!(hwmgr->dpm_level &
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(AMD_DPM_FORCED_LEVEL_MANUAL | AMD_DPM_FORCED_LEVEL_PROFILING)))
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return -EINVAL;
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return -EINVAL;
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switch (type) {
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switch (type) {
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@ -4031,7 +4031,8 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
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{
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
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if (!(hwmgr->dpm_level &
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(AMD_DPM_FORCED_LEVEL_MANUAL | AMD_DPM_FORCED_LEVEL_PROFILING)))
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return -EINVAL;
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return -EINVAL;
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switch (type) {
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switch (type) {
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