Merge remote-tracking branches 'spi/topic/drivers', 'spi/topic/dw', 'spi/topic/efm32', 'spi/topic/ep93xx', 'spi/topic/fsl', 'spi/topic/fsl-dspi', 'spi/topic/fsl-espi' and 'spi/topic/gpio' into spi-next
This commit is contained in:
Mark Brown
parent
9dee279b40
23e2c2aa45
c63f5da008
12f6dd860c
56fc0b42dc
7282326b72
0e0cd9ea89
f0a71337be
e1bde3b11f
commit
3bcbc14911
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@ -3,24 +3,24 @@
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Required properties:
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- #address-cells: see spi-bus.txt
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- #size-cells: see spi-bus.txt
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- compatible: should be "efm32,spi"
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- compatible: should be "energymicro,efm32-spi"
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- reg: Offset and length of the register set for the controller
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- interrupts: pair specifying rx and tx irq
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- clocks: phandle to the spi clock
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- cs-gpios: see spi-bus.txt
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- location: Value to write to the ROUTE register's LOCATION bitfield to configure the pinmux for the device, see datasheet for values.
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- efm32,location: Value to write to the ROUTE register's LOCATION bitfield to configure the pinmux for the device, see datasheet for values.
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Example:
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spi1: spi@0x4000c400 { /* USART1 */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "efm32,spi";
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compatible = "energymicro,efm32-spi";
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reg = <0x4000c400 0x400>;
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interrupts = <15 16>;
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clocks = <&cmu 20>;
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cs-gpios = <&gpio 51 1>; // D3
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location = <1>;
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efm32,location = <1>;
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status = "ok";
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ks8851@0 {
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@ -10,6 +10,7 @@ Required properties:
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- pinctrl-names: must contain a "default" entry.
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- spi-num-chipselects : the number of the chipselect signals.
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- bus-num : the slave chip chipselect signal number.
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- big-endian : if DSPI modudle is big endian, the bool will be set in node.
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Example:
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dspi0@4002c000 {
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@ -24,6 +25,7 @@ dspi0@4002c000 {
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bus-num = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dspi0_1>;
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big-endian;
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status = "okay";
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sflash: at26df081a@0 {
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@ -270,6 +270,7 @@ config SPI_FSL_SPI
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config SPI_FSL_DSPI
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tristate "Freescale DSPI controller"
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select SPI_BITBANG
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select REGMAP_MMIO
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depends on SOC_VF610 || COMPILE_TEST
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help
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This enables support for the Freescale DSPI controller in master
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@ -546,7 +547,7 @@ config SPI_DW_MID_DMA
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config SPI_DW_MMIO
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tristate "Memory-mapped io interface driver for DW SPI core"
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depends on SPI_DESIGNWARE && HAVE_CLK
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depends on SPI_DESIGNWARE
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#
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# There are lots of SPI device types, with sensors and memory
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@ -66,7 +66,7 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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dws->bus_num = 0;
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dws->bus_num = pdev->id;
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dws->num_cs = 4;
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dws->max_freq = clk_get_rate(dwsmmio->clk);
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@ -276,8 +276,7 @@ static void giveback(struct dw_spi *dws)
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queue_work(dws->workqueue, &dws->pump_messages);
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spin_unlock_irqrestore(&dws->lock, flags);
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last_transfer = list_entry(msg->transfers.prev,
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struct spi_transfer,
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last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
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transfer_list);
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if (!last_transfer->cs_change && dws->cs_control)
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@ -439,12 +438,6 @@ static void pump_transfers(unsigned long data)
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if (transfer->speed_hz != speed) {
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speed = transfer->speed_hz;
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if (speed > dws->max_freq) {
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printk(KERN_ERR "MRST SPI0: unsupported"
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"freq: %dHz\n", speed);
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message->status = -EIO;
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goto early_exit;
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}
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/* clk_div doesn't support odd number */
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clk_div = dws->max_freq / speed;
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@ -671,12 +664,6 @@ static int dw_spi_setup(struct spi_device *spi)
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return 0;
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}
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static void dw_spi_cleanup(struct spi_device *spi)
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{
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struct chip_data *chip = spi_get_ctldata(spi);
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kfree(chip);
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}
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static int init_queue(struct dw_spi *dws)
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{
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INIT_LIST_HEAD(&dws->queue);
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@ -806,9 +793,9 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
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master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
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master->bus_num = dws->bus_num;
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master->num_chipselect = dws->num_cs;
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master->cleanup = dw_spi_cleanup;
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master->setup = dw_spi_setup;
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master->transfer = dw_spi_transfer;
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master->max_speed_hz = dws->max_freq;
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/* Basic HW init */
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spi_hw_init(dws);
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@ -287,17 +287,17 @@ static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata)
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return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK);
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}
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static int efm32_spi_probe_dt(struct platform_device *pdev,
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static void efm32_spi_probe_dt(struct platform_device *pdev,
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struct spi_master *master, struct efm32_spi_ddata *ddata)
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{
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struct device_node *np = pdev->dev.of_node;
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u32 location;
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int ret;
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if (!np)
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return 1;
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ret = of_property_read_u32(np, "location", &location);
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ret = of_property_read_u32(np, "efm32,location", &location);
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if (ret)
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/* fall back to old and (wrongly) generic property "location" */
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ret = of_property_read_u32(np, "location", &location);
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if (!ret) {
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dev_dbg(&pdev->dev, "using location %u\n", location);
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} else {
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@ -308,7 +308,6 @@ static int efm32_spi_probe_dt(struct platform_device *pdev,
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}
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ddata->pdata.location = location;
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return 0;
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}
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static int efm32_spi_probe(struct platform_device *pdev)
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@ -318,9 +317,14 @@ static int efm32_spi_probe(struct platform_device *pdev)
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int ret;
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struct spi_master *master;
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struct device_node *np = pdev->dev.of_node;
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unsigned int num_cs, i;
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int num_cs, i;
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if (!np)
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return -EINVAL;
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num_cs = of_gpio_named_count(np, "cs-gpios");
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if (num_cs < 0)
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return num_cs;
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master = spi_alloc_master(&pdev->dev,
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sizeof(*ddata) + num_cs * sizeof(unsigned));
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@ -412,23 +416,7 @@ static int efm32_spi_probe(struct platform_device *pdev)
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goto err;
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}
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ret = efm32_spi_probe_dt(pdev, master, ddata);
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if (ret > 0) {
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/* not created by device tree */
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const struct efm32_spi_pdata *pdata =
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dev_get_platdata(&pdev->dev);
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if (pdata)
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ddata->pdata = *pdata;
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else
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ddata->pdata.location =
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efm32_spi_get_configured_location(ddata);
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master->bus_num = pdev->id;
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} else if (ret < 0) {
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goto err_disable_clk;
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}
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efm32_spi_probe_dt(pdev, master, ddata);
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efm32_spi_write32(ddata, 0, REG_IEN);
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efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN |
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@ -484,6 +472,9 @@ static int efm32_spi_remove(struct platform_device *pdev)
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static const struct of_device_id efm32_spi_dt_ids[] = {
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{
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.compatible = "energymicro,efm32-spi",
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}, {
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/* doesn't follow the "vendor,device" scheme, don't use */
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.compatible = "efm32,spi",
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}, {
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/* sentinel */
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@ -73,8 +73,6 @@
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* @clk: clock for the controller
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* @regs_base: pointer to ioremap()'d registers
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* @sspdr_phys: physical address of the SSPDR register
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* @min_rate: minimum clock rate (in Hz) supported by the controller
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* @max_rate: maximum clock rate (in Hz) supported by the controller
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* @wait: wait here until given transfer is completed
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* @current_msg: message that is currently processed (or %NULL if none)
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* @tx: current byte in transfer to transmit
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@ -95,8 +93,6 @@ struct ep93xx_spi {
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struct clk *clk;
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void __iomem *regs_base;
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unsigned long sspdr_phys;
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unsigned long min_rate;
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unsigned long max_rate;
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struct completion wait;
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struct spi_message *current_msg;
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size_t tx;
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@ -199,9 +195,9 @@ static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
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* @div_scr: pointer to return the scr divider
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*/
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static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
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unsigned long rate,
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u8 *div_cpsr, u8 *div_scr)
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u32 rate, u8 *div_cpsr, u8 *div_scr)
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{
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struct spi_master *master = platform_get_drvdata(espi->pdev);
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unsigned long spi_clk_rate = clk_get_rate(espi->clk);
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int cpsr, scr;
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@ -210,7 +206,7 @@ static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
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* controller. Note that minimum value is already checked in
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* ep93xx_spi_transfer_one_message().
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*/
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rate = clamp(rate, espi->min_rate, espi->max_rate);
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rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);
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/*
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* Calculate divisors so that we can get speed according the
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@ -735,13 +731,6 @@ static int ep93xx_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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struct spi_transfer *t;
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/* first validate each transfer */
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list_for_each_entry(t, &msg->transfers, transfer_list) {
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if (t->speed_hz < espi->min_rate)
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return -EINVAL;
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}
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msg->state = NULL;
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msg->status = 0;
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@ -917,8 +906,8 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
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* Calculate maximum and minimum supported clock rates
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* for the controller.
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*/
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espi->max_rate = clk_get_rate(espi->clk) / 2;
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espi->min_rate = clk_get_rate(espi->clk) / (254 * 256);
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master->max_speed_hz = clk_get_rate(espi->clk) / 2;
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master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
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espi->pdev = pdev;
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espi->sspdr_phys = res->start + SSPDR;
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@ -18,6 +18,7 @@
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/sched.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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@ -108,11 +109,11 @@ struct fsl_dspi {
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struct spi_bitbang bitbang;
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struct platform_device *pdev;
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void __iomem *base;
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struct regmap *regmap;
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int irq;
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struct clk *clk;
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struct clk *clk;
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struct spi_transfer *cur_transfer;
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struct spi_transfer *cur_transfer;
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struct chip_data *cur_chip;
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size_t len;
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void *tx;
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@ -123,24 +124,17 @@ struct fsl_dspi {
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u8 cs;
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u16 void_write_data;
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wait_queue_head_t waitq;
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u32 waitflags;
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wait_queue_head_t waitq;
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u32 waitflags;
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};
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static inline int is_double_byte_mode(struct fsl_dspi *dspi)
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{
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return ((readl(dspi->base + SPI_CTAR(dspi->cs)) & SPI_FRAME_BITS_MASK)
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== SPI_FRAME_BITS(8)) ? 0 : 1;
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}
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unsigned int val;
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static void set_bit_mode(struct fsl_dspi *dspi, unsigned char bits)
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{
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u32 temp;
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regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
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temp = readl(dspi->base + SPI_CTAR(dspi->cs));
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temp &= ~SPI_FRAME_BITS_MASK;
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temp |= SPI_FRAME_BITS(bits);
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writel(temp, dspi->base + SPI_CTAR(dspi->cs));
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return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
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}
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static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
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@ -188,7 +182,8 @@ static int dspi_transfer_write(struct fsl_dspi *dspi)
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*/
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if (tx_word && (dspi->len == 1)) {
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dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
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set_bit_mode(dspi, 8);
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regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
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SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
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tx_word = 0;
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}
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@ -238,7 +233,8 @@ static int dspi_transfer_write(struct fsl_dspi *dspi)
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dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
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}
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writel(dspi_pushr, dspi->base + SPI_PUSHR);
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regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
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tx_count++;
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}
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@ -253,17 +249,23 @@ static int dspi_transfer_read(struct fsl_dspi *dspi)
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while ((dspi->rx < dspi->rx_end)
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&& (rx_count < DSPI_FIFO_SIZE)) {
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if (rx_word) {
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unsigned int val;
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if ((dspi->rx_end - dspi->rx) == 1)
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break;
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d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR));
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regmap_read(dspi->regmap, SPI_POPR, &val);
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d = SPI_POPR_RXDATA(val);
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if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
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*(u16 *)dspi->rx = d;
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dspi->rx += 2;
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} else {
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d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR));
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unsigned int val;
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regmap_read(dspi->regmap, SPI_POPR, &val);
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d = SPI_POPR_RXDATA(val);
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if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
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*(u8 *)dspi->rx = d;
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dspi->rx++;
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|
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@ -295,13 +297,13 @@ static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
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if (!dspi->tx)
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dspi->dataflags |= TRAN_STATE_TX_VOID;
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writel(dspi->cur_chip->mcr_val, dspi->base + SPI_MCR);
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writel(dspi->cur_chip->ctar_val, dspi->base + SPI_CTAR(dspi->cs));
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writel(SPI_RSER_EOQFE, dspi->base + SPI_RSER);
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regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
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regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi->cur_chip->ctar_val);
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regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
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if (t->speed_hz)
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writel(dspi->cur_chip->ctar_val,
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dspi->base + SPI_CTAR(dspi->cs));
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regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
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dspi->cur_chip->ctar_val);
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dspi_transfer_write(dspi);
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|
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|
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@ -315,7 +317,9 @@ static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
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static void dspi_chipselect(struct spi_device *spi, int value)
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{
|
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struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
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u32 pushr = readl(dspi->base + SPI_PUSHR);
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unsigned int pushr;
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regmap_read(dspi->regmap, SPI_PUSHR, &pushr);
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|
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switch (value) {
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case BITBANG_CS_ACTIVE:
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|
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@ -326,7 +330,7 @@ static void dspi_chipselect(struct spi_device *spi, int value)
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break;
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}
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writel(pushr, dspi->base + SPI_PUSHR);
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regmap_write(dspi->regmap, SPI_PUSHR, pushr);
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}
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|
||||
static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
|
||||
|
|
@ -338,7 +342,8 @@ static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
|
|||
/* Only alloc on first setup */
|
||||
chip = spi_get_ctldata(spi);
|
||||
if (chip == NULL) {
|
||||
chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL);
|
||||
chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data),
|
||||
GFP_KERNEL);
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
|
@ -349,7 +354,6 @@ static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
|
|||
fmsz = spi->bits_per_word - 1;
|
||||
} else {
|
||||
pr_err("Invalid wordsize\n");
|
||||
kfree(chip);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
|
|
@ -382,13 +386,15 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)
|
|||
{
|
||||
struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
|
||||
|
||||
writel(SPI_SR_EOQF, dspi->base + SPI_SR);
|
||||
regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
|
||||
|
||||
dspi_transfer_read(dspi);
|
||||
|
||||
if (!dspi->len) {
|
||||
if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
|
||||
set_bit_mode(dspi, 16);
|
||||
regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
|
||||
SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
|
||||
|
||||
dspi->waitflags = 1;
|
||||
wake_up_interruptible(&dspi->waitq);
|
||||
} else {
|
||||
|
|
@ -430,8 +436,13 @@ static int dspi_resume(struct device *dev)
|
|||
}
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
static const struct dev_pm_ops dspi_pm = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(dspi_suspend, dspi_resume)
|
||||
static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
|
||||
|
||||
static struct regmap_config dspi_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = 0x88,
|
||||
};
|
||||
|
||||
static int dspi_probe(struct platform_device *pdev)
|
||||
|
|
@ -440,6 +451,7 @@ static int dspi_probe(struct platform_device *pdev)
|
|||
struct spi_master *master;
|
||||
struct fsl_dspi *dspi;
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
int ret = 0, cs_num, bus_num;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
|
||||
|
|
@ -474,12 +486,24 @@ static int dspi_probe(struct platform_device *pdev)
|
|||
master->bus_num = bus_num;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
dspi->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(dspi->base)) {
|
||||
ret = PTR_ERR(dspi->base);
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base)) {
|
||||
ret = PTR_ERR(base);
|
||||
goto out_master_put;
|
||||
}
|
||||
|
||||
dspi_regmap_config.lock_arg = dspi;
|
||||
dspi_regmap_config.val_format_endian =
|
||||
of_property_read_bool(np, "big-endian")
|
||||
? REGMAP_ENDIAN_BIG : REGMAP_ENDIAN_DEFAULT;
|
||||
dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
|
||||
&dspi_regmap_config);
|
||||
if (IS_ERR(dspi->regmap)) {
|
||||
dev_err(&pdev->dev, "failed to init regmap: %ld\n",
|
||||
PTR_ERR(dspi->regmap));
|
||||
return PTR_ERR(dspi->regmap);
|
||||
}
|
||||
|
||||
dspi->irq = platform_get_irq(pdev, 0);
|
||||
if (dspi->irq < 0) {
|
||||
dev_err(&pdev->dev, "can't get platform irq\n");
|
||||
|
|
|
|||
|
|
@ -219,13 +219,8 @@ static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
|
|||
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
|
||||
struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
|
||||
unsigned int len = t->len;
|
||||
u8 bits_per_word;
|
||||
int ret;
|
||||
|
||||
bits_per_word = spi->bits_per_word;
|
||||
if (t->bits_per_word)
|
||||
bits_per_word = t->bits_per_word;
|
||||
|
||||
mpc8xxx_spi->len = t->len;
|
||||
len = roundup(len, 4) / 4;
|
||||
|
||||
|
|
|
|||
|
|
@ -200,7 +200,7 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
|
|||
const void *prop;
|
||||
int ret = -ENOMEM;
|
||||
|
||||
pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
|
||||
pinfo = devm_kzalloc(&ofdev->dev, sizeof(*pinfo), GFP_KERNEL);
|
||||
if (!pinfo)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
@ -215,15 +215,13 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
|
|||
pdata->sysclk = get_brgfreq();
|
||||
if (pdata->sysclk == -1) {
|
||||
pdata->sysclk = fsl_get_sys_freq();
|
||||
if (pdata->sysclk == -1) {
|
||||
ret = -ENODEV;
|
||||
goto err;
|
||||
}
|
||||
if (pdata->sysclk == -1)
|
||||
return -ENODEV;
|
||||
}
|
||||
#else
|
||||
ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk);
|
||||
if (ret)
|
||||
goto err;
|
||||
return ret;
|
||||
#endif
|
||||
|
||||
prop = of_get_property(np, "mode", NULL);
|
||||
|
|
@ -237,8 +235,4 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
|
|||
pdata->flags = SPI_CPM_MODE | SPI_CPM1;
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
kfree(pinfo);
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -239,12 +239,6 @@ static int fsl_spi_setup_transfer(struct spi_device *spi,
|
|||
if (!bits_per_word)
|
||||
bits_per_word = spi->bits_per_word;
|
||||
|
||||
/* Make sure its a bit width we support [4..16, 32] */
|
||||
if ((bits_per_word < 4)
|
||||
|| ((bits_per_word > 16) && (bits_per_word != 32))
|
||||
|| (bits_per_word > mpc8xxx_spi->max_bits_per_word))
|
||||
return -EINVAL;
|
||||
|
||||
if (!hz)
|
||||
hz = spi->max_speed_hz;
|
||||
|
||||
|
|
@ -362,18 +356,28 @@ static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
|
|||
static void fsl_spi_do_one_msg(struct spi_message *m)
|
||||
{
|
||||
struct spi_device *spi = m->spi;
|
||||
struct spi_transfer *t;
|
||||
struct spi_transfer *t, *first;
|
||||
unsigned int cs_change;
|
||||
const int nsecs = 50;
|
||||
int status;
|
||||
|
||||
/* Don't allow changes if CS is active */
|
||||
first = list_first_entry(&m->transfers, struct spi_transfer,
|
||||
transfer_list);
|
||||
list_for_each_entry(t, &m->transfers, transfer_list) {
|
||||
if ((first->bits_per_word != t->bits_per_word) ||
|
||||
(first->speed_hz != t->speed_hz)) {
|
||||
status = -EINVAL;
|
||||
dev_err(&spi->dev,
|
||||
"bits_per_word/speed_hz should be same for the same SPI transfer\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
cs_change = 1;
|
||||
status = 0;
|
||||
status = -EINVAL;
|
||||
list_for_each_entry(t, &m->transfers, transfer_list) {
|
||||
if (t->bits_per_word || t->speed_hz) {
|
||||
/* Don't allow changes if CS is active */
|
||||
status = -EINVAL;
|
||||
|
||||
if (cs_change)
|
||||
status = fsl_spi_setup_transfer(spi, t);
|
||||
if (status < 0)
|
||||
|
|
@ -641,6 +645,10 @@ static struct spi_master * fsl_spi_probe(struct device *dev,
|
|||
if (mpc8xxx_spi->type == TYPE_GRLIB)
|
||||
fsl_spi_grlib_probe(dev);
|
||||
|
||||
master->bits_per_word_mask =
|
||||
(SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
|
||||
SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
|
||||
|
||||
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
|
||||
mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
|
||||
|
||||
|
|
|
|||
|
|
@ -250,7 +250,7 @@ static int spi_gpio_setup(struct spi_device *spi)
|
|||
/*
|
||||
* ... otherwise, take it from spi->controller_data
|
||||
*/
|
||||
cs = (unsigned int) spi->controller_data;
|
||||
cs = (unsigned int)(uintptr_t) spi->controller_data;
|
||||
}
|
||||
|
||||
if (!spi->controller_state) {
|
||||
|
|
|
|||
|
|
@ -459,9 +459,8 @@ static void giveback(struct pl022 *pl022)
|
|||
struct spi_transfer *last_transfer;
|
||||
pl022->next_msg_cs_active = false;
|
||||
|
||||
last_transfer = list_entry(pl022->cur_msg->transfers.prev,
|
||||
struct spi_transfer,
|
||||
transfer_list);
|
||||
last_transfer = list_last_entry(&pl022->cur_msg->transfers,
|
||||
struct spi_transfer, transfer_list);
|
||||
|
||||
/* Delay if requested before any change in chip select */
|
||||
if (last_transfer->delay_usecs)
|
||||
|
|
|
|||
|
|
@ -362,8 +362,7 @@ static void giveback(struct driver_data *drv_data)
|
|||
drv_data->cur_msg = NULL;
|
||||
drv_data->cur_transfer = NULL;
|
||||
|
||||
last_transfer = list_entry(msg->transfers.prev,
|
||||
struct spi_transfer,
|
||||
last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
|
||||
transfer_list);
|
||||
|
||||
/* Delay if requested before any change in chip select */
|
||||
|
|
|
|||
Loading…
Reference in New Issue