Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer fixes from Ingo Molnar: "Misc fixes: a /dev/rtc regression fix, two APIC timer period calibration fixes, an ARM clocksource driver fix and a NOHZ power use regression fix" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/hpet: Fix /dev/rtc breakage caused by RTC cleanup x86/timers/apic: Inform TSC deadline clockevent device about recalibration x86/timers/apic: Fix imprecise timer interrupts by eliminating TSC clockevents frequency roundoff error timers: Fix get_next_timer_interrupt() computation clocksource/arm_arch_timer: Force per-CPU interrupt to be level-triggered
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3bc6d8c155
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@ -135,6 +135,7 @@ extern void init_apic_mappings(void);
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void register_lapic_address(unsigned long address);
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extern void setup_boot_APIC_clock(void);
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extern void setup_secondary_APIC_clock(void);
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extern void lapic_update_tsc_freq(void);
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extern int APIC_init_uniprocessor(void);
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#ifdef CONFIG_X86_64
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@ -170,6 +171,7 @@ static inline void init_apic_mappings(void) { }
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static inline void disable_local_APIC(void) { }
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# define setup_boot_APIC_clock x86_init_noop
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# define setup_secondary_APIC_clock x86_init_noop
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static inline void lapic_update_tsc_freq(void) { }
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#endif /* !CONFIG_X86_LOCAL_APIC */
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#ifdef CONFIG_X86_X2APIC
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@ -313,7 +313,7 @@ int lapic_get_maxlvt(void)
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/* Clock divisor */
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#define APIC_DIVISOR 16
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#define TSC_DIVISOR 32
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#define TSC_DIVISOR 8
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/*
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* This function sets up the local APIC timer, with a timeout of
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@ -565,12 +565,36 @@ static void setup_APIC_timer(void)
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CLOCK_EVT_FEAT_DUMMY);
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levt->set_next_event = lapic_next_deadline;
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clockevents_config_and_register(levt,
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(tsc_khz / TSC_DIVISOR) * 1000,
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tsc_khz * (1000 / TSC_DIVISOR),
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0xF, ~0UL);
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} else
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clockevents_register_device(levt);
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}
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/*
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* Install the updated TSC frequency from recalibration at the TSC
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* deadline clockevent devices.
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*/
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static void __lapic_update_tsc_freq(void *info)
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{
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struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
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if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
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return;
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clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
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}
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void lapic_update_tsc_freq(void)
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{
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/*
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* The clockevent device's ->mult and ->shift can both be
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* changed. In order to avoid races, schedule the frequency
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* update code on each CPU.
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*/
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on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
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}
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/*
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* In this functions we calibrate APIC bus clocks to the external timer.
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*
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@ -1242,7 +1242,7 @@ irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
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memset(&curr_time, 0, sizeof(struct rtc_time));
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if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
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mc146818_set_time(&curr_time);
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mc146818_get_time(&curr_time);
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if (hpet_rtc_flags & RTC_UIE &&
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curr_time.tm_sec != hpet_prev_update_sec) {
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@ -22,6 +22,7 @@
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#include <asm/nmi.h>
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#include <asm/x86_init.h>
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#include <asm/geode.h>
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#include <asm/apic.h>
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unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
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EXPORT_SYMBOL(cpu_khz);
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@ -1249,6 +1250,9 @@ static void tsc_refine_calibration_work(struct work_struct *work)
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(unsigned long)tsc_khz / 1000,
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(unsigned long)tsc_khz % 1000);
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/* Inform the TSC deadline clockevent devices about the recalibration */
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lapic_update_tsc_freq();
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out:
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if (boot_cpu_has(X86_FEATURE_ART))
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art_related_clocksource = &clocksource_tsc;
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@ -8,6 +8,9 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) "arm_arch_timer: " fmt
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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@ -370,16 +373,33 @@ static bool arch_timer_has_nonsecure_ppi(void)
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arch_timer_ppi[PHYS_NONSECURE_PPI]);
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}
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static u32 check_ppi_trigger(int irq)
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{
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u32 flags = irq_get_trigger_type(irq);
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if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
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pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
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pr_warn("WARNING: Please fix your firmware\n");
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flags = IRQF_TRIGGER_LOW;
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}
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return flags;
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}
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static int arch_timer_starting_cpu(unsigned int cpu)
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{
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struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
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u32 flags;
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__arch_timer_setup(ARCH_CP15_TIMER, clk);
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enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], 0);
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flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
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enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
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if (arch_timer_has_nonsecure_ppi())
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enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
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if (arch_timer_has_nonsecure_ppi()) {
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flags = check_ppi_trigger(arch_timer_ppi[PHYS_NONSECURE_PPI]);
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enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], flags);
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}
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arch_counter_set_user_access();
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if (evtstrm_enable)
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@ -1496,6 +1496,7 @@ u64 get_next_timer_interrupt(unsigned long basej, u64 basem)
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struct timer_base *base = this_cpu_ptr(&timer_bases[BASE_STD]);
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u64 expires = KTIME_MAX;
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unsigned long nextevt;
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bool is_max_delta;
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/*
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* Pretend that there is no timer pending if the cpu is offline.
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@ -1506,6 +1507,7 @@ u64 get_next_timer_interrupt(unsigned long basej, u64 basem)
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spin_lock(&base->lock);
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nextevt = __next_timer_interrupt(base);
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is_max_delta = (nextevt == base->clk + NEXT_TIMER_MAX_DELTA);
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base->next_expiry = nextevt;
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/*
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* We have a fresh next event. Check whether we can forward the base:
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@ -1519,7 +1521,8 @@ u64 get_next_timer_interrupt(unsigned long basej, u64 basem)
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expires = basem;
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base->is_idle = false;
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} else {
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expires = basem + (nextevt - basej) * TICK_NSEC;
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if (!is_max_delta)
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expires = basem + (nextevt - basej) * TICK_NSEC;
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/*
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* If we expect to sleep more than a tick, mark the base idle:
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*/
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