spi: sprd: Add ADI r3 support
ADI r3p0 is used on SC9863 and UMS512 SoCs. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Link: https://lore.kernel.org/r/20210826091549.2138125-3-zhang.lyra@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Chunyan Zhang
Mark Brown
parent
245ca2cc21
commit
3b66ca9783
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@ -52,10 +52,20 @@
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/*
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* ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
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* The slave devices address offset is always 0x8000 and size is 4K.
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* ADI supports 12/14bit address for r2p0, and additional 17bit for r3p0 or
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* later versions. Since bit[1:0] are zero, so the spec describe them as
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* 10/12/15bit address mode.
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* The 10bit mode supports sigle slave, 12/15bit mode supports 3 slave, the
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* high two bits is slave_id.
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* The slave devices address offset is 0x8000 for 10/12bit address mode,
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* and 0x20000 for 15bit mode.
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*/
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#define ADI_SLAVE_ADDR_SIZE SZ_4K
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#define ADI_SLAVE_OFFSET 0x8000
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#define ADI_10BIT_SLAVE_ADDR_SIZE SZ_4K
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#define ADI_10BIT_SLAVE_OFFSET 0x8000
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#define ADI_12BIT_SLAVE_ADDR_SIZE SZ_16K
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#define ADI_12BIT_SLAVE_OFFSET 0x8000
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#define ADI_15BIT_SLAVE_ADDR_SIZE SZ_128K
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#define ADI_15BIT_SLAVE_OFFSET 0x20000
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/* Timeout (ms) for the trylock of hardware spinlocks */
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#define ADI_HWSPINLOCK_TIMEOUT 5000
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@ -67,24 +77,35 @@
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#define ADI_FIFO_DRAIN_TIMEOUT 1000
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#define ADI_READ_TIMEOUT 2000
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#define REG_ADDR_LOW_MASK GENMASK(11, 0)
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/*
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* Read back address from REG_ADI_RD_DATA bit[30:16] which maps to:
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* REG_ADI_RD_CMD bit[14:0] for r2p0
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* REG_ADI_RD_CMD bit[16:2] for r3p0
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*/
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#define RDBACK_ADDR_MASK_R2 GENMASK(14, 0)
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#define RDBACK_ADDR_MASK_R3 GENMASK(16, 2)
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#define RDBACK_ADDR_SHIFT_R3 2
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/* Registers definitions for PMIC watchdog controller */
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#define REG_WDG_LOAD_LOW 0x80
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#define REG_WDG_LOAD_HIGH 0x84
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#define REG_WDG_CTRL 0x88
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#define REG_WDG_LOCK 0xa0
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#define REG_WDG_LOAD_LOW 0x0
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#define REG_WDG_LOAD_HIGH 0x4
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#define REG_WDG_CTRL 0x8
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#define REG_WDG_LOCK 0x20
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/* Bits definitions for register REG_WDG_CTRL */
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#define BIT_WDG_RUN BIT(1)
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#define BIT_WDG_NEW BIT(2)
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#define BIT_WDG_RST BIT(3)
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/* Bits definitions for register REG_MODULE_EN */
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#define BIT_WDG_EN BIT(2)
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/* Registers definitions for PMIC */
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#define PMIC_RST_STATUS 0xee8
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#define PMIC_MODULE_EN 0xc08
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#define PMIC_CLK_EN 0xc18
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#define BIT_WDG_EN BIT(2)
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#define PMIC_WDG_BASE 0x80
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/* Definition of PMIC reset status register */
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#define HWRST_STATUS_SECURITY 0x02
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@ -107,6 +128,22 @@
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#define WDG_LOAD_MASK GENMASK(15, 0)
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#define WDG_UNLOCK_KEY 0xe551
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struct sprd_adi_wdg {
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u32 base;
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u32 rst_sts;
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u32 wdg_en;
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u32 wdg_clk;
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};
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struct sprd_adi_data {
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u32 slave_offset;
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u32 slave_addr_size;
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int (*read_check)(u32 val, u32 reg);
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int (*restart)(struct notifier_block *this,
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unsigned long mode, void *cmd);
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void (*wdg_rst)(void *p);
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};
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struct sprd_adi {
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struct spi_controller *ctlr;
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struct device *dev;
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@ -115,11 +152,12 @@ struct sprd_adi {
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unsigned long slave_vbase;
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unsigned long slave_pbase;
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struct notifier_block restart_handler;
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const struct sprd_adi_data *data;
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};
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static int sprd_adi_check_addr(struct sprd_adi *sadi, u32 reg)
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{
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if (reg >= ADI_SLAVE_ADDR_SIZE) {
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if (reg >= sadi->data->slave_addr_size) {
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dev_err(sadi->dev,
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"slave address offset is incorrect, reg = 0x%x\n",
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reg);
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@ -155,11 +193,35 @@ static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
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return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
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}
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static int sprd_adi_read_check(u32 val, u32 addr)
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{
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u32 rd_addr;
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rd_addr = (val & RD_ADDR_MASK) >> RD_ADDR_SHIFT;
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if (rd_addr != addr) {
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pr_err("ADI read error, addr = 0x%x, val = 0x%x\n", addr, val);
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return -EIO;
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}
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return 0;
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}
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static int sprd_adi_read_check_r2(u32 val, u32 reg)
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{
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return sprd_adi_read_check(val, reg & RDBACK_ADDR_MASK_R2);
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}
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static int sprd_adi_read_check_r3(u32 val, u32 reg)
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{
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return sprd_adi_read_check(val, (reg & RDBACK_ADDR_MASK_R3) >> RDBACK_ADDR_SHIFT_R3);
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}
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static int sprd_adi_read(struct sprd_adi *sadi, u32 reg, u32 *read_val)
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{
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int read_timeout = ADI_READ_TIMEOUT;
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unsigned long flags;
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u32 val, rd_addr;
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u32 val;
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int ret = 0;
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if (sadi->hwlock) {
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@ -203,18 +265,15 @@ static int sprd_adi_read(struct sprd_adi *sadi, u32 reg, u32 *read_val)
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}
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/*
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* The return value includes data and read register address, from bit 0
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* to bit 15 are data, and from bit 16 to bit 30 are read register
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* address. Then we can check the returned register address to validate
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* data.
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* The return value before adi r5p0 includes data and read register
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* address, from bit 0to bit 15 are data, and from bit 16 to bit 30
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* are read register address. Then we can check the returned register
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* address to validate data.
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*/
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rd_addr = (val & RD_ADDR_MASK) >> RD_ADDR_SHIFT;
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if (rd_addr != (reg & REG_ADDR_LOW_MASK)) {
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dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
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reg, val);
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ret = -EIO;
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goto out;
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if (sadi->data->read_check) {
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ret = sadi->data->read_check(val, reg);
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if (ret < 0)
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goto out;
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}
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*read_val = val & RD_VALUE_MASK;
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@ -299,20 +358,21 @@ static int sprd_adi_transfer_one(struct spi_controller *ctlr,
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return ret;
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}
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static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi)
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static void sprd_adi_set_wdt_rst_mode(void *p)
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{
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#if IS_ENABLED(CONFIG_SPRD_WATCHDOG)
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u32 val;
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struct sprd_adi *sadi = (struct sprd_adi *)p;
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/* Set default watchdog reboot mode */
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/* Init watchdog reset mode */
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sprd_adi_read(sadi, PMIC_RST_STATUS, &val);
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val |= HWRST_STATUS_WATCHDOG;
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sprd_adi_write(sadi, PMIC_RST_STATUS, val);
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#endif
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}
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static int sprd_adi_restart_handler(struct notifier_block *this,
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unsigned long mode, void *cmd)
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static int sprd_adi_restart(struct notifier_block *this, unsigned long mode,
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void *cmd, struct sprd_adi_wdg *wdg)
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{
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struct sprd_adi *sadi = container_of(this, struct sprd_adi,
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restart_handler);
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@ -348,40 +408,40 @@ static int sprd_adi_restart_handler(struct notifier_block *this,
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reboot_mode = HWRST_STATUS_NORMAL;
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/* Record the reboot mode */
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sprd_adi_read(sadi, PMIC_RST_STATUS, &val);
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sprd_adi_read(sadi, wdg->rst_sts, &val);
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val &= ~HWRST_STATUS_WATCHDOG;
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val |= reboot_mode;
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sprd_adi_write(sadi, PMIC_RST_STATUS, val);
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sprd_adi_write(sadi, wdg->rst_sts, val);
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/* Enable the interface clock of the watchdog */
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sprd_adi_read(sadi, PMIC_MODULE_EN, &val);
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sprd_adi_read(sadi, wdg->wdg_en, &val);
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val |= BIT_WDG_EN;
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sprd_adi_write(sadi, PMIC_MODULE_EN, val);
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sprd_adi_write(sadi, wdg->wdg_en, val);
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/* Enable the work clock of the watchdog */
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sprd_adi_read(sadi, PMIC_CLK_EN, &val);
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sprd_adi_read(sadi, wdg->wdg_clk, &val);
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val |= BIT_WDG_EN;
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sprd_adi_write(sadi, PMIC_CLK_EN, val);
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sprd_adi_write(sadi, wdg->wdg_clk, val);
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/* Unlock the watchdog */
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sprd_adi_write(sadi, REG_WDG_LOCK, WDG_UNLOCK_KEY);
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sprd_adi_write(sadi, wdg->base + REG_WDG_LOCK, WDG_UNLOCK_KEY);
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sprd_adi_read(sadi, REG_WDG_CTRL, &val);
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sprd_adi_read(sadi, wdg->base + REG_WDG_CTRL, &val);
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val |= BIT_WDG_NEW;
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sprd_adi_write(sadi, REG_WDG_CTRL, val);
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sprd_adi_write(sadi, wdg->base + REG_WDG_CTRL, val);
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/* Load the watchdog timeout value, 50ms is always enough. */
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sprd_adi_write(sadi, REG_WDG_LOAD_HIGH, 0);
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sprd_adi_write(sadi, REG_WDG_LOAD_LOW,
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sprd_adi_write(sadi, wdg->base + REG_WDG_LOAD_HIGH, 0);
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sprd_adi_write(sadi, wdg->base + REG_WDG_LOAD_LOW,
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WDG_LOAD_VAL & WDG_LOAD_MASK);
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/* Start the watchdog to reset system */
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sprd_adi_read(sadi, REG_WDG_CTRL, &val);
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sprd_adi_read(sadi, wdg->base + REG_WDG_CTRL, &val);
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val |= BIT_WDG_RUN | BIT_WDG_RST;
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sprd_adi_write(sadi, REG_WDG_CTRL, val);
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sprd_adi_write(sadi, wdg->base + REG_WDG_CTRL, val);
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/* Lock the watchdog */
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sprd_adi_write(sadi, REG_WDG_LOCK, ~WDG_UNLOCK_KEY);
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sprd_adi_write(sadi, wdg->base + REG_WDG_LOCK, ~WDG_UNLOCK_KEY);
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mdelay(1000);
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@ -389,6 +449,19 @@ static int sprd_adi_restart_handler(struct notifier_block *this,
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return NOTIFY_DONE;
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}
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static int sprd_adi_restart_sc9860(struct notifier_block *this,
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unsigned long mode, void *cmd)
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{
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struct sprd_adi_wdg wdg = {
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.base = PMIC_WDG_BASE,
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.rst_sts = PMIC_RST_STATUS,
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.wdg_en = PMIC_MODULE_EN,
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.wdg_clk = PMIC_CLK_EN,
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};
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return sprd_adi_restart(this, mode, cmd, &wdg);
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}
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static void sprd_adi_hw_init(struct sprd_adi *sadi)
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{
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struct device_node *np = sadi->dev->of_node;
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@ -440,10 +513,11 @@ static void sprd_adi_hw_init(struct sprd_adi *sadi)
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static int sprd_adi_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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const struct sprd_adi_data *data;
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struct spi_controller *ctlr;
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struct sprd_adi *sadi;
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struct resource *res;
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u32 num_chipselect;
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u16 num_chipselect;
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int ret;
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if (!np) {
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@ -451,6 +525,12 @@ static int sprd_adi_probe(struct platform_device *pdev)
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return -ENODEV;
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}
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data = of_device_get_match_data(&pdev->dev);
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if (!data) {
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dev_err(&pdev->dev, "no matching driver data found\n");
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return -EINVAL;
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}
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pdev->id = of_alias_get_id(np, "spi");
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num_chipselect = of_get_child_count(np);
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@ -468,10 +548,12 @@ static int sprd_adi_probe(struct platform_device *pdev)
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goto put_ctlr;
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}
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sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
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sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
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sadi->slave_vbase = (unsigned long)sadi->base +
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data->slave_offset;
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sadi->slave_pbase = res->start + data->slave_offset;
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sadi->ctlr = ctlr;
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sadi->dev = &pdev->dev;
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sadi->data = data;
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ret = of_hwspin_lock_get_id(np, 0);
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if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
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sadi->hwlock =
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@ -492,7 +574,9 @@ static int sprd_adi_probe(struct platform_device *pdev)
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}
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sprd_adi_hw_init(sadi);
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sprd_adi_set_wdt_rst_mode(sadi);
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if (sadi->data->wdg_rst)
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sadi->data->wdg_rst(sadi);
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ctlr->dev.of_node = pdev->dev.of_node;
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ctlr->bus_num = pdev->id;
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@ -507,12 +591,14 @@ static int sprd_adi_probe(struct platform_device *pdev)
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goto put_ctlr;
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}
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sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
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sadi->restart_handler.priority = 128;
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ret = register_restart_handler(&sadi->restart_handler);
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if (ret) {
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dev_err(&pdev->dev, "can not register restart handler\n");
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goto put_ctlr;
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if (sadi->data->restart) {
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sadi->restart_handler.notifier_call = sadi->data->restart;
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sadi->restart_handler.priority = 128;
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ret = register_restart_handler(&sadi->restart_handler);
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if (ret) {
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dev_err(&pdev->dev, "can not register restart handler\n");
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goto put_ctlr;
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}
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}
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return 0;
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@ -531,9 +617,38 @@ static int sprd_adi_remove(struct platform_device *pdev)
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return 0;
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}
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static struct sprd_adi_data sc9860_data = {
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.slave_offset = ADI_10BIT_SLAVE_OFFSET,
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.slave_addr_size = ADI_10BIT_SLAVE_ADDR_SIZE,
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.read_check = sprd_adi_read_check_r2,
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.restart = sprd_adi_restart_sc9860,
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.wdg_rst = sprd_adi_set_wdt_rst_mode,
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};
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static struct sprd_adi_data sc9863_data = {
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.slave_offset = ADI_12BIT_SLAVE_OFFSET,
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.slave_addr_size = ADI_12BIT_SLAVE_ADDR_SIZE,
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.read_check = sprd_adi_read_check_r3,
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};
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static struct sprd_adi_data ums512_data = {
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.slave_offset = ADI_15BIT_SLAVE_OFFSET,
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.slave_addr_size = ADI_15BIT_SLAVE_ADDR_SIZE,
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.read_check = sprd_adi_read_check_r3,
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};
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static const struct of_device_id sprd_adi_of_match[] = {
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{
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.compatible = "sprd,sc9860-adi",
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.data = &sc9860_data,
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},
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{
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.compatible = "sprd,sc9863-adi",
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.data = &sc9863_data,
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},
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{
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.compatible = "sprd,ums512-adi",
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.data = &ums512_data,
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},
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{ },
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};
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