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linux-sg2042
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spi: ti-qspi: one only one interrupt handler 

The here used irq and threaded irq handler is a complete non-sense. After
the status register is read and the source disabled it schedules a thread
(the irq thread) to read the status from the variable, invoke complete()
and then renable the interrupt. Again: schedule a thread which invokes
_only_ complete().
This patch removes this non-sense and we remain with one handler which
invokes complete() if needed.
The device remove path should now disable the interupts.
This has been compile time tested.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Tested-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Sebastian Andrzej Siewior 2013-10-02 16:45:25 +02:00 committed by Mark Brown
parent 633795b992
commit 3b3a80019f
1 changed files with 7 additions and 34 deletions
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41
drivers/spi/spi-ti-qspi.c
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@ -41,9 +41,6 @@ struct ti_qspi_regs {
struct ti_qspi { struct ti_qspi {
struct completion transfer_complete; struct completion transfer_complete;
/* IRQ synchronization */
spinlock_t lock;
/* list synchronization */ /* list synchronization */
struct mutex list_lock; struct mutex list_lock;
@ -57,7 +54,6 @@ struct ti_qspi {
u32 spi_max_frequency; u32 spi_max_frequency;
u32 cmd; u32 cmd;
u32 dc; u32 dc;
u32 stat;
}; };
#define QSPI_PID (0x0) #define QSPI_PID (0x0)
@ -397,13 +393,12 @@ static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
{ {
struct ti_qspi *qspi = dev_id; struct ti_qspi *qspi = dev_id;
u16 int_stat; u16 int_stat;
u32 stat;
irqreturn_t ret = IRQ_HANDLED; irqreturn_t ret = IRQ_HANDLED;
spin_lock(&qspi->lock);
int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR); int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);
qspi->stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
if (!int_stat) { if (!int_stat) {
dev_dbg(qspi->dev, "No IRQ triggered\n"); dev_dbg(qspi->dev, "No IRQ triggered\n");
@ -411,33 +406,12 @@ static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
goto out; goto out;
} }
ret = IRQ_WAKE_THREAD;
ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,
QSPI_INTR_STATUS_ENABLED_CLEAR); QSPI_INTR_STATUS_ENABLED_CLEAR);
if (stat & WC)
out:
spin_unlock(&qspi->lock);
return ret;
}
static irqreturn_t ti_qspi_threaded_isr(int this_irq, void *dev_id)
{
struct ti_qspi *qspi = dev_id;
unsigned long flags;
spin_lock_irqsave(&qspi->lock, flags);
if (qspi->stat & WC)
complete(&qspi->transfer_complete); complete(&qspi->transfer_complete);
out:
spin_unlock_irqrestore(&qspi->lock, flags); return ret;
ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
return IRQ_HANDLED;
} }
static int ti_qspi_runtime_resume(struct device *dev) static int ti_qspi_runtime_resume(struct device *dev)
@ -499,7 +473,6 @@ static int ti_qspi_probe(struct platform_device *pdev)
return irq; return irq;
} }
spin_lock_init(&qspi->lock);
mutex_init(&qspi->list_lock); mutex_init(&qspi->list_lock);
qspi->base = devm_ioremap_resource(&pdev->dev, r); qspi->base = devm_ioremap_resource(&pdev->dev, r);
@ -508,8 +481,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
goto free_master; goto free_master;
} }
ret = devm_request_threaded_irq(&pdev->dev, irq, ti_qspi_isr, ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
ti_qspi_threaded_isr, 0,
dev_name(&pdev->dev), qspi); dev_name(&pdev->dev), qspi);
if (ret < 0) { if (ret < 0) {
dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
@ -547,6 +519,7 @@ static int ti_qspi_remove(struct platform_device *pdev)
{ {
struct ti_qspi *qspi = platform_get_drvdata(pdev); struct ti_qspi *qspi = platform_get_drvdata(pdev);
ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
spi_unregister_master(qspi->master); spi_unregister_master(qspi->master);
return 0; return 0;