Staging: comedi: Coding style cleanups in adv_pci_dio.c
This patch fixes up many coding style issues in adv_pci_dio.c found by checkpatch.pl Signed-off-by: Mark Rankilor <reodge@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mark
Greg Kroah-Hartman
parent
5e95efecb5
commit
3afbe13cbe
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@ -67,9 +67,12 @@ enum hw_io_access {
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#define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
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#define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
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#define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per card */
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#define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per card */
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/* (could be more than one 8254 per subdevice) */
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#define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
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* card */
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#define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per
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* card */
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/* (could be more than one 8254 per
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* subdevice) */
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#define SIZE_8254 4 /* 8254 IO space length */
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#define SIZE_8255 4 /* 8255 IO space length */
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@ -84,7 +87,8 @@ enum hw_io_access {
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#define PCI1730_DO 2 /* W: Digital output 0-15 */
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#define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
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#define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
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#define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for interrupts */
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#define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
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* interrupts */
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#define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
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#define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
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#define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
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@ -99,7 +103,8 @@ enum hw_io_access {
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#define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
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#define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
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#define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
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#define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for interrupts */
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#define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
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* interrupts */
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#define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
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#define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
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#define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */
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@ -161,37 +166,66 @@ enum hw_io_access {
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#define INTCSR3 0x3b
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/* PCI-1760 mailbox commands */
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#define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actaul DI status in IMB3 */
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#define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual
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* DI status in IMB3 */
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#define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */
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#define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */
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#define CMD_ReadCurrentStatus 0x07 /* Read the current status of the register in OMB0, result in IMB0 */
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#define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in IMB1.IMB0 */
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#define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in IMB1.IMB0 */
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#define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in OMB0 */
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#define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on bits in OMB0 */
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#define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on bits in OMB0 */
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#define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in OMB0 */
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#define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in OMB0 to its reset values */
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#define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow interrupts based on bits in OMB0 */
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#define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value interrupts based on bits in OMB0 */
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#define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0 - rising, =1 - falling) */
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#define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current value */
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#define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value 256*OMB1+OMB0 */
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#define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value 256*OMB1+OMB0 */
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#define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value 256*OMB1+OMB0 */
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#define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value 256*OMB1+OMB0 */
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#define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value 256*OMB1+OMB0 */
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#define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value 256*OMB1+OMB0 */
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#define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value 256*OMB1+OMB0 */
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#define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value 256*OMB1+OMB0 */
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#define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value 256*OMB1+OMB0 */
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#define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value 256*OMB1+OMB0 */
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#define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value 256*OMB1+OMB0 */
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#define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value 256*OMB1+OMB0 */
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#define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value 256*OMB1+OMB0 */
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#define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value 256*OMB1+OMB0 */
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#define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value 256*OMB1+OMB0 */
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#define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value 256*OMB1+OMB0 */
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#define CMD_ReadCurrentStatus 0x07 /* Read the current status of the
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* register in OMB0, result in IMB0 */
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#define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in
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* IMB1.IMB0 */
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#define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in
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* IMB1.IMB0 */
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#define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in
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* OMB0 */
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#define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on
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* bits in OMB0 */
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#define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on
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* bits in OMB0 */
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#define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in
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* OMB0 */
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#define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in
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* OMB0 to its reset values */
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#define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow
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* interrupts based on bits in OMB0 */
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#define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value
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* interrupts based on bits in OMB0 */
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#define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0
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* - rising, =1 - falling) */
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#define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current
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* value */
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#define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value
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* 256*OMB1+OMB0 */
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#define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value
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* 256*OMB1+OMB0 */
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#define OMBCMD_RETRY 0x03 /* 3 times try request before error */
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@ -373,9 +407,12 @@ struct pci_dio_private {
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char GlobalIrqEnabled; /* 1= any IRQ source is enabled */
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/* PCI-1760 specific data */
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unsigned char IDICntEnable; /* counter's counting enable status */
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unsigned char IDICntOverEnable; /* counter's overflow interrupts enable status */
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unsigned char IDICntMatchEnable; /* counter's match interrupts enable status */
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unsigned char IDICntEdge; /* counter's count edge value (bit=0 - rising, =1 - falling) */
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unsigned char IDICntOverEnable; /* counter's overflow interrupts enable
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* status */
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unsigned char IDICntMatchEnable; /* counter's match interrupts
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* enable status */
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unsigned char IDICntEdge; /* counter's count edge value
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* (bit=0 - rising, =1 - falling) */
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unsigned short CntResValue[8]; /* counters' reset value */
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unsigned short CntMatchValue[8]; /* counters' match interrupt value */
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unsigned char IDIFiltersEn; /* IDI's digital filters enable status */
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@ -691,7 +728,8 @@ static int pci1760_insn_cnt_write(struct comedi_device *dev,
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};
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unsigned char imb[4];
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if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) { /* Set reset value if different */
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/* Set reset value if different */
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if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) {
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ret = pci1760_mbxrequest(dev, omb, imb);
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if (!ret)
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return ret;
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@ -704,7 +742,8 @@ static int pci1760_insn_cnt_write(struct comedi_device *dev,
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if (!ret)
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return ret;
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if (!(bitmask & devpriv->IDICntEnable)) { /* start counter if it don't run */
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/* start counter if it don't run */
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if (!(bitmask & devpriv->IDICntEnable)) {
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omb[0] = bitmask;
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omb[2] = CMD_EnableIDICounters;
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ret = pci1760_mbxrequest(dev, omb, imb);
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@ -740,12 +779,14 @@ static int pci1760_reset(struct comedi_device *dev)
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devpriv->IDICntEnable = 0;
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omb[0] = 0x00;
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omb[2] = CMD_OverflowIDICounters; /* disable counters overflow interrupts */
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omb[2] = CMD_OverflowIDICounters; /* disable counters overflow
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* interrupts */
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pci1760_mbxrequest(dev, omb, imb);
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devpriv->IDICntOverEnable = 0;
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omb[0] = 0x00;
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omb[2] = CMD_MatchIntIDICounters; /* disable counters match value interrupts */
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omb[2] = CMD_MatchIntIDICounters; /* disable counters match value
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* interrupts */
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pci1760_mbxrequest(dev, omb, imb);
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devpriv->IDICntMatchEnable = 0;
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@ -766,7 +807,8 @@ static int pci1760_reset(struct comedi_device *dev)
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}
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omb[0] = 0xff;
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omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset values */
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omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset
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* values */
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pci1760_mbxrequest(dev, omb, imb);
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omb[0] = 0x00;
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@ -807,9 +849,12 @@ static int pci_dio_reset(struct comedi_device *dev)
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outb(0, dev->iobase + PCI1730_IDO + 1);
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/* NO break there! */
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case TYPE_PCI1733:
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outb(0, dev->iobase + PCI1730_3_INT_EN); /* disable interrupts */
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outb(0x0f, dev->iobase + PCI1730_3_INT_CLR); /* clear interrupts */
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outb(0, dev->iobase + PCI1730_3_INT_RF); /* set rising edge trigger */
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/* disable interrupts */
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outb(0, dev->iobase + PCI1730_3_INT_EN);
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/* clear interrupts */
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outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
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/* set rising edge trigger */
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outb(0, dev->iobase + PCI1730_3_INT_RF);
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break;
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case TYPE_PCI1734:
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outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */
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@ -830,43 +875,53 @@ static int pci_dio_reset(struct comedi_device *dev)
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case TYPE_PCI1736:
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outb(0, dev->iobase + PCI1736_IDO);
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outb(0, dev->iobase + PCI1736_IDO + 1);
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outb(0, dev->iobase + PCI1736_3_INT_EN); /* disable interrupts */
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outb(0x0f, dev->iobase + PCI1736_3_INT_CLR); /* clear interrupts */
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outb(0, dev->iobase + PCI1736_3_INT_RF); /* set rising edge trigger */
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/* disable interrupts */
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outb(0, dev->iobase + PCI1736_3_INT_EN);
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/* clear interrupts */
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outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
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/* set rising edge trigger */
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outb(0, dev->iobase + PCI1736_3_INT_RF);
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break;
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case TYPE_PCI1750:
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case TYPE_PCI1751:
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outb(0x88, dev->iobase + PCI1750_ICR); /* disable & clear interrupts */
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/* disable & clear interrupts */
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outb(0x88, dev->iobase + PCI1750_ICR);
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break;
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case TYPE_PCI1752:
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outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze function */
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outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
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* function */
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outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */
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outw(0, dev->iobase + PCI1752_IDO + 2);
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outw(0, dev->iobase + PCI1752_IDO2);
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outw(0, dev->iobase + PCI1752_IDO2 + 2);
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break;
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case TYPE_PCI1753E:
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outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear interrupts */
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outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear
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* interrupts */
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outb(0x80, dev->iobase + PCI1753E_ICR1);
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outb(0x80, dev->iobase + PCI1753E_ICR2);
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outb(0x80, dev->iobase + PCI1753E_ICR3);
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/* NO break there! */
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case TYPE_PCI1753:
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outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear interrupts */
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outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear
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* interrupts */
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outb(0x80, dev->iobase + PCI1753_ICR1);
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outb(0x80, dev->iobase + PCI1753_ICR2);
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outb(0x80, dev->iobase + PCI1753_ICR3);
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break;
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case TYPE_PCI1754:
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outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear interrupts */
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outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
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* interrupts */
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outw(0x08, dev->iobase + PCI1754_6_ICR1);
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outw(0x08, dev->iobase + PCI1754_ICR2);
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outw(0x08, dev->iobase + PCI1754_ICR3);
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break;
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case TYPE_PCI1756:
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outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze function */
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outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear interrupts */
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outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
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* function */
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outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
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* interrupts */
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outw(0x08, dev->iobase + PCI1754_6_ICR1);
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outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */
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outw(0, dev->iobase + PCI1756_IDO + 2);
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@ -875,7 +930,8 @@ static int pci_dio_reset(struct comedi_device *dev)
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pci1760_reset(dev);
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break;
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case TYPE_PCI1762:
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outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear interrupts */
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outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear
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* interrupts */
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break;
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}
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@ -1215,15 +1271,12 @@ static int pci_dio_detach(struct comedi_device *dev)
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}
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}
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if (this_board->boardid.chans) {
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if (this_board->boardid.chans)
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subdev++;
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}
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for (i = 0; i < MAX_8254_SUBDEVS; i++) {
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if (this_board->s8254[i].chans) {
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for (i = 0; i < MAX_8254_SUBDEVS; i++)
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if (this_board->s8254[i].chans)
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subdev++;
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}
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}
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for (i = 0; i < dev->n_subdevices; i++) {
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s = dev->subdevices + i;
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