Blackfin arch: cache the values of vco/sclk/cclk as the overhead of doing so (~24 bytes) is worth avoiding the software mult/div routines
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
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@ -850,38 +850,55 @@ static int __init topology_init(void)
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subsys_initcall(topology_init);
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subsys_initcall(topology_init);
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/* Get the voltage input multiplier */
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static u_long cached_vco_pll_ctl, cached_vco;
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static u_long get_vco(void)
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static u_long get_vco(void)
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{
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{
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u_long msel;
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u_long msel;
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u_long vco;
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msel = (bfin_read_PLL_CTL() >> 9) & 0x3F;
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u_long pll_ctl = bfin_read_PLL_CTL();
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if (pll_ctl == cached_vco_pll_ctl)
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return cached_vco;
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else
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cached_vco_pll_ctl = pll_ctl;
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msel = (pll_ctl >> 9) & 0x3F;
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if (0 == msel)
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if (0 == msel)
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msel = 64;
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msel = 64;
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vco = CONFIG_CLKIN_HZ;
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cached_vco = CONFIG_CLKIN_HZ;
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vco >>= (1 & bfin_read_PLL_CTL()); /* DF bit */
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cached_vco >>= (1 & pll_ctl); /* DF bit */
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vco = msel * vco;
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cached_vco *= msel;
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return vco;
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return cached_vco;
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}
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}
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/* Get the Core clock */
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/* Get the Core clock */
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static u_long cached_cclk_pll_div, cached_cclk;
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u_long get_cclk(void)
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u_long get_cclk(void)
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{
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{
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u_long csel, ssel;
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u_long csel, ssel;
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if (bfin_read_PLL_STAT() & 0x1)
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if (bfin_read_PLL_STAT() & 0x1)
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return CONFIG_CLKIN_HZ;
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return CONFIG_CLKIN_HZ;
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ssel = bfin_read_PLL_DIV();
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ssel = bfin_read_PLL_DIV();
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if (ssel == cached_cclk_pll_div)
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return cached_cclk;
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else
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cached_cclk_pll_div = ssel;
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csel = ((ssel >> 4) & 0x03);
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csel = ((ssel >> 4) & 0x03);
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ssel &= 0xf;
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ssel &= 0xf;
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if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
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if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
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return get_vco() / ssel;
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cached_cclk = get_vco() / ssel;
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return get_vco() >> csel;
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else
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cached_cclk = get_vco() >> csel;
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return cached_cclk;
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}
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}
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EXPORT_SYMBOL(get_cclk);
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EXPORT_SYMBOL(get_cclk);
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/* Get the System clock */
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/* Get the System clock */
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static u_long cached_sclk_pll_div, cached_sclk;
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u_long get_sclk(void)
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u_long get_sclk(void)
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{
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{
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u_long ssel;
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u_long ssel;
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@ -889,13 +906,20 @@ u_long get_sclk(void)
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if (bfin_read_PLL_STAT() & 0x1)
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if (bfin_read_PLL_STAT() & 0x1)
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return CONFIG_CLKIN_HZ;
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return CONFIG_CLKIN_HZ;
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ssel = (bfin_read_PLL_DIV() & 0xf);
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ssel = bfin_read_PLL_DIV();
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if (ssel == cached_sclk_pll_div)
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return cached_sclk;
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else
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cached_sclk_pll_div = ssel;
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ssel &= 0xf;
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if (0 == ssel) {
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if (0 == ssel) {
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printk(KERN_WARNING "Invalid System Clock\n");
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printk(KERN_WARNING "Invalid System Clock\n");
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ssel = 1;
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ssel = 1;
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}
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}
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return get_vco() / ssel;
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cached_sclk = get_vco() / ssel;
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return cached_sclk;
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}
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}
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EXPORT_SYMBOL(get_sclk);
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EXPORT_SYMBOL(get_sclk);
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