Documentation: kbuild: Improve grammar
- singular versus plural, - "by" versus "of", - missing "if", "it", "the", - consistent use of "xxx-specific" versus "xxx specific". Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Michal Marek <mmarek@suse.cz>
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@ -174,7 +174,7 @@ more details, with real examples.
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--- 3.3 Loadable module goals - obj-m
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$(obj-m) specify object files which are built as loadable
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$(obj-m) specifies object files which are built as loadable
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kernel modules.
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A module may be built from one source file or several source
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@ -277,7 +277,7 @@ more details, with real examples.
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down in the ext2 directory.
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Kbuild only uses this information to decide that it needs to visit
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the directory, it is the Makefile in the subdirectory that
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specifies what is modules and what is built-in.
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specifies what is modular and what is built-in.
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It is good practice to use a CONFIG_ variable when assigning directory
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names. This allows kbuild to totally skip the directory if the
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@ -403,7 +403,7 @@ more details, with real examples.
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echoing information to user in a rule is often a good practice
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but when execution "make -s" one does not expect to see any output
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except for warnings/errors.
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To support this kbuild define $(kecho) which will echo out the
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To support this kbuild defines $(kecho) which will echo out the
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text following $(kecho) to stdout except if "make -s" is used.
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Example:
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@ -417,7 +417,7 @@ more details, with real examples.
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The kernel may be built with several different versions of
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$(CC), each supporting a unique set of features and options.
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kbuild provide basic support to check for valid options for $(CC).
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kbuild provides basic support to check for valid options for $(CC).
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$(CC) is usually the gcc compiler, but other alternatives are
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available.
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@ -456,8 +456,8 @@ more details, with real examples.
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Note: as-instr-option uses KBUILD_AFLAGS for $(AS) options
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cc-option
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cc-option is used to check if $(CC) supports a given option, and not
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supported to use an optional second option.
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cc-option is used to check if $(CC) supports a given option, and if
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not supported to use an optional second option.
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Example:
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#arch/x86/Makefile
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@ -557,8 +557,8 @@ more details, with real examples.
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false ; \
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fi
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In this example for a specific GCC version the build will error out explaining
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to the user why it stops.
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In this example for a specific GCC version the build will error out
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explaining to the user why it stops.
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cc-cross-prefix
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cc-cross-prefix is used to check if there exists a $(CC) in path with
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@ -656,7 +656,7 @@ Both possibilities are described in the following.
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In the example above the executable is composed of the C++ file
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qconf.cc - identified by $(qconf-cxxobjs).
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If qconf is composed by a mixture of .c and .cc files, then an
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If qconf is composed of a mixture of .c and .cc files, then an
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additional line can be used to identify this.
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Example:
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@ -733,7 +733,7 @@ Both possibilities are described in the following.
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hostprogs-$(CONFIG_KALLSYMS) += kallsyms
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Kbuild knows about both 'y' for built-in and 'm' for module.
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So if a config symbol evaluate to 'm', kbuild will still build
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So if a config symbol evaluates to 'm', kbuild will still build
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the binary. In other words, Kbuild handles hostprogs-m exactly
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like hostprogs-y. But only hostprogs-y is recommended to be used
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when no CONFIG symbols are involved.
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@ -754,8 +754,8 @@ Additional files can be specified in kbuild makefiles by use of $(clean-files).
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#drivers/pci/Makefile
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clean-files := devlist.h classlist.h
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When executing "make clean", the two files "devlist.h classlist.h" will
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be deleted. Kbuild will assume files to be in same relative directory as the
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When executing "make clean", the two files "devlist.h classlist.h" will be
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deleted. Kbuild will assume files to be in the same relative directory as the
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Makefile except if an absolute path is specified (path starting with '/').
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To delete a directory hierarchy use:
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@ -786,7 +786,7 @@ is not sufficient this sometimes needs to be explicit.
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The above assignment instructs kbuild to descend down in the
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directory compressed/ when "make clean" is executed.
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To support the clean infrastructure in the Makefiles that builds the
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To support the clean infrastructure in the Makefiles that build the
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final bootimage there is an optional target named archclean:
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Example:
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@ -926,7 +926,7 @@ When kbuild executes, the following steps are followed (roughly):
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KBUILD_AFLAGS_MODULE Options for $(AS) when building modules
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$(KBUILD_AFLAGS_MODULE) is used to add arch specific options that
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$(KBUILD_AFLAGS_MODULE) is used to add arch-specific options that
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are used for $(AS).
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From commandline AFLAGS_MODULE shall be used (see kbuild.txt).
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@ -937,13 +937,13 @@ When kbuild executes, the following steps are followed (roughly):
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KBUILD_CFLAGS_MODULE Options for $(CC) when building modules
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$(KBUILD_CFLAGS_MODULE) is used to add arch specific options that
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$(KBUILD_CFLAGS_MODULE) is used to add arch-specific options that
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are used for $(CC).
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From commandline CFLAGS_MODULE shall be used (see kbuild.txt).
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KBUILD_LDFLAGS_MODULE Options for $(LD) when linking modules
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$(KBUILD_LDFLAGS_MODULE) is used to add arch specific options
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$(KBUILD_LDFLAGS_MODULE) is used to add arch-specific options
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used when linking modules. This is often a linker script.
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From commandline LDFLAGS_MODULE shall be used (see kbuild.txt).
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@ -1065,7 +1065,7 @@ When kbuild executes, the following steps are followed (roughly):
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extra-y
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extra-y specify additional targets created in the current
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extra-y specifies additional targets created in the current
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directory, in addition to any targets specified by obj-*.
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Listing all targets in extra-y is required for two purposes:
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@ -1141,7 +1141,7 @@ When kbuild executes, the following steps are followed (roughly):
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2) delete target during make clean
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The ": %: %.o" part of the prerequisite is a shorthand that
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free us from listing the setup.o and bootsect.o files.
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frees us from listing the setup.o and bootsect.o files.
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Note: It is a common mistake to forget the "targets :=" assignment,
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resulting in the target file being recompiled for no
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obvious reason.
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@ -1213,11 +1213,11 @@ When kbuild executes, the following steps are followed (roughly):
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When building the *.lds target, kbuild uses the variables:
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KBUILD_CPPFLAGS : Set in top-level Makefile
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cppflags-y : May be set in the kbuild makefile
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CPPFLAGS_$(@F) : Target specific flags.
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CPPFLAGS_$(@F) : Target-specific flags.
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Note that the full filename is used in this
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assignment.
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The kbuild infrastructure for *lds file are used in several
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The kbuild infrastructure for *lds files is used in several
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architecture-specific files.
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--- 6.10 Generic header files
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@ -1230,11 +1230,11 @@ When kbuild executes, the following steps are followed (roughly):
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=== 7 Kbuild syntax for exported headers
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The kernel include a set of headers that is exported to userspace.
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The kernel includes a set of headers that is exported to userspace.
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Many headers can be exported as-is but other headers require a
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minimal pre-processing before they are ready for user-space.
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The pre-processing does:
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- drop kernel specific annotations
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- drop kernel-specific annotations
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- drop include of compiler.h
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- drop all sections that are kernel internal (guarded by ifdef __KERNEL__)
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--- 7.1 header-y
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header-y specify header files to be exported.
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header-y specifies header files to be exported.
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Example:
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#include/linux/Kbuild
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@ -1254,7 +1254,7 @@ See subsequent chapter for the syntax of the Kbuild file.
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The convention is to list one file per line and
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preferably in alphabetic order.
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header-y also specify which subdirectories to visit.
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header-y also specifies which subdirectories to visit.
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A subdirectory is identified by a trailing '/' which
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can be seen in the example above for the usb subdirectory.
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--- 7.3 destination-y
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When an architecture have a set of exported headers that needs to be
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When an architecture has a set of exported headers that needs to be
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exported to a different directory destination-y is used.
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destination-y specify the destination directory for all exported
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destination-y specifies the destination directory for all exported
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headers in the file where it is present.
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Example:
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@ -1367,9 +1367,9 @@ The top Makefile exports the following variables:
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INSTALL_MOD_STRIP
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If this variable is specified, will cause modules to be stripped
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If this variable is specified, it will cause modules to be stripped
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after they are installed. If INSTALL_MOD_STRIP is '1', then the
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default option --strip-debug will be used. Otherwise,
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default option --strip-debug will be used. Otherwise, the
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INSTALL_MOD_STRIP value will be used as the option(s) to the strip
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command.
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