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x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number 

The Hygon Dhyana CPU has a special MSR way to force WB for memory >4GB,
and support TOP_MEM2. Therefore, it is necessary to add Hygon Dhyana
support in amd_special_default_mtrr().

The number of variable MTRRs for Hygon is 2 as AMD's.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: x86@kernel.org
Cc: thomas.lendacky@amd.com
Link: https://lkml.kernel.org/r/8246f81648d014601de3812ade40e85d9c50d9b3.1537533369.git.puwen@hygon.cn
This commit is contained in:
Pu Wen 2018-09-23 17:34:16 +08:00 committed by Borislav Petkov
parent d4f7423efd
commit 39dc6f154d
2 changed files with 3 additions and 2 deletions
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3
arch/x86/kernel/cpu/mtrr/cleanup.c
View File

@ -831,7 +831,8 @@ int __init amd_special_default_mtrr(void)
{ {
u32 l, h; u32 l, h;
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
return 0; return 0;
if (boot_cpu_data.x86 < 0xf) if (boot_cpu_data.x86 < 0xf)
return 0; return 0;

2
arch/x86/kernel/cpu/mtrr/mtrr.c
View File

@ -127,7 +127,7 @@ static void __init set_num_var_ranges(void)
if (use_intel()) if (use_intel())
rdmsr(MSR_MTRRcap, config, dummy); rdmsr(MSR_MTRRcap, config, dummy);
else if (is_cpu(AMD)) else if (is_cpu(AMD) || is_cpu(HYGON))
config = 2; config = 2;
else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
config = 8; config = 8;