drm/radeon: add cik tile mode array query
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
0672e27bea
commit
39aee49028
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@ -1059,6 +1059,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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gb_tile_moden = 0;
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gb_tile_moden = 0;
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break;
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break;
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}
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}
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rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
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WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
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WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
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}
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}
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for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
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for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
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@ -1277,6 +1278,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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gb_tile_moden = 0;
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gb_tile_moden = 0;
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break;
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break;
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}
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}
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rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
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WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
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WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
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}
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}
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} else if (num_rbs < 4) {
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} else if (num_rbs < 4) {
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@ -1402,6 +1404,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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gb_tile_moden = 0;
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gb_tile_moden = 0;
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break;
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break;
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}
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}
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rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
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WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
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WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
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}
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}
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}
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}
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@ -1619,6 +1622,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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gb_tile_moden = 0;
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gb_tile_moden = 0;
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break;
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break;
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}
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}
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rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
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WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
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WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
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}
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}
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for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
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for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
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@ -1587,6 +1587,7 @@ struct cik_asic {
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unsigned multi_gpu_tile_size;
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unsigned multi_gpu_tile_size;
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unsigned tile_config;
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unsigned tile_config;
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uint32_t tile_mode_array[32];
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};
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};
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union radeon_asic_config {
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union radeon_asic_config {
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@ -74,9 +74,10 @@
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* 2.31.0 - Add fastfb support for rs690
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* 2.31.0 - Add fastfb support for rs690
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* 2.32.0 - new info request for rings working
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* 2.32.0 - new info request for rings working
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* 2.33.0 - Add SI tiling mode array query
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* 2.33.0 - Add SI tiling mode array query
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* 2.34.0 - Add CIK tiling mode array query
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*/
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*/
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#define KMS_DRIVER_MAJOR 2
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#define KMS_DRIVER_MAJOR 2
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#define KMS_DRIVER_MINOR 33
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#define KMS_DRIVER_MINOR 34
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#define KMS_DRIVER_PATCHLEVEL 0
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#define KMS_DRIVER_PATCHLEVEL 0
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int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
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int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
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int radeon_driver_unload_kms(struct drm_device *dev);
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int radeon_driver_unload_kms(struct drm_device *dev);
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@ -423,15 +423,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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break;
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break;
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case RADEON_INFO_SI_TILE_MODE_ARRAY:
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case RADEON_INFO_SI_TILE_MODE_ARRAY:
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if (rdev->family >= CHIP_BONAIRE) {
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if (rdev->family >= CHIP_BONAIRE) {
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DRM_DEBUG_KMS("tile mode array is not implemented yet\n");
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value = rdev->config.cik.tile_mode_array;
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value_size = sizeof(uint32_t)*32;
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} else if (rdev->family >= CHIP_TAHITI) {
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value = rdev->config.si.tile_mode_array;
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value_size = sizeof(uint32_t)*32;
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} else {
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DRM_DEBUG_KMS("tile mode array is si+ only!\n");
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return -EINVAL;
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return -EINVAL;
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}
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}
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if (rdev->family < CHIP_TAHITI) {
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DRM_DEBUG_KMS("tile mode array is si only!\n");
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return -EINVAL;
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}
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value = rdev->config.si.tile_mode_array;
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value_size = sizeof(uint32_t)*32;
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break;
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break;
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default:
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default:
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DRM_DEBUG_KMS("Invalid request %d\n", info->request);
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DRM_DEBUG_KMS("Invalid request %d\n", info->request);
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