dmaengine: tegra-apb: Fix coding style problems
This patch fixes few dozens of coding style problems reported by checkpatch and prettifies code where makes sense. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20200209163356.6439-9-digetx@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
parent
2cd3d13cb4
commit
3964293aec
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@ -59,7 +59,7 @@
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#define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC
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#define TEGRA_APBDMA_CHAN_CSRE 0x00C
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#define TEGRA_APBDMA_CHAN_CSRE_PAUSE (1 << 31)
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#define TEGRA_APBDMA_CHAN_CSRE_PAUSE BIT(31)
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/* AHB memory address */
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#define TEGRA_APBDMA_CHAN_AHBPTR 0x010
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@ -120,21 +120,21 @@ struct tegra_dma;
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* @support_separate_wcount_reg: Support separate word count register.
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*/
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struct tegra_dma_chip_data {
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int nr_channels;
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int channel_reg_size;
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int max_dma_count;
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unsigned int nr_channels;
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unsigned int channel_reg_size;
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unsigned int max_dma_count;
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bool support_channel_pause;
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bool support_separate_wcount_reg;
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};
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/* DMA channel registers */
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struct tegra_dma_channel_regs {
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unsigned long csr;
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unsigned long ahb_ptr;
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unsigned long apb_ptr;
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unsigned long ahb_seq;
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unsigned long apb_seq;
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unsigned long wcount;
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u32 csr;
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u32 ahb_ptr;
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u32 apb_ptr;
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u32 ahb_seq;
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u32 apb_seq;
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u32 wcount;
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};
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/*
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@ -168,7 +168,7 @@ struct tegra_dma_desc {
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struct list_head node;
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struct list_head tx_list;
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struct list_head cb_node;
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int cb_count;
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unsigned int cb_count;
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};
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struct tegra_dma_channel;
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@ -181,7 +181,7 @@ struct tegra_dma_channel {
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struct dma_chan dma_chan;
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char name[12];
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bool config_init;
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int id;
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unsigned int id;
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void __iomem *chan_addr;
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spinlock_t lock;
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bool busy;
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@ -201,7 +201,7 @@ struct tegra_dma_channel {
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/* Channel-slave specific configuration */
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unsigned int slave_id;
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struct dma_slave_config dma_sconfig;
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struct tegra_dma_channel_regs channel_reg;
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struct tegra_dma_channel_regs channel_reg;
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};
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/* tegra_dma: Tegra DMA specific information */
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@ -239,7 +239,7 @@ static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
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}
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static inline void tdc_write(struct tegra_dma_channel *tdc,
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u32 reg, u32 val)
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u32 reg, u32 val)
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{
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writel(val, tdc->chan_addr + reg);
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}
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@ -254,8 +254,8 @@ static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
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return container_of(dc, struct tegra_dma_channel, dma_chan);
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}
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static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
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struct dma_async_tx_descriptor *td)
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static inline struct tegra_dma_desc *
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txd_to_tegra_dma_desc(struct dma_async_tx_descriptor *td)
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{
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return container_of(td, struct tegra_dma_desc, txd);
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}
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@ -270,8 +270,7 @@ static int tegra_dma_runtime_suspend(struct device *dev);
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static int tegra_dma_runtime_resume(struct device *dev);
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/* Get DMA desc from free list, if not there then allocate it. */
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static struct tegra_dma_desc *tegra_dma_desc_get(
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struct tegra_dma_channel *tdc)
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static struct tegra_dma_desc *tegra_dma_desc_get(struct tegra_dma_channel *tdc)
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{
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struct tegra_dma_desc *dma_desc;
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unsigned long flags;
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@ -298,11 +297,12 @@ static struct tegra_dma_desc *tegra_dma_desc_get(
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dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
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dma_desc->txd.tx_submit = tegra_dma_tx_submit;
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dma_desc->txd.flags = 0;
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return dma_desc;
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}
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static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
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struct tegra_dma_desc *dma_desc)
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struct tegra_dma_desc *dma_desc)
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{
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unsigned long flags;
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@ -313,29 +313,29 @@ static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
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spin_unlock_irqrestore(&tdc->lock, flags);
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}
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static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
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struct tegra_dma_channel *tdc)
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static struct tegra_dma_sg_req *
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tegra_dma_sg_req_get(struct tegra_dma_channel *tdc)
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{
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struct tegra_dma_sg_req *sg_req = NULL;
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struct tegra_dma_sg_req *sg_req;
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unsigned long flags;
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spin_lock_irqsave(&tdc->lock, flags);
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if (!list_empty(&tdc->free_sg_req)) {
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sg_req = list_first_entry(&tdc->free_sg_req,
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typeof(*sg_req), node);
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sg_req = list_first_entry(&tdc->free_sg_req, typeof(*sg_req),
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node);
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list_del(&sg_req->node);
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spin_unlock_irqrestore(&tdc->lock, flags);
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return sg_req;
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}
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spin_unlock_irqrestore(&tdc->lock, flags);
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sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_NOWAIT);
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sg_req = kzalloc(sizeof(*sg_req), GFP_NOWAIT);
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return sg_req;
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}
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static int tegra_dma_slave_config(struct dma_chan *dc,
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struct dma_slave_config *sconfig)
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struct dma_slave_config *sconfig)
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{
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struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
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@ -352,11 +352,12 @@ static int tegra_dma_slave_config(struct dma_chan *dc,
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tdc->slave_id = sconfig->slave_id;
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}
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tdc->config_init = true;
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return 0;
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}
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static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
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bool wait_for_burst_complete)
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bool wait_for_burst_complete)
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{
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struct tegra_dma *tdma = tdc->tdma;
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@ -391,13 +392,13 @@ out:
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}
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static void tegra_dma_pause(struct tegra_dma_channel *tdc,
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bool wait_for_burst_complete)
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bool wait_for_burst_complete)
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{
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struct tegra_dma *tdma = tdc->tdma;
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if (tdma->chip_data->support_channel_pause) {
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tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
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TEGRA_APBDMA_CHAN_CSRE_PAUSE);
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TEGRA_APBDMA_CHAN_CSRE_PAUSE);
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if (wait_for_burst_complete)
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udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
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} else {
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@ -409,17 +410,15 @@ static void tegra_dma_resume(struct tegra_dma_channel *tdc)
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{
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struct tegra_dma *tdma = tdc->tdma;
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if (tdma->chip_data->support_channel_pause) {
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if (tdma->chip_data->support_channel_pause)
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tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
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} else {
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else
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tegra_dma_global_resume(tdc);
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}
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}
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static void tegra_dma_stop(struct tegra_dma_channel *tdc)
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{
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u32 csr;
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u32 status;
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u32 csr, status;
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/* Disable interrupts */
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csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
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@ -440,7 +439,7 @@ static void tegra_dma_stop(struct tegra_dma_channel *tdc)
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}
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static void tegra_dma_start(struct tegra_dma_channel *tdc,
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struct tegra_dma_sg_req *sg_req)
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struct tegra_dma_sg_req *sg_req)
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{
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struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
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@ -454,11 +453,11 @@ static void tegra_dma_start(struct tegra_dma_channel *tdc,
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/* Start DMA */
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tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
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ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
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ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
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}
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static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
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struct tegra_dma_sg_req *nsg_req)
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struct tegra_dma_sg_req *nsg_req)
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{
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unsigned long status;
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@ -492,9 +491,9 @@ static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
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tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
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if (tdc->tdma->chip_data->support_separate_wcount_reg)
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tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
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nsg_req->ch_regs.wcount);
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nsg_req->ch_regs.wcount);
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tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
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nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
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nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
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nsg_req->configured = true;
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nsg_req->words_xferred = 0;
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@ -508,8 +507,7 @@ static void tdc_start_head_req(struct tegra_dma_channel *tdc)
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if (list_empty(&tdc->pending_sg_req))
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return;
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sg_req = list_first_entry(&tdc->pending_sg_req,
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typeof(*sg_req), node);
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sg_req = list_first_entry(&tdc->pending_sg_req, typeof(*sg_req), node);
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tegra_dma_start(tdc, sg_req);
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sg_req->configured = true;
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sg_req->words_xferred = 0;
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@ -518,34 +516,35 @@ static void tdc_start_head_req(struct tegra_dma_channel *tdc)
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static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
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{
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struct tegra_dma_sg_req *hsgreq;
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struct tegra_dma_sg_req *hnsgreq;
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struct tegra_dma_sg_req *hsgreq, *hnsgreq;
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if (list_empty(&tdc->pending_sg_req))
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return;
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hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
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if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
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hnsgreq = list_first_entry(&hsgreq->node,
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typeof(*hnsgreq), node);
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hnsgreq = list_first_entry(&hsgreq->node, typeof(*hnsgreq),
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node);
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tegra_dma_configure_for_next(tdc, hnsgreq);
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}
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}
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static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
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struct tegra_dma_sg_req *sg_req, unsigned long status)
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static inline unsigned int
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get_current_xferred_count(struct tegra_dma_channel *tdc,
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struct tegra_dma_sg_req *sg_req,
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unsigned long status)
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{
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return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
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}
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static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
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{
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struct tegra_dma_sg_req *sgreq;
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struct tegra_dma_desc *dma_desc;
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struct tegra_dma_sg_req *sgreq;
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while (!list_empty(&tdc->pending_sg_req)) {
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sgreq = list_first_entry(&tdc->pending_sg_req,
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typeof(*sgreq), node);
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sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq),
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node);
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list_move_tail(&sgreq->node, &tdc->free_sg_req);
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if (sgreq->last_sg) {
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dma_desc = sgreq->dma_desc;
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@ -555,7 +554,7 @@ static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
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/* Add in cb list if it is not there. */
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if (!dma_desc->cb_count)
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list_add_tail(&dma_desc->cb_node,
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&tdc->cb_desc);
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&tdc->cb_desc);
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dma_desc->cb_count++;
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}
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}
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@ -563,9 +562,10 @@ static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
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}
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static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
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struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
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struct tegra_dma_sg_req *last_sg_req,
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bool to_terminate)
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{
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struct tegra_dma_sg_req *hsgreq = NULL;
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struct tegra_dma_sg_req *hsgreq;
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if (list_empty(&tdc->pending_sg_req)) {
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dev_err(tdc2dev(tdc), "DMA is running without req\n");
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@ -589,14 +589,15 @@ static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
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/* Configure next request */
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if (!to_terminate)
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tdc_configure_next_head_desc(tdc);
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return true;
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}
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static void handle_once_dma_done(struct tegra_dma_channel *tdc,
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bool to_terminate)
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bool to_terminate)
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{
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struct tegra_dma_sg_req *sgreq;
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struct tegra_dma_desc *dma_desc;
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struct tegra_dma_sg_req *sgreq;
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tdc->busy = false;
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sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
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@ -622,10 +623,10 @@ static void handle_once_dma_done(struct tegra_dma_channel *tdc,
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}
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static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
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bool to_terminate)
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bool to_terminate)
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{
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struct tegra_dma_sg_req *sgreq;
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struct tegra_dma_desc *dma_desc;
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struct tegra_dma_sg_req *sgreq;
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bool st;
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sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
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@ -657,13 +658,13 @@ static void tegra_dma_tasklet(unsigned long data)
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struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
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struct dmaengine_desc_callback cb;
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struct tegra_dma_desc *dma_desc;
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unsigned int cb_count;
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unsigned long flags;
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int cb_count;
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spin_lock_irqsave(&tdc->lock, flags);
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while (!list_empty(&tdc->cb_desc)) {
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dma_desc = list_first_entry(&tdc->cb_desc,
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typeof(*dma_desc), cb_node);
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dma_desc = list_first_entry(&tdc->cb_desc, typeof(*dma_desc),
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cb_node);
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list_del(&dma_desc->cb_node);
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dmaengine_desc_get_callback(&dma_desc->txd, &cb);
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cb_count = dma_desc->cb_count;
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@ -681,8 +682,8 @@ static void tegra_dma_tasklet(unsigned long data)
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static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
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{
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struct tegra_dma_channel *tdc = dev_id;
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unsigned long status;
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unsigned long flags;
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u32 status;
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spin_lock_irqsave(&tdc->lock, flags);
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@ -697,8 +698,9 @@ static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
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}
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spin_unlock_irqrestore(&tdc->lock, flags);
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dev_info(tdc2dev(tdc),
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"Interrupt already served status 0x%08lx\n", status);
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dev_info(tdc2dev(tdc), "Interrupt already served status 0x%08x\n",
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status);
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return IRQ_NONE;
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}
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@ -714,6 +716,7 @@ static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
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cookie = dma_cookie_assign(&dma_desc->txd);
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list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
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spin_unlock_irqrestore(&tdc->lock, flags);
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return cookie;
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}
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@ -747,11 +750,10 @@ end:
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static int tegra_dma_terminate_all(struct dma_chan *dc)
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{
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struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
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struct tegra_dma_sg_req *sgreq;
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struct tegra_dma_desc *dma_desc;
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struct tegra_dma_sg_req *sgreq;
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unsigned long flags;
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unsigned long status;
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unsigned long wcount;
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u32 status, wcount;
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bool was_busy;
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spin_lock_irqsave(&tdc->lock, flags);
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@ -781,8 +783,8 @@ static int tegra_dma_terminate_all(struct dma_chan *dc)
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tegra_dma_stop(tdc);
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if (!list_empty(&tdc->pending_sg_req) && was_busy) {
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sgreq = list_first_entry(&tdc->pending_sg_req,
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typeof(*sgreq), node);
|
||||
sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq),
|
||||
node);
|
||||
sgreq->dma_desc->bytes_transferred +=
|
||||
get_current_xferred_count(tdc, sgreq, wcount);
|
||||
}
|
||||
|
@ -792,12 +794,13 @@ skip_dma_stop:
|
|||
tegra_dma_abort_all(tdc);
|
||||
|
||||
while (!list_empty(&tdc->cb_desc)) {
|
||||
dma_desc = list_first_entry(&tdc->cb_desc,
|
||||
typeof(*dma_desc), cb_node);
|
||||
dma_desc = list_first_entry(&tdc->cb_desc, typeof(*dma_desc),
|
||||
cb_node);
|
||||
list_del(&dma_desc->cb_node);
|
||||
dma_desc->cb_count = 0;
|
||||
}
|
||||
spin_unlock_irqrestore(&tdc->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -811,7 +814,7 @@ static void tegra_dma_synchronize(struct dma_chan *dc)
|
|||
static unsigned int tegra_dma_sg_bytes_xferred(struct tegra_dma_channel *tdc,
|
||||
struct tegra_dma_sg_req *sg_req)
|
||||
{
|
||||
unsigned long status, wcount = 0;
|
||||
u32 status, wcount = 0;
|
||||
|
||||
if (!list_is_first(&sg_req->node, &tdc->pending_sg_req))
|
||||
return 0;
|
||||
|
@ -868,7 +871,8 @@ static unsigned int tegra_dma_sg_bytes_xferred(struct tegra_dma_channel *tdc,
|
|||
}
|
||||
|
||||
static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
|
||||
dma_cookie_t cookie, struct dma_tx_state *txstate)
|
||||
dma_cookie_t cookie,
|
||||
struct dma_tx_state *txstate)
|
||||
{
|
||||
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
||||
struct tegra_dma_desc *dma_desc;
|
||||
|
@ -915,11 +919,12 @@ found:
|
|||
|
||||
trace_tegra_dma_tx_status(&tdc->dma_chan, cookie, txstate);
|
||||
spin_unlock_irqrestore(&tdc->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline int get_bus_width(struct tegra_dma_channel *tdc,
|
||||
enum dma_slave_buswidth slave_bw)
|
||||
static inline unsigned int get_bus_width(struct tegra_dma_channel *tdc,
|
||||
enum dma_slave_buswidth slave_bw)
|
||||
{
|
||||
switch (slave_bw) {
|
||||
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
||||
|
@ -932,16 +937,17 @@ static inline int get_bus_width(struct tegra_dma_channel *tdc,
|
|||
return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
|
||||
default:
|
||||
dev_warn(tdc2dev(tdc),
|
||||
"slave bw is not supported, using 32bits\n");
|
||||
"slave bw is not supported, using 32bits\n");
|
||||
return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int get_burst_size(struct tegra_dma_channel *tdc,
|
||||
u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
|
||||
static inline unsigned int get_burst_size(struct tegra_dma_channel *tdc,
|
||||
u32 burst_size,
|
||||
enum dma_slave_buswidth slave_bw,
|
||||
u32 len)
|
||||
{
|
||||
int burst_byte;
|
||||
int burst_ahb_width;
|
||||
unsigned int burst_byte, burst_ahb_width;
|
||||
|
||||
/*
|
||||
* burst_size from client is in terms of the bus_width.
|
||||
|
@ -968,9 +974,12 @@ static inline int get_burst_size(struct tegra_dma_channel *tdc,
|
|||
}
|
||||
|
||||
static int get_transfer_param(struct tegra_dma_channel *tdc,
|
||||
enum dma_transfer_direction direction, unsigned long *apb_addr,
|
||||
unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
|
||||
enum dma_slave_buswidth *slave_bw)
|
||||
enum dma_transfer_direction direction,
|
||||
u32 *apb_addr,
|
||||
u32 *apb_seq,
|
||||
u32 *csr,
|
||||
unsigned int *burst_size,
|
||||
enum dma_slave_buswidth *slave_bw)
|
||||
{
|
||||
switch (direction) {
|
||||
case DMA_MEM_TO_DEV:
|
||||
|
@ -991,13 +1000,15 @@ static int get_transfer_param(struct tegra_dma_channel *tdc,
|
|||
|
||||
default:
|
||||
dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
|
||||
return -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
|
||||
struct tegra_dma_channel_regs *ch_regs, u32 len)
|
||||
struct tegra_dma_channel_regs *ch_regs,
|
||||
u32 len)
|
||||
{
|
||||
u32 len_field = (len - 4) & 0xFFFC;
|
||||
|
||||
|
@ -1007,20 +1018,23 @@ static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
|
|||
ch_regs->csr |= len_field;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
|
||||
struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
|
||||
enum dma_transfer_direction direction, unsigned long flags,
|
||||
void *context)
|
||||
static struct dma_async_tx_descriptor *
|
||||
tegra_dma_prep_slave_sg(struct dma_chan *dc,
|
||||
struct scatterlist *sgl,
|
||||
unsigned int sg_len,
|
||||
enum dma_transfer_direction direction,
|
||||
unsigned long flags,
|
||||
void *context)
|
||||
{
|
||||
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
||||
struct tegra_dma_desc *dma_desc;
|
||||
unsigned int i;
|
||||
struct scatterlist *sg;
|
||||
unsigned long csr, ahb_seq, apb_ptr, apb_seq;
|
||||
struct list_head req_list;
|
||||
struct tegra_dma_sg_req *sg_req = NULL;
|
||||
u32 burst_size;
|
||||
struct tegra_dma_sg_req *sg_req = NULL;
|
||||
u32 csr, ahb_seq, apb_ptr, apb_seq;
|
||||
enum dma_slave_buswidth slave_bw;
|
||||
struct tegra_dma_desc *dma_desc;
|
||||
struct list_head req_list;
|
||||
struct scatterlist *sg;
|
||||
unsigned int burst_size;
|
||||
unsigned int i;
|
||||
|
||||
if (!tdc->config_init) {
|
||||
dev_err(tdc2dev(tdc), "DMA channel is not configured\n");
|
||||
|
@ -1032,7 +1046,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
|
|||
}
|
||||
|
||||
if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
|
||||
&burst_size, &slave_bw) < 0)
|
||||
&burst_size, &slave_bw) < 0)
|
||||
return NULL;
|
||||
|
||||
INIT_LIST_HEAD(&req_list);
|
||||
|
@ -1078,7 +1092,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
|
|||
len = sg_dma_len(sg);
|
||||
|
||||
if ((len & 3) || (mem & 3) ||
|
||||
(len > tdc->tdma->chip_data->max_dma_count)) {
|
||||
len > tdc->tdma->chip_data->max_dma_count) {
|
||||
dev_err(tdc2dev(tdc),
|
||||
"DMA length/memory address is not supported\n");
|
||||
tegra_dma_desc_put(tdc, dma_desc);
|
||||
|
@ -1130,20 +1144,21 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
|
|||
return &dma_desc->txd;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
|
||||
struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
|
||||
size_t period_len, enum dma_transfer_direction direction,
|
||||
unsigned long flags)
|
||||
static struct dma_async_tx_descriptor *
|
||||
tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr,
|
||||
size_t buf_len,
|
||||
size_t period_len,
|
||||
enum dma_transfer_direction direction,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
||||
struct tegra_dma_desc *dma_desc = NULL;
|
||||
struct tegra_dma_sg_req *sg_req = NULL;
|
||||
unsigned long csr, ahb_seq, apb_ptr, apb_seq;
|
||||
int len;
|
||||
size_t remain_len;
|
||||
dma_addr_t mem = buf_addr;
|
||||
u32 burst_size;
|
||||
u32 csr, ahb_seq, apb_ptr, apb_seq;
|
||||
enum dma_slave_buswidth slave_bw;
|
||||
struct tegra_dma_desc *dma_desc;
|
||||
dma_addr_t mem = buf_addr;
|
||||
unsigned int burst_size;
|
||||
size_t len, remain_len;
|
||||
|
||||
if (!buf_len || !period_len) {
|
||||
dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
|
||||
|
@ -1177,13 +1192,13 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
|
|||
|
||||
len = period_len;
|
||||
if ((len & 3) || (buf_addr & 3) ||
|
||||
(len > tdc->tdma->chip_data->max_dma_count)) {
|
||||
len > tdc->tdma->chip_data->max_dma_count) {
|
||||
dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
|
||||
&burst_size, &slave_bw) < 0)
|
||||
&burst_size, &slave_bw) < 0)
|
||||
return NULL;
|
||||
|
||||
ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
|
||||
|
@ -1307,8 +1322,8 @@ static void tegra_dma_free_chan_resources(struct dma_chan *dc)
|
|||
tdc->isr_handler = NULL;
|
||||
|
||||
while (!list_empty(&dma_desc_list)) {
|
||||
dma_desc = list_first_entry(&dma_desc_list,
|
||||
typeof(*dma_desc), node);
|
||||
dma_desc = list_first_entry(&dma_desc_list, typeof(*dma_desc),
|
||||
node);
|
||||
list_del(&dma_desc->node);
|
||||
kfree(dma_desc);
|
||||
}
|
||||
|
@ -1327,8 +1342,8 @@ static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
|
|||
struct of_dma *ofdma)
|
||||
{
|
||||
struct tegra_dma *tdma = ofdma->of_dma_data;
|
||||
struct dma_chan *chan;
|
||||
struct tegra_dma_channel *tdc;
|
||||
struct dma_chan *chan;
|
||||
|
||||
if (dma_spec->args[0] > TEGRA_APBDMA_CSR_REQ_SEL_MASK) {
|
||||
dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]);
|
||||
|
@ -1383,20 +1398,16 @@ static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
|
|||
|
||||
static int tegra_dma_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_dma *tdma;
|
||||
int ret;
|
||||
int i;
|
||||
const struct tegra_dma_chip_data *cdata;
|
||||
struct tegra_dma *tdma;
|
||||
unsigned int i;
|
||||
size_t size;
|
||||
int ret;
|
||||
|
||||
cdata = of_device_get_match_data(&pdev->dev);
|
||||
if (!cdata) {
|
||||
dev_err(&pdev->dev, "Error: No device match data found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
size = struct_size(tdma, channels, cdata->nr_channels);
|
||||
|
||||
tdma = devm_kzalloc(&pdev->dev,
|
||||
struct_size(tdma, channels, cdata->nr_channels),
|
||||
GFP_KERNEL);
|
||||
tdma = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
|
||||
if (!tdma)
|
||||
return -ENOMEM;
|
||||
|
||||
|
@ -1428,10 +1439,8 @@ static int tegra_dma_probe(struct platform_device *pdev)
|
|||
else
|
||||
ret = pm_runtime_get_sync(&pdev->dev);
|
||||
|
||||
if (ret < 0) {
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
if (ret < 0)
|
||||
goto err_pm_disable;
|
||||
|
||||
/* Reset DMA controller */
|
||||
reset_control_assert(tdma->rst);
|
||||
|
@ -1474,13 +1483,13 @@ static int tegra_dma_probe(struct platform_device *pdev)
|
|||
tdc->dma_chan.device = &tdma->dma_dev;
|
||||
dma_cookie_init(&tdc->dma_chan);
|
||||
list_add_tail(&tdc->dma_chan.device_node,
|
||||
&tdma->dma_dev.channels);
|
||||
&tdma->dma_dev.channels);
|
||||
tdc->tdma = tdma;
|
||||
tdc->id = i;
|
||||
tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;
|
||||
|
||||
tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
|
||||
(unsigned long)tdc);
|
||||
(unsigned long)tdc);
|
||||
spin_lock_init(&tdc->lock);
|
||||
|
||||
INIT_LIST_HEAD(&tdc->pending_sg_req);
|
||||
|
@ -1532,16 +1541,19 @@ static int tegra_dma_probe(struct platform_device *pdev)
|
|||
goto err_unregister_dma_dev;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
|
||||
cdata->nr_channels);
|
||||
dev_info(&pdev->dev, "Tegra20 APB DMA driver registered %u channels\n",
|
||||
cdata->nr_channels);
|
||||
|
||||
return 0;
|
||||
|
||||
err_unregister_dma_dev:
|
||||
dma_async_device_unregister(&tdma->dma_dev);
|
||||
|
||||
err_pm_disable:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
if (!pm_runtime_status_suspended(&pdev->dev))
|
||||
tegra_dma_runtime_suspend(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -1561,7 +1573,7 @@ static int tegra_dma_remove(struct platform_device *pdev)
|
|||
static int tegra_dma_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct tegra_dma *tdma = dev_get_drvdata(dev);
|
||||
int i;
|
||||
unsigned int i;
|
||||
|
||||
tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
|
||||
for (i = 0; i < tdma->chip_data->nr_channels; i++) {
|
||||
|
@ -1590,7 +1602,8 @@ static int tegra_dma_runtime_suspend(struct device *dev)
|
|||
static int tegra_dma_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct tegra_dma *tdma = dev_get_drvdata(dev);
|
||||
int i, ret;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(tdma->dma_clk);
|
||||
if (ret < 0) {
|
||||
|
@ -1618,7 +1631,7 @@ static int tegra_dma_runtime_resume(struct device *dev)
|
|||
tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
|
||||
tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
|
||||
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
|
||||
(ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
|
||||
ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
Loading…
Reference in New Issue