firewire: ohci: cache the context run bit
The DMA context run control bit is entirely controlled by software, so it is safe to cache it. This allows the driver to avoid doing an additional MMIO read when queueing an AT packet. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
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@ -125,6 +125,7 @@ struct context {
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struct fw_ohci *ohci;
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struct fw_ohci *ohci;
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u32 regs;
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u32 regs;
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int total_allocation;
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int total_allocation;
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bool running;
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bool flushing;
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bool flushing;
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/*
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/*
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@ -1174,6 +1175,7 @@ static void context_run(struct context *ctx, u32 extra)
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le32_to_cpu(ctx->last->branch_address));
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le32_to_cpu(ctx->last->branch_address));
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reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
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reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
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reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
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reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
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ctx->running = true;
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flush_writes(ohci);
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flush_writes(ohci);
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}
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}
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@ -1202,6 +1204,7 @@ static void context_stop(struct context *ctx)
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ctx->active = false;
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ctx->active = false;
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reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
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reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
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ctx->running = false;
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flush_writes(ctx->ohci);
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flush_writes(ctx->ohci);
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for (i = 0; i < 10; i++) {
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for (i = 0; i < 10; i++) {
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@ -1232,7 +1235,6 @@ static int at_context_queue_packet(struct context *ctx,
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struct descriptor *d, *last;
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struct descriptor *d, *last;
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__le32 *header;
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__le32 *header;
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int z, tcode;
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int z, tcode;
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u32 reg;
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d = context_get_descriptors(ctx, 4, &d_bus);
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d = context_get_descriptors(ctx, 4, &d_bus);
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if (d == NULL) {
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if (d == NULL) {
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@ -1351,9 +1353,7 @@ static int at_context_queue_packet(struct context *ctx,
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context_append(ctx, d, z, 4 - z);
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context_append(ctx, d, z, 4 - z);
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/* If the context isn't already running, start it up. */
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if (!ctx->running)
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reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
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if ((reg & CONTEXT_RUN) == 0)
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context_run(ctx, 0);
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context_run(ctx, 0);
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return 0;
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return 0;
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