sh: Get SH-5 caches working again post-unification.
A number of cleanups to get the SH-5 cache management code in line with the rest of the SH backend. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
5c8f82c649
commit
38350e0a00
|
|
@ -20,19 +20,18 @@ int __init detect_cpu_and_cache_system(void)
|
|||
{
|
||||
unsigned long long cir;
|
||||
|
||||
/* Do peeks in real mode to avoid having to set up a mapping for the
|
||||
WPC registers. On SH5-101 cut2, such a mapping would be exposed to
|
||||
an address translation erratum which would make it hard to set up
|
||||
correctly. */
|
||||
/*
|
||||
* Do peeks in real mode to avoid having to set up a mapping for
|
||||
* the WPC registers. On SH5-101 cut2, such a mapping would be
|
||||
* exposed to an address translation erratum which would make it
|
||||
* hard to set up correctly.
|
||||
*/
|
||||
cir = peek_real_address_q(0x0d000008);
|
||||
if ((cir & 0xffff) == 0x5103) {
|
||||
if ((cir & 0xffff) == 0x5103)
|
||||
boot_cpu_data.type = CPU_SH5_103;
|
||||
} else if (((cir >> 32) & 0xffff) == 0x51e2) {
|
||||
else if (((cir >> 32) & 0xffff) == 0x51e2)
|
||||
/* CPU.VCR aliased at CIR address on SH5-101 */
|
||||
boot_cpu_data.type = CPU_SH5_101;
|
||||
} else {
|
||||
boot_cpu_data.type = CPU_SH_NONE;
|
||||
}
|
||||
|
||||
/*
|
||||
* First, setup some sane values for the I-cache.
|
||||
|
|
@ -40,37 +39,33 @@ int __init detect_cpu_and_cache_system(void)
|
|||
boot_cpu_data.icache.ways = 4;
|
||||
boot_cpu_data.icache.sets = 256;
|
||||
boot_cpu_data.icache.linesz = L1_CACHE_BYTES;
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* FIXME: This can probably be cleaned up a bit as well.. for example,
|
||||
* do we really need the way shift _and_ the way_step_shift ?? Judging
|
||||
* by the existing code, I would guess no.. is there any valid reason
|
||||
* why we need to be tracking this around?
|
||||
*/
|
||||
boot_cpu_data.icache.way_shift = 13;
|
||||
boot_cpu_data.icache.way_incr = (1 << 13);
|
||||
boot_cpu_data.icache.entry_shift = 5;
|
||||
boot_cpu_data.icache.set_shift = 4;
|
||||
boot_cpu_data.icache.way_step_shift = 16;
|
||||
boot_cpu_data.icache.asid_shift = 2;
|
||||
|
||||
/*
|
||||
* way offset = cache size / associativity, so just don't factor in
|
||||
* associativity in the first place..
|
||||
*/
|
||||
boot_cpu_data.icache.way_ofs = boot_cpu_data.icache.sets *
|
||||
boot_cpu_data.icache.linesz;
|
||||
|
||||
boot_cpu_data.icache.asid_mask = 0x3fc;
|
||||
boot_cpu_data.icache.idx_mask = 0x1fe0;
|
||||
boot_cpu_data.icache.epn_mask = 0xffffe000;
|
||||
#endif
|
||||
|
||||
boot_cpu_data.icache.way_size = boot_cpu_data.icache.sets *
|
||||
boot_cpu_data.icache.linesz;
|
||||
boot_cpu_data.icache.entry_mask = 0x1fe0;
|
||||
boot_cpu_data.icache.flags = 0;
|
||||
|
||||
/* A trivial starting point.. */
|
||||
memcpy(&boot_cpu_data.dcache,
|
||||
&boot_cpu_data.icache, sizeof(struct cache_info));
|
||||
/*
|
||||
* Next, setup some sane values for the D-cache.
|
||||
*
|
||||
* On the SH5, these are pretty consistent with the I-cache settings,
|
||||
* so we just copy over the existing definitions.. these can be fixed
|
||||
* up later, especially if we add runtime CPU probing.
|
||||
*
|
||||
* Though in the meantime it saves us from having to duplicate all of
|
||||
* the above definitions..
|
||||
*/
|
||||
boot_cpu_data.dcache = boot_cpu_data.icache;
|
||||
|
||||
/*
|
||||
* Setup any cache-related flags here
|
||||
*/
|
||||
#if defined(CONFIG_CACHE_WRITETHROUGH)
|
||||
set_bit(SH_CACHE_MODE_WT, &(boot_cpu_data.dcache.flags));
|
||||
#elif defined(CONFIG_CACHE_WRITEBACK)
|
||||
set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags));
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -3,8 +3,6 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/page.h>
|
||||
|
||||
struct vm_area_struct;
|
||||
struct page;
|
||||
struct mm_struct;
|
||||
|
|
@ -27,7 +25,7 @@ extern void flush_icache_user_range(struct vm_area_struct *vma,
|
|||
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
|
||||
|
||||
#define flush_icache_page(vma, page) do { } while (0)
|
||||
#define p3_cache_init() do { } while (0)
|
||||
void p3_cache_init(void);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
|
|
|
|||
|
|
@ -66,6 +66,9 @@ static inline void set_asid(unsigned long asid)
|
|||
: "=r" (sr), "=r" (pc) : "0" (sr));
|
||||
}
|
||||
|
||||
/* arch/sh/kernel/cpu/sh5/entry.S */
|
||||
extern unsigned long switch_and_save_asid(unsigned long new_asid);
|
||||
|
||||
/* No spare register to twiddle, so use a software cache */
|
||||
extern pgd_t *mmu_pdtp_cache;
|
||||
|
||||
|
|
|
|||
|
|
@ -55,11 +55,14 @@ extern void clear_page(void *to);
|
|||
extern void copy_page(void *to, void *from);
|
||||
|
||||
#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \
|
||||
(defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB))
|
||||
(defined(CONFIG_CPU_SH5) || defined(CONFIG_CPU_SH4) || \
|
||||
defined(CONFIG_SH7705_CACHE_32KB))
|
||||
struct page;
|
||||
struct vm_area_struct;
|
||||
extern void clear_user_page(void *to, unsigned long address, struct page *page);
|
||||
#ifdef CONFIG_CPU_SH4
|
||||
extern void copy_user_page(void *to, void *from, unsigned long address,
|
||||
struct page *page);
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
extern void copy_user_highpage(struct page *to, struct page *from,
|
||||
unsigned long vaddr, struct vm_area_struct *vma);
|
||||
#define __HAVE_ARCH_COPY_USER_HIGHPAGE
|
||||
|
|
|
|||
Loading…
Reference in New Issue