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driver:tpu:support multi cards 

Signed-off-by: tingzhu.wang@sophgo.com <tingzhu.wang@sophgo.com>
This commit is contained in:
tingzhu.wang@sophgo.com 2024-09-10 00:33:50 +08:00 committed by Xiaoguang Xing
parent 7bf1622822
commit 37a59cb8e7
13 changed files with 1173 additions and 351 deletions
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4
arch/riscv/boot/dts/sophgo/Makefile
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@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SOPHGO) += sg2044r-x7.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += bm1690-sc11-ap.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += bm1690-sc11-ap-chip2.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += bm1690-sc11-ap-chip0.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += bm1690-sc11-ap-chip1.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += bm1690-evb-ap.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += bm1690-cdm-ap.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += bm1690-cdm-rp.dtb

128
arch/riscv/boot/dts/sophgo/bm1690-pcie-tpu-card.dtsi
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@ -1,128 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
*/
#define BM1690_PCIE_MODE
#define BM1690_SC11
/ {
soc {
sgtpu {
compatible = "sophgo,tpu-1690";
reg = <0x70 0x50000000 0x0 0x8000>,
<0x69 0x08050000 0x0 0x3000>, // TPSYS0_SYS_REG, size should be 0C00
<0x69 0x18050000 0x0 0x3000>,
<0x69 0x28050000 0x0 0x3000>,
<0x69 0x38050000 0x0 0x3000>,
<0x69 0x48050000 0x0 0x3000>,
<0x69 0x58050000 0x0 0x3000>,
<0x69 0x68050000 0x0 0x3000>,
<0x69 0x78050000 0x0 0x3000>;
sophgo_fw_mode = <1>;
};
pcie_ep@0 {
compatible = "sophgo,pcie-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x0>;
socket_id = <0x0 0x0>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
#if defined BM1690_EVB_X4
// c2c0_x4_1
reg = <0x6c 0x00C00000 0x00000000 0x00300000>,
<0x6c 0x00f00000 0x00000000 0x00004000>,
<0x6c 0x00f80c00 0x00000000 0x00001000>,
<0x6c 0x007d0000 0x00000000 0x00001000>,
<0x6c 0x00000000 0x00000000 0x01ffffff>;
#endif
#if defined BM1690_EVB_X8
// c2c0_x8_1
reg = <0x6c 0x00000000 0x00000000 0x00300000>,
<0x6c 0x00300000 0x00000000 0x00004000>,
<0x6c 0x000c0c00 0x00000000 0x00001000>,
<0x6c 0x007d0000 0x00000000 0x00001000>,
<0x6c 0x00000000 0x00000000 0x01ffffff>;
#endif
#if defined PLD_C2C_1T16D
//pcie1
reg = <0x6c 0x00400000 0x00000000 0x00300000>,
<0x6c 0x00700000 0x00000000 0x00004000>,
<0x6c 0x00780c00 0x00000000 0x00001000>,
<0x6c 0x007d0000 0x00000000 0x00001000>,
<0x6c 0x00000000 0x00000000 0x01ffffff>;
#endif
#if defined AI_MODE_2044REVB
//cxp pcie9
reg = <0x6c 0x08400000 0x00000000 0x00300000>,
<0x6c 0x08700000 0x00000000 0x00004000>,
<0x6c 0x08780c00 0x00000000 0x00001000>,
<0x6c 0x087d0000 0x00000000 0x00001000>,
<0x6c 0x08400000 0x00000000 0x00fdffff>;
#endif
#if defined BM1690_SC11
// c2c1_x8_1
reg = <0x6c 0x02000000 0x00000000 0x00300000>,
<0x6c 0x02300000 0x00000000 0x00004000>,
<0x6c 0x020c0000 0x00000000 0x00001000>;
c2c_config_range = <0x6c 0x02000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x027d0000 0x00000000 0x00001000>;
#endif
reg-names = "dbi", "atu", "ctrl";
sophgo_card@0 {
compatible = "sophgo,sophgo-card";
reg = <0x1 0xa0000000 0x00000000 0x01400000>,
<0x70 0x101ff000 0x00000000 0x00001000>;
reg-names = "share-memory", "config_file";
host-channel-num = <1>;
tpu-channel-num = <8>;
media-channel-num = <0>;
tx-channel = <0x0 0x2 0x4 0x6 0x8 0xa 0xc 0xe 0x10>;
rx-channel = <0x1 0x3 0x5 0x7 0x9 0xb 0xd 0xf 0x11>;
channel-size = <0x100000>;
share-memory-type = <1>;
interrupt-parent = <&intc>;
interrupts = <352 IRQ_TYPE_EDGE_RISING>,
<353 IRQ_TYPE_EDGE_RISING>,
<354 IRQ_TYPE_EDGE_RISING>,
<355 IRQ_TYPE_EDGE_RISING>,
<356 IRQ_TYPE_EDGE_RISING>,
<357 IRQ_TYPE_EDGE_RISING>,
<358 IRQ_TYPE_EDGE_RISING>,
<359 IRQ_TYPE_EDGE_RISING>,
<360 IRQ_TYPE_EDGE_RISING>;
clr-irq = <0x6E 0x10000000 0x00000000 0x00000000>,
<0x6E 0x10000004 0x00000000 0x00000000>,
<0x6E 0x10000008 0x00000000 0x00000000>,
<0x6E 0x1000000c 0x00000000 0x00000000>,
<0x6E 0x10000010 0x00000000 0x00000000>,
<0x6E 0x10000014 0x00000000 0x00000000>,
<0x6E 0x10000018 0x00000000 0x00000000>,
<0x6E 0x1000001c 0x00000000 0x00000000>,
<0x6E 0x10000020 0x00000000 0x00000000>;
virtual-msi = <0x0 0x0 0x00000000 0x00000000>,
<0x69 0x0cd00000 0x00000000 0x00000001>,
<0x69 0x1cd00000 0x00000000 0x00000001>,
<0x69 0x2cd00000 0x00000000 0x00000001>,
<0x69 0x3cd00000 0x00000000 0x00000001>,
<0x69 0x4cd00000 0x00000000 0x00000001>,
<0x69 0x5cd00000 0x00000000 0x00000001>,
<0x69 0x6cd00000 0x00000000 0x00000001>,
<0x69 0x7cd00000 0x00000000 0x00000001>;
};
};
};
};

542
arch/riscv/boot/dts/sophgo/bm1690-sc11-ap-chip0.dts Normal file
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@ -0,0 +1,542 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/sophgo,sg2044-reset.h>
#include <dt-bindings/clock/sophgo,sg2044-clock.h>
#include "bm1690-cpu-ap.dtsi"
#include "sg2044-clock.dtsi"
#include "sg2044-pinctrl.dtsi"
#include "sg2044-peri-sys.dtsi"
#include "bm1690-video-sys.dtsi"
#include "bm1690-pcie-intc.dtsi"
/ {
/delete-node/ memory@80200000;
/delete-node/ bm-emmc@703000A000;
};
/ {
memory@80200000 {
device_type = "memory";
reg = <0x00000000 0x80200000 0x00000000 0x1fe00000>;
};
uart0: serial@7030000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x30000000 0x00000000 0x00001000>;
interrupt-parent = <&intc>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
//c2c0 x8/x4_1
pciephy_0: pciephy_0@6C00f81000 {
compatible = "sophgo,pcie-phy";
#phy-cells = <1>;
reg = <0x6c 0x00f81000 0x0 0x00001000>;
bus-width = <8>;
};
//c2c0 x8/x4_0
pciephy_1: pciephy_1@6C00781000 {
compatible = "sophgo,pcie-phy";
#phy-cells = <1>;
reg = <0x6c 0x00781000 0x0 0x00001000>;
bus-width = <8>;
};
//c2c1 x8/x4_1
pciephy_2: pciephy_2@6C02f81000 {
compatible = "sophgo,pcie-phy";
#phy-cells = <1>;
reg = <0x6c 0x02f81000 0x0 0x00001000>;
bus-width = <8>;
};
//c2c1 x8/x4_0
pciephy_3: pciephy_3@6C02781000 {
compatible = "sophgo,pcie-phy";
#phy-cells = <1>;
reg = <0x6c 0x02781000 0x0 0x00001000>;
bus-width = <8>;
};
//cxp x8/x4
pciephy_4: pciephy_4@6C08781000 {
compatible = "sophgo,pcie-phy";
#phy-cells = <1>;
reg = <0x6c 0x08781000 0x0 0x00001000>;
bus-width = <8>;
};
c2c_enable {
compatible = "sophgo,c2c_enable";
};
//c2c0_x8_1 c2c rc (on board)
pcie_rc_0: pcie@6c00000000 {
compatible = "sophgo,bm1690-c2c-pcie-host";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0x0f>;
linux,pci-domain = <0>;
interrupt-parent = <&intc1>;
reg = <0x6c 0x00000000 0x0 0x00001000>,
<0x6c 0x000c0000 0x0 0x00001000>,
<0x6c 0x00300000 0x0 0x00004000>,
<0x48 0x00000000 0x0 0x00001000>;
reg-names = "dbi", "ctrl", "atu", "config";
c2c_top = <0x6C 0x007D0000 0x0 0x00001000>;
dma-coherent;
pcie-card;
// IO, check IO_SPACE_LIMIT
// 32bit prefetchable memory
// 32bit non-prefetchable memory
// 64bit prefetchable memory
// 64bit non-prefetchable memory
phys = <&pciephy_0 0>;
phy-names = "pcie-phy";
max-link-speed = <4>;
num-lanes = <8>;
prst = <&port0a 2 0>;
ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00400000>,
<0x42000000 0x0 0x10000000 0x48 0x10000000 0x0 0x04000000>,
<0x02000000 0x0 0x14000000 0x48 0x14000000 0x0 0x04000000>,
<0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>,
<0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>,
<0x43000000 0x40 0x0 0x40 0x0 0x40 0x0>;
cfg_range = <0x6c 0x00000000 0x6c 0x003fffff>;
slv_range = <0x48 0x00000000 0x4b 0xffffffff>;
dw_range = <0x0 0x10000000 0x0 0x17ffffff>;
up_start_addr = <0x04000048 0x00000000>;
status = "okay";
};
//c2c0_x8_0
pcie_rc_1: pcie@6c00400000 {
compatible = "sophgo,bm1690-c2c-pcie-host";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x10 0x1f>;
linux,pci-domain = <1>;
interrupt-parent = <&intc1>;
reg = <0x6c 0x00400000 0x0 0x00001000>,
<0x6c 0x00780000 0x0 0x00001000>,
<0x6c 0x00700000 0x0 0x00004000>,
<0x40 0x00000000 0x0 0x00001000>;
reg-names = "dbi", "ctrl", "atu", "config";
dma-coherent;
pcie-card;
// IO, check IO_SPACE_LIMIT
// 32bit prefetchable memory
// 32bit non-prefetchable memory
// 64bit prefetchable memory
// 64bit non-prefetchable memory
phys = <&pciephy_1 0>;
phy-names = "pcie-phy";
max-link-speed = <4>;
num-lanes = <8>;
prst = <&port0a 6 0>;
ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00400000>,
<0x42000000 0x0 0x00000000 0x40 0x00000000 0x0 0x04000000>,
<0x02000000 0x0 0x04000000 0x40 0x04000000 0x0 0x04000000>,
<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>,
<0x43000000 0x40 0x0 0x40 0x0 0x40 0x0>;
cfg_range = <0x6c 0x00000000 0x6c 0x003fffff>;
slv_range = <0x40 0x00000000 0x43 0xffffffff>;
dw_range = <0x0 0x00000000 0x0 0x7ffffff>;
up_start_addr = <0x04000040 0x00000000>;
status = "disable";
};
//c2c1_x8_1
pcie_rc_4: pcie@6c02000000 {
compatible = "sophgo,bm1690-c2c-pcie-host";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x40 0x4f>;
linux,pci-domain = <4>;
interrupt-parent = <&intc1>;
reg = <0x6c 0x02000000 0x0 0x00001000>,
<0x6c 0x020c0000 0x0 0x00001000>,
<0x6c 0x02300000 0x0 0x00004000>,
<0x58 0x00000000 0x0 0x00001000>;
reg-names = "dbi", "ctrl", "atu", "config";
c2c_top = <0x6C 0x027D0000 0x0 0x00001000>;
dma-coherent;
pcie-card;
// IO, check IO_SPACE_LIMIT
// 32bit prefetchable memory
// 32bit non-prefetchable memory
// 64bit prefetchable memory
// 64bit non-prefetchable memory
phys = <&pciephy_2 0>;
phy-names = "pcie-phy";
max-link-speed = <4>;
num-lanes = <8>;
prst = <&port0a 22 0>;
ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00400000>,
<0x42000000 0x0 0x20000000 0x58 0x20000000 0x0 0x04000000>,
<0x02000000 0x0 0x24000000 0x58 0x24000000 0x0 0x04000000>,
<0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>,
<0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>,
<0x43000000 0x40 0x0 0x40 0x0 0x40 0x0>;
cfg_range = <0x6c 0x02000000 0x6c 0x03ffffff>;
slv_range = <0x58 0x00000000 0x57 0xffffffff>;
dw_range = <0x0 0x30000000 0x0 0x37ffffff>;
up_start_addr = <0x04000058 0x00000000>;
status = "disable";
};
//c2c1_x8_0 cascade
pcie_rc_5: pcie@6c02400000 {
compatible = "sophgo,bm1690-pcie-host";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x50 0x5f>;
linux,pci-domain = <5>;
interrupt-parent = <&intc1>;
reg = <0x6c 0x02400000 0x0 0x00001000>,
<0x6c 0x02780000 0x0 0x00001000>,
<0x6c 0x02700000 0x0 0x00004000>,
<0x50 0x00000000 0x0 0x00001000>;
reg-names = "dbi", "ctrl", "atu", "config";
c2c_top = <0x6C 0x027D0000 0x0 0x00001000>;
dma-coherent;
pcie-card;
// IO, check IO_SPACE_LIMIT
// 32bit prefetchable memory
// 32bit non-prefetchable memory
// 64bit prefetchable memory
// 64bit non-prefetchable memory
phys = <&pciephy_3 0>;
phy-names = "pcie-phy";
max-link-speed = <4>;
num-lanes = <8>;
prst = <&port0a 20 0>;
ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00400000>,
<0x42000000 0x0 0x20000000 0x50 0x20000000 0x0 0x04000000>,
<0x02000000 0x0 0x24000000 0x50 0x24000000 0x0 0x04000000>,
<0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>,
<0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>,
<0x43000000 0x40 0x0 0x40 0x0 0x40 0x0>;
cfg_range = <0x6c 0x02000000 0x6c 0x03ffffff>;
slv_range = <0x50 0x00000000 0x53 0xffffffff>;
dw_range = <0x0 0x20000000 0x0 0x27ffffff>;
up_start_addr = <0x04000050 0x00000000>;
status = "okay";
};
//cxp
pcie_rc_8: pcie@6c08400000 {
compatible = "sophgo,bm1690-c2c-pcie-host";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x80 0x8f>;
linux,pci-domain = <8>;
interrupt-parent = <&intc1>;
reg = <0x6c 0x08400000 0x0 0x00001000>,
<0x6c 0x08780000 0x0 0x00001000>,
<0x6c 0x08700000 0x0 0x00004000>,
<0x60 0x00000000 0x0 0x00010000>;
reg-names = "dbi", "ctrl", "atu", "config";
c2c_top = <0x6C 0x087D0000 0x0 0x00001000>;
dma-coherent;
pcie-card;
// IO, check IO_SPACE_LIMIT
// 32bit prefetchable memory
// 32bit non-prefetchable memory
// 64bit prefetchable memory
// 64bit non-prefetchable memory
phys = <&pciephy_4 0>;
phy-names = "pcie-phy";
max-link-speed = <4>;
num-lanes = <8>;
prst = <&port0a 7 0>;
ranges = <0x01000000 0x0 0x00000000 0x60 0x10000000 0x0 0x00400000>,
<0x42000000 0x0 0x20000000 0x60 0x20000000 0x0 0x04000000>,
<0x02000000 0x0 0x24000000 0x60 0x24000000 0x0 0x04000000>,
<0x43000000 0x62 0x00000000 0x62 0x00000000 0x2 0x00000000>,
<0x03000000 0x61 0x00000000 0x61 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>,
<0x43000000 0x40 0x0 0x40 0x0 0x40 0x0>;
cfg_range = <0x6c 0x08000000 0x6c 0x09ffffff>;
slv_range = <0x60 0x00000000 0x67 0xffffffff>;
dw_range = <0x0 0x40000000 0x0 0x47ffffff>;
up_start_addr = <0x04000060 0x00000000>;
status = "disable";
};
//c2c0_x8_1
pcie_ep_0: pcie_ep@6c00000000 {
compatible = "sophgo,c2c-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x0>;
socket_id = <0x0 0x1>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
//pcie1
reg = <0x6c 0x00000000 0x0 0x00300000>,
<0x6c 0x00300000 0x0 0x00004000>,
<0x6c 0x000c0000 0x0 0x00001000>;
reg-names = "dbi", "atu", "ctrl";
c2c_config_range = <0x6c 0x00000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x007d0000 0x0 0x00001000>;
phys = <&pciephy_0 0>;
phy-names = "pcie-phy";
perst-gpios = <&port0a 24 0>;
status = "disable";
};
//c2c0_x8_0
pcie_ep_1: pcie_ep@6c00400000 {
compatible = "sophgo,c2c-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x1>;
socket_id = <0x0 0x1>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
//pcie1
reg = <0x6c 0x00400000 0x00000000 0x00300000>,
<0x6c 0x00700000 0x00000000 0x00004000>,
<0x6c 0x00780000 0x00000000 0x00001000>;
reg-names = "dbi", "atu", "ctrl";
c2c_config_range = <0x6c 0x00000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x007d0000 0x0 0x00001000>;
perst-gpios = <&port0a 6 0>;
status = "disable";
};
// c2c1_x8_1
pcie_ep_4: pcie_ep@6c02000000 {
compatible = "sophgo,pcie-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x4>;
socket_id = <0x0 0x0>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
reg = <0x6c 0x02000000 0x00000000 0x00300000>,
<0x6c 0x02300000 0x00000000 0x00004000>,
<0x6c 0x020c0000 0x00000000 0x00001000>;
reg-names = "dbi", "atu", "ctrl";
c2c_config_range = <0x6c 0x02000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x027d0000 0x00000000 0x00001000>;
sophgo_card@0 {
compatible = "sophgo,sophgo-card";
reg = <0x1 0xa0000000 0x00000000 0x01400000>,
<0x70 0x101ff000 0x00000000 0x00001000>,
<0x70 0x50000000 0x00000000 0x00001000>;
reg-names = "share-memory", "config_file";
host-channel-num = <1>;
tpu-channel-num = <8>;
media-channel-num = <0>;
tx-channel = <0x0 0x2 0x4 0x6 0x8 0xa 0xc 0xe 0x10>;
rx-channel = <0x1 0x3 0x5 0x7 0x9 0xb 0xd 0xf 0x11>;
channel-size = <0x100000>;
share-memory-type = <1>;
interrupt-parent = <&intc>;
interrupts = <352 IRQ_TYPE_EDGE_RISING>,
<353 IRQ_TYPE_EDGE_RISING>,
<354 IRQ_TYPE_EDGE_RISING>,
<355 IRQ_TYPE_EDGE_RISING>,
<356 IRQ_TYPE_EDGE_RISING>,
<357 IRQ_TYPE_EDGE_RISING>,
<358 IRQ_TYPE_EDGE_RISING>,
<359 IRQ_TYPE_EDGE_RISING>,
<360 IRQ_TYPE_EDGE_RISING>;
clr-irq = <0x6E 0x10000000 0x00000000 0x00000000>,
<0x6E 0x10000004 0x00000000 0x00000000>,
<0x6E 0x10000008 0x00000000 0x00000000>,
<0x6E 0x1000000c 0x00000000 0x00000000>,
<0x6E 0x10000010 0x00000000 0x00000000>,
<0x6E 0x10000014 0x00000000 0x00000000>,
<0x6E 0x10000018 0x00000000 0x00000000>,
<0x6E 0x1000001c 0x00000000 0x00000000>,
<0x6E 0x10000020 0x00000000 0x00000000>;
virtual-msi = <0x0 0x0 0x00000000 0x00000000>,
<0x69 0x0cd00000 0x00000000 0x00000001>,
<0x69 0x1cd00000 0x00000000 0x00000001>,
<0x69 0x2cd00000 0x00000000 0x00000001>,
<0x69 0x3cd00000 0x00000000 0x00000001>,
<0x69 0x4cd00000 0x00000000 0x00000001>,
<0x69 0x5cd00000 0x00000000 0x00000001>,
<0x69 0x6cd00000 0x00000000 0x00000001>,
<0x69 0x7cd00000 0x00000000 0x00000001>;
};
};
//c2c1_x8_0
pcie_ep_5: pcie_ep@6c02400000 {
compatible = "sophgo,c2c-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x5>;
socket_id = <0x0 0x1>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
//pcie1
reg = <0x6c 0x02400000 0x0 0x00300000>,
<0x6c 0x02700000 0x0 0x00004000>,
<0x6c 0x02780000 0x0 0x00001000>;
reg-names = "dbi", "atu", "ctrl";
c2c_config_range = <0x6c 0x02000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x027d0000 0x0 0x00001000>;
phys = <&pciephy_3 0>;
phy-names = "pcie-phy";
perst-gpios = <&port0a 20 0>;
status = "disable";
};
//cxp
pcie_ep_8: pcie_ep@6c08400000 {
compatible = "sophgo,c2c-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x8>;
socket_id = <0x0 0x1>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
//pcie1
reg = <0x6c 0x08400000 0x0 0x00300000>,
<0x6c 0x08700000 0x0 0x00004000>,
<0x6c 0x08780000 0x0 0x00001000>;
reg-names = "dbi", "atu", "ctrl";
c2c_config_range = <0x6c 0x08000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x087d0000 0x0 0x00001000>;
phys = <&pciephy_4 0>;
phy-names = "pcie-phy";
perst-gpios = <&port0a 7 0>;
status = "disable";
};
veth: veth {
compatible = "sg2260, sgveth";
reg = <0x00000000 0x10000000 0x00000000 0x1000>,
<0x00000000 0x10010000 0x00000000 0x70000>,
<0x00000000 0x10080000 0x00000000 0x70000>,
<0x0000006e 0x10000000 0x00000000 0x100>;
reg-names = "shm_reg", "rx_reg", "tx_reg", "irq_reg";
interrupt-parent = <&intc>;
interrupts = <361 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rx";
status = "okay";
};
aliases {
serial0 = &uart0;
pcie_rc_0 = &pcie_rc_0;
pcie_rc_1 = &pcie_rc_1;
pcie_rc_4 = &pcie_rc_4;
pcie_rc_5 = &pcie_rc_5;
pcie_rc_8 = &pcie_rc_8;
pcie_ep_0 = &pcie_ep_0;
pcie_ep_1 = &pcie_ep_1;
pcie_ep_4 = &pcie_ep_4;
pcie_ep_5 = &pcie_ep_5;
pcie_ep_8 = &pcie_ep_8;
};
chosen {
bootargs = "console=ttyS0,115200 earlycon rdinit=/init root=/dev/ram0 rw initrd=0x8b000000,128M maxcpus=4 no5lvl";
stdout-path = "serial0";
};
};

552
arch/riscv/boot/dts/sophgo/bm1690-sc11-ap-chip1.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/sophgo,sg2044-reset.h>
#include <dt-bindings/clock/sophgo,sg2044-clock.h>
#include "bm1690-cpu-ap.dtsi"
#include "sg2044-clock.dtsi"
#include "sg2044-pinctrl.dtsi"
#include "sg2044-peri-sys.dtsi"
#include "bm1690-pcie-intc.dtsi"
/ {
/delete-node/ memory@80200000;
/delete-node/ bm-emmc@703000A000;
};
/ {
sgtpu {
compatible = "sophgo,tpu-1690";
reg = <0x70 0x50000000 0x0 0x8000>,
<0x69 0x08050000 0x0 0x3000>, // TPSYS0_SYS_REG, size should be 0C00
<0x69 0x18050000 0x0 0x3000>,
<0x69 0x28050000 0x0 0x3000>,
<0x69 0x38050000 0x0 0x3000>,
<0x69 0x48050000 0x0 0x3000>,
<0x69 0x58050000 0x0 0x3000>,
<0x69 0x68050000 0x0 0x3000>,
<0x69 0x78050000 0x0 0x3000>;
sophgo_fw_mode = <1>;
};
//c2c0 x8/x4_1
pciephy_0: pciephy_0@6C00f81000 {
compatible = "sophgo,pcie-phy";
#phy-cells = <1>;
reg = <0x6c 0x00f81000 0x0 0x00001000>;
bus-width = <8>;
};
//c2c0 x8/x4_0
pciephy_1: pciephy_1@6C00781000 {
compatible = "sophgo,pcie-phy";
#phy-cells = <1>;
reg = <0x6c 0x00781000 0x0 0x00001000>;
bus-width = <8>;
};
//c2c1 x8/x4_1
pciephy_2: pciephy_2@6C02f81000 {
compatible = "sophgo,pcie-phy";
#phy-cells = <1>;
reg = <0x6c 0x02f81000 0x0 0x00001000>;
bus-width = <8>;
};
//c2c1 x8/x4_0
pciephy_3: pciephy_3@6C02781000 {
compatible = "sophgo,pcie-phy";
#phy-cells = <1>;
reg = <0x6c 0x02781000 0x0 0x00001000>;
bus-width = <8>;
};
//cxp x8/x4
pciephy_4: pciephy_4@6C08781000 {
compatible = "sophgo,pcie-phy";
#phy-cells = <1>;
reg = <0x6c 0x08781000 0x0 0x00001000>;
bus-width = <8>;
};
c2c_enable {
compatible = "sophgo,c2c_enable";
};
//c2c0_x8_1 c2c rc (on board)
pcie_rc_0: pcie@6c00000000 {
compatible = "sophgo,bm1690-c2c-pcie-host";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0x0f>;
linux,pci-domain = <0>;
interrupt-parent = <&intc1>;
reg = <0x6c 0x00000000 0x0 0x00001000>,
<0x6c 0x000c0000 0x0 0x00001000>,
<0x6c 0x00300000 0x0 0x00004000>,
<0x48 0x00000000 0x0 0x00001000>;
reg-names = "dbi", "ctrl", "atu", "config";
c2c_top = <0x6C 0x007D0000 0x0 0x00001000>;
dma-coherent;
pcie-card;
// IO, check IO_SPACE_LIMIT
// 32bit prefetchable memory
// 32bit non-prefetchable memory
// 64bit prefetchable memory
// 64bit non-prefetchable memory
phys = <&pciephy_0 0>;
phy-names = "pcie-phy";
max-link-speed = <4>;
num-lanes = <8>;
prst = <&port0a 2 0>;
ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00400000>,
<0x42000000 0x0 0x10000000 0x48 0x10000000 0x0 0x04000000>,
<0x02000000 0x0 0x14000000 0x48 0x14000000 0x0 0x04000000>,
<0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>,
<0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>,
<0x43000000 0x40 0x0 0x40 0x0 0x40 0x0>;
cfg_range = <0x6c 0x00000000 0x6c 0x003fffff>;
slv_range = <0x48 0x00000000 0x4b 0xffffffff>;
dw_range = <0x0 0x10000000 0x0 0x17ffffff>;
up_start_addr = <0x04000048 0x00000000>;
status = "disable";
};
//c2c0_x8_0
pcie_rc_1: pcie@6c00400000 {
compatible = "sophgo,bm1690-c2c-pcie-host";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x10 0x1f>;
linux,pci-domain = <1>;
interrupt-parent = <&intc1>;
reg = <0x6c 0x00400000 0x0 0x00001000>,
<0x6c 0x00780000 0x0 0x00001000>,
<0x6c 0x00700000 0x0 0x00004000>,
<0x40 0x00000000 0x0 0x00001000>;
reg-names = "dbi", "ctrl", "atu", "config";
dma-coherent;
pcie-card;
// IO, check IO_SPACE_LIMIT
// 32bit prefetchable memory
// 32bit non-prefetchable memory
// 64bit prefetchable memory
// 64bit non-prefetchable memory
phys = <&pciephy_1 0>;
phy-names = "pcie-phy";
max-link-speed = <4>;
num-lanes = <8>;
prst = <&port0a 6 0>;
ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00400000>,
<0x42000000 0x0 0x00000000 0x40 0x00000000 0x0 0x04000000>,
<0x02000000 0x0 0x04000000 0x40 0x04000000 0x0 0x04000000>,
<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>,
<0x43000000 0x40 0x0 0x40 0x0 0x40 0x0>;
cfg_range = <0x6c 0x00000000 0x6c 0x003fffff>;
slv_range = <0x40 0x00000000 0x43 0xffffffff>;
dw_range = <0x0 0x00000000 0x0 0x7ffffff>;
up_start_addr = <0x04000040 0x00000000>;
status = "disable";
};
//c2c1_x8_1
pcie_rc_4: pcie@6c02000000 {
compatible = "sophgo,bm1690-c2c-pcie-host";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x40 0x4f>;
linux,pci-domain = <4>;
interrupt-parent = <&intc1>;
reg = <0x6c 0x02000000 0x0 0x00001000>,
<0x6c 0x020c0000 0x0 0x00001000>,
<0x6c 0x02300000 0x0 0x00004000>,
<0x58 0x00000000 0x0 0x00001000>;
reg-names = "dbi", "ctrl", "atu", "config";
c2c_top = <0x6C 0x027D0000 0x0 0x00001000>;
dma-coherent;
pcie-card;
// IO, check IO_SPACE_LIMIT
// 32bit prefetchable memory
// 32bit non-prefetchable memory
// 64bit prefetchable memory
// 64bit non-prefetchable memory
phys = <&pciephy_2 0>;
phy-names = "pcie-phy";
max-link-speed = <4>;
num-lanes = <8>;
prst = <&port0a 22 0>;
ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00400000>,
<0x42000000 0x0 0x20000000 0x58 0x20000000 0x0 0x04000000>,
<0x02000000 0x0 0x24000000 0x58 0x24000000 0x0 0x04000000>,
<0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>,
<0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>,
<0x43000000 0x40 0x0 0x40 0x0 0x40 0x0>;
cfg_range = <0x6c 0x02000000 0x6c 0x03ffffff>;
slv_range = <0x58 0x00000000 0x57 0xffffffff>;
dw_range = <0x0 0x30000000 0x0 0x37ffffff>;
up_start_addr = <0x04000058 0x00000000>;
status = "disable";
};
//c2c1_x8_0
pcie_rc_5: pcie@6c02400000 {
compatible = "sophgo,bm1690-c2c-pcie-host";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x50 0x5f>;
linux,pci-domain = <5>;
interrupt-parent = <&intc1>;
reg = <0x6c 0x02400000 0x0 0x00001000>,
<0x6c 0x02780000 0x0 0x00001000>,
<0x6c 0x02700000 0x0 0x00004000>,
<0x50 0x00000000 0x0 0x00001000>;
reg-names = "dbi", "ctrl", "atu", "config";
c2c_top = <0x6C 0x027D0000 0x0 0x00001000>;
dma-coherent;
pcie-card;
// IO, check IO_SPACE_LIMIT
// 32bit prefetchable memory
// 32bit non-prefetchable memory
// 64bit prefetchable memory
// 64bit non-prefetchable memory
phys = <&pciephy_3 0>;
phy-names = "pcie-phy";
max-link-speed = <4>;
num-lanes = <8>;
prst = <&port0a 20 0>;
ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00400000>,
<0x42000000 0x0 0x20000000 0x50 0x20000000 0x0 0x04000000>,
<0x02000000 0x0 0x24000000 0x50 0x24000000 0x0 0x04000000>,
<0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>,
<0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>,
<0x43000000 0x40 0x0 0x40 0x0 0x40 0x0>;
cfg_range = <0x6c 0x02000000 0x6c 0x03ffffff>;
slv_range = <0x50 0x00000000 0x53 0xffffffff>;
dw_range = <0x0 0x20000000 0x0 0x27ffffff>;
up_start_addr = <0x04000050 0x00000000>;
status = "okay";
};
//cxp
pcie_rc_8: pcie@6c08400000 {
compatible = "sophgo,bm1690-c2c-pcie-host";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x80 0x8f>;
linux,pci-domain = <8>;
interrupt-parent = <&intc1>;
reg = <0x6c 0x08400000 0x0 0x00001000>,
<0x6c 0x08780000 0x0 0x00001000>,
<0x6c 0x08700000 0x0 0x00004000>,
<0x60 0x00000000 0x0 0x00010000>;
reg-names = "dbi", "ctrl", "atu", "config";
c2c_top = <0x6C 0x087D0000 0x0 0x00001000>;
dma-coherent;
pcie-card;
// IO, check IO_SPACE_LIMIT
// 32bit prefetchable memory
// 32bit non-prefetchable memory
// 64bit prefetchable memory
// 64bit non-prefetchable memory
phys = <&pciephy_4 0>;
phy-names = "pcie-phy";
max-link-speed = <4>;
num-lanes = <8>;
prst = <&port0a 7 0>;
ranges = <0x01000000 0x0 0x00000000 0x60 0x10000000 0x0 0x00400000>,
<0x42000000 0x0 0x20000000 0x60 0x20000000 0x0 0x04000000>,
<0x02000000 0x0 0x24000000 0x60 0x24000000 0x0 0x04000000>,
<0x43000000 0x62 0x00000000 0x62 0x00000000 0x2 0x00000000>,
<0x03000000 0x61 0x00000000 0x61 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>,
<0x43000000 0x40 0x0 0x40 0x0 0x40 0x0>;
cfg_range = <0x6c 0x08000000 0x6c 0x09ffffff>;
slv_range = <0x60 0x00000000 0x67 0xffffffff>;
dw_range = <0x0 0x40000000 0x0 0x47ffffff>;
up_start_addr = <0x04000060 0x00000000>;
status = "disable";
};
//c2c0_x8_1 c2c ep (on board)
pcie_ep_0: pcie_ep@6c00000000 {
compatible = "sophgo,c2c-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x0>;
socket_id = <0x0 0x1>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
//pcie1
reg = <0x6c 0x00000000 0x0 0x00300000>,
<0x6c 0x00300000 0x0 0x00004000>,
<0x6c 0x000c0000 0x0 0x00001000>;
reg-names = "dbi", "atu", "ctrl";
c2c_config_range = <0x6c 0x00000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x007d0000 0x0 0x00001000>;
phys = <&pciephy_0 0>;
phy-names = "pcie-phy";
perst-gpios = <&port0a 24 0>;
status = "okay";
};
//c2c0_x8_0
pcie_ep_1: pcie_ep@6c00400000 {
compatible = "sophgo,pcie-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x1>;
socket_id = <0x0 0x1>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
//pcie1
reg = <0x6c 0x00400000 0x00000000 0x00300000>,
<0x6c 0x00700000 0x00000000 0x00004000>,
<0x6c 0x00780000 0x00000000 0x00001000>;
reg-names = "dbi", "atu", "ctrl";
c2c_config_range = <0x6c 0x00000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x007d0000 0x0 0x00001000>;
status = "okay";
sophgo_card@0 {
compatible = "sophgo,sophgo-card";
reg = <0x1 0xa0000000 0x00000000 0x01400000>,
<0x70 0x50000000 0x00000000 0x00001000>,
<0x70 0x101ff000 0x00000000 0x00001000>;
reg-names = "share-memory", "top-reg", "config_file";
host-channel-num = <1>;
tpu-channel-num = <8>;
media-channel-num = <0>;
tx-channel = <0x0 0x2 0x4 0x6 0x8 0xa 0xc 0xe 0x10>;
rx-channel = <0x1 0x3 0x5 0x7 0x9 0xb 0xd 0xf 0x11>;
channel-size = <0x100000>;
share-memory-type = <1>;
interrupt-parent = <&intc>;
interrupts = <352 IRQ_TYPE_EDGE_RISING>,
<353 IRQ_TYPE_EDGE_RISING>,
<354 IRQ_TYPE_EDGE_RISING>,
<355 IRQ_TYPE_EDGE_RISING>,
<356 IRQ_TYPE_EDGE_RISING>,
<357 IRQ_TYPE_EDGE_RISING>,
<358 IRQ_TYPE_EDGE_RISING>,
<359 IRQ_TYPE_EDGE_RISING>,
<360 IRQ_TYPE_EDGE_RISING>;
clr-irq = <0x6E 0x10000000 0x00000000 0x00000000>,
<0x6E 0x10000004 0x00000000 0x00000000>,
<0x6E 0x10000008 0x00000000 0x00000000>,
<0x6E 0x1000000c 0x00000000 0x00000000>,
<0x6E 0x10000010 0x00000000 0x00000000>,
<0x6E 0x10000014 0x00000000 0x00000000>,
<0x6E 0x10000018 0x00000000 0x00000000>,
<0x6E 0x1000001c 0x00000000 0x00000000>,
<0x6E 0x10000020 0x00000000 0x00000000>;
virtual-msi = <0x0 0x0 0x00000000 0x00000000>,
<0x69 0x0cd00000 0x00000000 0x00000001>,
<0x69 0x1cd00000 0x00000000 0x00000001>,
<0x69 0x2cd00000 0x00000000 0x00000001>,
<0x69 0x3cd00000 0x00000000 0x00000001>,
<0x69 0x4cd00000 0x00000000 0x00000001>,
<0x69 0x5cd00000 0x00000000 0x00000001>,
<0x69 0x6cd00000 0x00000000 0x00000001>,
<0x69 0x7cd00000 0x00000000 0x00000001>;
};
};
//c2c1_x8_1
pcie_ep_4: pcie_ep@6c02000000 {
compatible = "sophgo,c2c-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x4>;
socket_id = <0x0 0x1>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
//pcie1
reg = <0x6c 0x02000000 0x0 0x00300000>,
<0x6c 0x02300000 0x0 0x00004000>,
<0x6c 0x020c0000 0x0 0x00001000>;
reg-names = "dbi", "atu", "ctrl";
c2c_config_range = <0x6c 0x02000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x027d0000 0x0 0x00001000>;
phys = <&pciephy_2 0>;
phy-names = "pcie-phy";
perst-gpios = <&port0a 22 0>;
status = "disable";
};
//c2c1_x8_0
pcie_ep_5: pcie_ep@6c02400000 {
compatible = "sophgo,c2c-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x5>;
socket_id = <0x0 0x1>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
//pcie1
reg = <0x6c 0x02400000 0x0 0x00300000>,
<0x6c 0x02700000 0x0 0x00004000>,
<0x6c 0x02780000 0x0 0x00001000>;
reg-names = "dbi", "atu", "ctrl";
c2c_config_range = <0x6c 0x02000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x027d0000 0x0 0x00001000>;
phys = <&pciephy_3 0>;
phy-names = "pcie-phy";
perst-gpios = <&port0a 20 0>;
status = "disable";
};
//cxp
pcie_ep_8: pcie_ep@6c08400000 {
compatible = "sophgo,c2c-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x8>;
socket_id = <0x0 0x1>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
//pcie1
reg = <0x6c 0x08400000 0x0 0x00300000>,
<0x6c 0x08700000 0x0 0x00004000>,
<0x6c 0x08780000 0x0 0x00001000>;
reg-names = "dbi", "atu", "ctrl";
c2c_config_range = <0x6c 0x08000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x087d0000 0x0 0x00001000>;
phys = <&pciephy_4 0>;
phy-names = "pcie-phy";
perst-gpios = <&port0a 7 0>;
status = "disable";
};
};
/ {
memory@80200000 {
device_type = "memory";
reg = <0x00000000 0x80200000 0x00000000 0x1fe00000>;
};
uart0: serial@7030000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x30000000 0x00000000 0x00001000>;
interrupt-parent = <&intc>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
aliases {
serial0 = &uart0;
pcie_rc_0 = &pcie_rc_0;
pcie_rc_1 = &pcie_rc_1;
pcie_rc_4 = &pcie_rc_4;
pcie_rc_5 = &pcie_rc_5;
pcie_rc_8 = &pcie_rc_8;
pcie_ep_0 = &pcie_ep_0;
pcie_ep_1 = &pcie_ep_1;
pcie_ep_4 = &pcie_ep_4;
pcie_ep_5 = &pcie_ep_5;
pcie_ep_8 = &pcie_ep_8;
};
chosen {
bootargs = "console=ttyS0,115200 earlycon rdinit=/init root=/dev/ram0 rw initrd=0x8b000000,128M maxcpus=4 no5lvl";
stdout-path = "serial0";
};
};

183
arch/riscv/boot/dts/sophgo/bm1690-sc11-ap-chip2.dts
View File

@ -1,183 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/sophgo,sg2044-reset.h>
#include <dt-bindings/clock/sophgo,sg2044-clock.h>
#include "bm1690-cpu-ap.dtsi"
#include "sg2044-clock.dtsi"
#include "sg2044-pinctrl.dtsi"
#include "sg2044-peri-sys.dtsi"
#include "bm1690-pcie-intc.dtsi"
/ {
/delete-node/ memory@80200000;
/delete-node/ bm-emmc@703000A000;
};
/ {
memory@80200000 {
device_type = "memory";
reg = <0x00000000 0x80200000 0x00000000 0x1fe00000>;
};
uart0: serial@7030000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x30000000 0x00000000 0x00001000>;
interrupt-parent = <&intc>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
};
aliases {
serial0 = &uart0;
};
chosen {
bootargs = "console=ttyS0,115200 earlycon rdinit=/init root=/dev/ram0 rw initrd=0x8b000000,128M maxcpus=4 no5lvl";
stdout-path = "serial0";
};
};
/ {
soc {
sgtpu {
compatible = "sophgo,tpu-1690";
reg = <0x70 0x50000000 0x0 0x8000>,
<0x69 0x08050000 0x0 0x3000>, // TPSYS0_SYS_REG, size should be 0C00
<0x69 0x18050000 0x0 0x3000>,
<0x69 0x28050000 0x0 0x3000>,
<0x69 0x38050000 0x0 0x3000>,
<0x69 0x48050000 0x0 0x3000>,
<0x69 0x58050000 0x0 0x3000>,
<0x69 0x68050000 0x0 0x3000>,
<0x69 0x78050000 0x0 0x3000>;
sophgo_fw_mode = <1>;
};
//c2c0 x8/x4_1
pciephy_1: pciephy_0@6C00f81000 {
compatible = "sophgo,pcie-phy";
#phy-cells = <1>;
reg = <0x6c 0x00f81000 0x0 0x00001000>;
bus-width = <8>;
};
//c2c0_x8_1
pcie_ep@0 {
compatible = "sophgo,c2c-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x1>;
socket_id = <0x0 0x1>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
//pcie1
reg = <0x6c 0x00000000 0x0 0x00001000>,
<0x6c 0x00300000 0x0 0x00004000>,
<0x6c 0x000c0000 0x0 0x00001000>;
reg-names = "dbi", "atu", "ctrl";
c2c_config_range = <0x6c 0x00000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x007d0000 0x0 0x00001000>;
phys = <&pciephy_1 0>;
phy-names = "pcie-phy";
perst = <&port0a 2 0>;
};
//c2c0_x8_0
pcie_ep@1 {
compatible = "sophgo,pcie-link-ep";
chip_type = "bm1690";
#address-cells = <2>;
#size-cells = <2>;
ranges;//this is must, must, must, must
pcie_id = <0x0 0x1>;
socket_id = <0x0 0x1>;
speed = <0x0 0x5>;
lane_num = <0x0 0x8>;
func_num = <0x0 0x1>;
//pcie1
reg = <0x6c 0x00400000 0x00000000 0x00300000>,
<0x6c 0x00700000 0x00000000 0x00004000>,
<0x6c 0x00780000 0x00000000 0x00001000>;
reg-names = "dbi", "atu", "ctrl";
c2c_config_range = <0x6c 0x00000000 0x00000000 0x01ffffff>;
c2c_top = <0x6c 0x007d0000 0x0 0x00001000>;
sophgo_card@0 {
compatible = "sophgo,sophgo-card";
reg = <0x1 0xa0000000 0x00000000 0x01400000>,
<0x70 0x50000000 0x00000000 0x00001000>,
<0x70 0x101ff000 0x00000000 0x00001000>;
reg-names = "share-memory", "top-reg", "config_file";
host-channel-num = <1>;
tpu-channel-num = <8>;
media-channel-num = <0>;
tx-channel = <0x0 0x2 0x4 0x6 0x8 0xa 0xc 0xe 0x10>;
rx-channel = <0x1 0x3 0x5 0x7 0x9 0xb 0xd 0xf 0x11>;
channel-size = <0x100000>;
share-memory-type = <1>;
interrupt-parent = <&intc>;
interrupts = <352 IRQ_TYPE_EDGE_RISING>,
<353 IRQ_TYPE_EDGE_RISING>,
<354 IRQ_TYPE_EDGE_RISING>,
<355 IRQ_TYPE_EDGE_RISING>,
<356 IRQ_TYPE_EDGE_RISING>,
<357 IRQ_TYPE_EDGE_RISING>,
<358 IRQ_TYPE_EDGE_RISING>,
<359 IRQ_TYPE_EDGE_RISING>,
<360 IRQ_TYPE_EDGE_RISING>;
clr-irq = <0x6E 0x10000000 0x00000000 0x00000000>,
<0x6E 0x10000004 0x00000000 0x00000000>,
<0x6E 0x10000008 0x00000000 0x00000000>,
<0x6E 0x1000000c 0x00000000 0x00000000>,
<0x6E 0x10000010 0x00000000 0x00000000>,
<0x6E 0x10000014 0x00000000 0x00000000>,
<0x6E 0x10000018 0x00000000 0x00000000>,
<0x6E 0x1000001c 0x00000000 0x00000000>,
<0x6E 0x10000020 0x00000000 0x00000000>;
virtual-msi = <0x0 0x0 0x00000000 0x00000000>,
<0x69 0x0cd00000 0x00000000 0x00000001>,
<0x69 0x1cd00000 0x00000000 0x00000001>,
<0x69 0x2cd00000 0x00000000 0x00000001>,
<0x69 0x3cd00000 0x00000000 0x00000001>,
<0x69 0x4cd00000 0x00000000 0x00000001>,
<0x69 0x5cd00000 0x00000000 0x00000001>,
<0x69 0x6cd00000 0x00000000 0x00000001>,
<0x69 0x7cd00000 0x00000000 0x00000001>;
};
};
veth: veth {
compatible = "sg2260, sgveth";
reg = <0x00000000 0x10000000 0x00000000 0x1000>,
<0x00000000 0x10010000 0x00000000 0x70000>,
<0x00000000 0x10080000 0x00000000 0x70000>,
<0x0000006e 0x10000000 0x00000000 0x100>;
reg-names = "shm_reg", "rx_reg", "tx_reg", "irq_reg";
interrupt-parent = <&intc>;
interrupts = <361 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rx";
status = "disable";
};
};
};

6
arch/riscv/configs/sophgo_bm1690_ap_normal_defconfig
View File

@ -33,7 +33,8 @@ CONFIG_SOC_SOPHGO=y
# CONFIG_ERRATA_THEAD_PMU is not set
CONFIG_SMP=y
CONFIG_NR_CPUS=4
CONFIG_HZ_100=y
CONFIG_HZ_100=n
CONFIG_HZ_300=y
CONFIG_KEXEC=y
CONFIG_KEXEC_FILE=y
# CONFIG_STACKPROTECTOR is not set
@ -187,4 +188,5 @@ CONFIG_RCU_EQS_DEBUG=y
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_MEMTEST=y
CONFIG_SOPHGO_VTTY=y
CONFIG_SOPHGO_VTTY=y
CONFIG_PREEMPT=y

5
drivers/pci/controller/dwc/pcie-dw-sophgo.c
View File

@ -461,11 +461,6 @@ static int sophgo_dw_pcie_get_resources(struct sophgo_dw_pcie *pcie)
pcie->pe_rst = of_get_named_gpio(dev->of_node, "prst", 0); //TODO:default high? or low?
dev_err(dev, "perst:[gpio%d]\n", pcie->pe_rst);
pcie->c2c_prst = of_get_named_gpio(dev->of_node, "c2c_prst", 0);
dev_err(dev, "c2c prst:%d\n", pcie->c2c_prst);
gpio_direction_output(pcie->c2c_prst, 0);
gpio_set_value(pcie->c2c_prst, 0);
}
return 0;

1
drivers/pci/controller/dwc/pcie-dw-sophgo.h
View File

@ -106,7 +106,6 @@ struct sophgo_dw_pcie {
struct reset_control_bulk_data app_rsts[DW_PCIE_NUM_APP_RSTS];
struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS];
int pe_rst;
int c2c_prst;
struct phy *phy;
};

28
drivers/soc/sophgo/pcie_device/pcie_device.c
View File

@ -95,7 +95,7 @@ static int pci_platform_init(struct pci_dev *pdev)
pci_err(pdev, "cannot reserve memory region\n");
goto err1_out;
}
#if 0
// BAR0
hdev->BarPhys[0] = pci_resource_start(pdev, 0);
hdev->BarLength[0] = pci_resource_len(pdev, 0);
@ -120,12 +120,12 @@ static int pci_platform_init(struct pci_dev *pdev)
hdev->BarVirt[3] = pci_iomap(pdev, 4, 0);
for (i = 0; i < 4; i++) {
pci_info(pdev, "BAR%d address 0x%p/0x%llx length 0x%llx\n",
pci_info(pdev, "BAR%d address 0x%px/0x%llx length 0x%llx\n",
i, hdev->BarVirt[i],
hdev->BarPhys[i],
hdev->BarLength[i]);
}
#endif
pci_set_master(pdev);
if (pci_try_set_mwi(pdev))
@ -193,7 +193,7 @@ static void bm1690_map_bar(struct p_dev *hdev, struct pci_dev *pdev)
REG_WRITE32(atu_base_addr, 0x300, 0);
REG_WRITE32(atu_base_addr, 0x304, 0x80000100);
REG_WRITE32(atu_base_addr, 0x308, (u32)(hdev->BarPhys[1] & 0xffffffff)); //src addr
REG_WRITE32(atu_base_addr, 0x30C, hdev->BarPhys[1] >> 32);
REG_WRITE32(atu_base_addr, 0x30C, 0);
REG_WRITE32(atu_base_addr, 0x310, (u32)(hdev->BarPhys[1] & 0xffffffff) + 0x1fffff); //size 2M
REG_WRITE32(atu_base_addr, 0x314, 0x10000000); //dst addr
REG_WRITE32(atu_base_addr, 0x318, 0x70);
@ -204,15 +204,17 @@ static void bm1690_map_bar(struct p_dev *hdev, struct pci_dev *pdev)
REG_WRITE32(atu_base_addr, 0x504, 0x80000100);
REG_WRITE32(atu_base_addr, 0x508, (u32)(hdev->BarPhys[1] & 0xffffffff)
+ BAR1_PART2_OFFSET); //src addr
REG_WRITE32(atu_base_addr, 0x50C, hdev->BarPhys[1] >> 32);
REG_WRITE32(atu_base_addr, 0x50C, 0);
REG_WRITE32(atu_base_addr, 0x510, (u32)(hdev->BarPhys[1] & 0xffffffff)
+ BAR1_PART2_OFFSET + 0x7fff); //size 3M
REG_WRITE32(atu_base_addr, 0x514, 0x50000000); //dst addr
REG_WRITE32(atu_base_addr, 0x518, 0x70);
hdev->top_bar_vaddr = hdev->BarVirt[1] + BAR1_PART2_OFFSET;
val = top_reg_read(hdev, 0x0);
pr_info("[Top_reg_0] the val = 0x%x\n", val);
val = top_reg_read(hdev, 0x4);
pr_info("[Top_reg_read] the val = 0x%x\n", val);
pr_info("[Top_reg_1] the val = 0x%x\n", val);
c2c_id = (val >> 3) & 0x3;
if (c2c_id == 2)
c2c_id = 4;
@ -223,7 +225,7 @@ static void bm1690_map_bar(struct p_dev *hdev, struct pci_dev *pdev)
REG_WRITE32(atu_base_addr, 0x704, 0x80000100);
REG_WRITE32(atu_base_addr, 0x708, (u32)(hdev->BarPhys[1] & 0xffffffff)
+ BAR1_PART1_OFFSET); //src addr
REG_WRITE32(atu_base_addr, 0x70C, hdev->BarPhys[1] >> 32);
REG_WRITE32(atu_base_addr, 0x70C, 0);
REG_WRITE32(atu_base_addr, 0x710, (u32)(hdev->BarPhys[1] & 0xffffffff)
+ BAR1_PART1_OFFSET + 0x7ffff); //size 3M
REG_WRITE32(atu_base_addr, 0x714, (c2c_base & 0xffffffff)); //dst addr
@ -235,7 +237,7 @@ static void bm1690_map_bar(struct p_dev *hdev, struct pci_dev *pdev)
REG_WRITE32(atu_base_addr, 0x904, 0x80000100);
REG_WRITE32(atu_base_addr, 0x908, (u32)(hdev->BarPhys[1] & 0xffffffff)
+ BAR1_PART3_OFFSET); //src addr
REG_WRITE32(atu_base_addr, 0x90C, hdev->BarPhys[1] >> 32);
REG_WRITE32(atu_base_addr, 0x90C, 0);
REG_WRITE32(atu_base_addr, 0x910, (u32)(hdev->BarPhys[1] & 0xffffffff)
+ BAR1_PART3_OFFSET + 0x1fff);//size 256K
REG_WRITE32(atu_base_addr, 0x914, 0x10000000); //dst addr
@ -246,7 +248,7 @@ static void bm1690_map_bar(struct p_dev *hdev, struct pci_dev *pdev)
REG_WRITE32(atu_base_addr, 0xb04, 0x80000100);
REG_WRITE32(atu_base_addr, 0xb08, (u32)(hdev->BarPhys[1] & 0xffffffff)
+ BAR1_PART4_OFFSET); //src addr
REG_WRITE32(atu_base_addr, 0xb0C, hdev->BarPhys[1] >> 32);
REG_WRITE32(atu_base_addr, 0xb0C, 0);
REG_WRITE32(atu_base_addr, 0xb10, (u32)(hdev->BarPhys[1] & 0xffffffff)
+ BAR1_PART4_OFFSET + 0xfffff); //size 3M
REG_WRITE32(atu_base_addr, 0xb14, 0x40000000); //dst addr
@ -354,17 +356,17 @@ static int pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
pci_platform_init(pdev);
writel(0x5, top_base + 0x1c4);
#if 0
bm1690_map_bar(hdev, pdev);
bm1690_map_bar(hdev, pdev);
#if 0
ret = build_pcie_info(hdev);
if (ret)
goto failed;
pr_info("[pcie device]:bus%d probe done\n", hdev->bus_num);
config_ep_huge_bar(hdev);
#endif
config_ep_huge_bar(hdev);
return 0;
failed:
return ret;

16
drivers/soc/sophgo/pcie_ep/ap_pcie_ep.c
View File

@ -147,7 +147,10 @@ static irqreturn_t perst_interrupt(int irq, void *dev_id)
{
struct sophgo_pcie_ep *sg_ep = (struct sophgo_pcie_ep *)dev_id;
pr_err("%s get perst interrupt\n", sg_ep->name);
pr_err("%s get perst interrupt, clr irq va:0x%llx\n", sg_ep->name, (uint64_t)sg_ep->clr_irq);
if (sg_ep->clr_irq)
writel(sg_ep->clr_irq_data, sg_ep->clr_irq);
schedule_delayed_work(&sg_ep->link_work, 0);
@ -220,15 +223,10 @@ static int sophgo_c2c_link_probe(struct platform_device *pdev)
struct sophgo_pcie_ep *sg_ep = dev_get_drvdata(dev);
int ret;
sg_ep->perst_irqnr = gpio_to_irq(sg_ep->perst_gpio);
if (sg_ep->perst_irqnr < 0) {
pr_err("failed get pcie%d perst irq nr\n", (int)sg_ep->ep_info.pcie_id);
return -1;
}
INIT_DELAYED_WORK(&sg_ep->link_work, c2c_init_ep);
sophgo_c2c_ep_enable_probe(pdev);
ret = request_irq(sg_ep->perst_irqnr, perst_interrupt, IRQF_TRIGGER_HIGH,
ret = request_irq(sg_ep->perst_irqnr, perst_interrupt, IRQF_TRIGGER_RISING,
sg_ep->name, sg_ep);
if (ret < 0) {
pr_err("%s request int failed\n", sg_ep->name);
@ -257,11 +255,11 @@ static int sophgo_pcie_ep_get_dtbif(struct platform_device *pdev, uint64_t link_
if (strcmp(chip_type, "bm1684x") == 0) {
sg_ep->chip_type = CHIP_BM1684X;
bm1684x_ep_int(pdev);
pr_info("found bm1684x pcie ep\n");
dev_info(dev, "found bm1684x pcie ep\n");
} else if (strcmp(chip_type, "bm1690") == 0) {
sg_ep->chip_type = CHIP_BM1690;
bm1690_ep_int(pdev);
pr_info("found bm1690 pcie ep\n");
dev_info(dev, "found bm1690 pcie ep\n");
} else {
pr_err("unknown chip type %s\n", chip_type);
return -EINVAL;

5
drivers/soc/sophgo/pcie_ep/ap_pcie_ep.h
View File

@ -69,14 +69,17 @@ struct sophgo_pcie_ep {
void __iomem *ctrl_reg_base;
void __iomem *atu_base;
void __iomem *dbi_base;
uint64_t dbi_base_pa;
void __iomem *c2c_top_base;
void __iomem *sii_base;
void __iomem *share_vector_reg;
void __iomem *clr_irq;
uint64_t clr_irq_data;
struct phy *phy;
uint64_t c2c_config_base;
uint64_t c2c_config_size;
char name[32];
int perst_gpio;
struct gpio_desc *perst_gpio;
int perst_irqnr;
struct pcie_info ep_info;
uint64_t vector_allocated;

50
drivers/soc/sophgo/pcie_ep/bm1690_ep_init.c
View File

@ -156,6 +156,11 @@ void pcie_config_ep_function(struct sophgo_pcie_ep *sg_ep)
val = (val & 0xfffffffe) | 0x1;
writel(val, (pcie_dbi_base + 0x8bc));
//config subdevice id
writel(PCIE_DATA_LINK_C2C << 16, pcie_dbi_base + SUBSYSTEM_ID_SUBSYTEM_VENDOR_DI_REG);
pr_err("config dbi subdevice id:0x%x\n", readl(pcie_dbi_base + SUBSYSTEM_ID_SUBSYTEM_VENDOR_DI_REG));
val = readl(pcie_dbi_base + 0xc);
if (func_num == 0x1)
writel((val & (~(1 << 23))), (pcie_dbi_base + 0xc));
@ -376,6 +381,16 @@ static int pcie_config_soft_cold_reset(struct sophgo_pcie_ep *pcie)
return 0;
}
static void pcie_config_bar0_iatu(struct sophgo_pcie_ep *sg_ep)
{
void __iomem *atu_base = sg_ep->atu_base;
writel((sg_ep->dbi_base_pa & 0xffffffff), (atu_base + 0x114));
writel(0x6c, (atu_base + 0x118));
writel(0x0, (atu_base + 0x100));
writel(0xC0080000, (atu_base + 0x104));
}
void bm1690_pcie_init_link(struct sophgo_pcie_ep *sg_ep)
{
pr_info("begin c2c ep init\n");
@ -394,7 +409,7 @@ void bm1690_pcie_init_link(struct sophgo_pcie_ep *sg_ep)
pcie_config_ep_function(sg_ep);
pcie_config_axi_route(sg_ep);
pcie_config_ep_bar(sg_ep);
pcie_config_bar0_iatu(sg_ep);
#ifdef PCIE_EP_HUGE_BAR
if (link_mode == PCIE_CHIPS_C2C_LINK)
pcie_config_ep_huge_bar(c2c_id, wrapper_id, phy_id, 0);
@ -564,6 +579,7 @@ int bm1690_ep_int(struct platform_device *pdev)
int ret;
uint64_t start;
uint64_t size;
uint64_t clr_irq_pa;
ret = of_property_read_u64(dev_node, "pcie_id", &sg_ep->ep_info.pcie_id);
if (ret)
@ -609,6 +625,7 @@ int bm1690_ep_int(struct platform_device *pdev)
dev_err(dev, "dbi base ioremap failed\n");
goto unmap_config;
}
sg_ep->dbi_base_pa = regs->start;
regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
if (!regs) {
@ -637,14 +654,33 @@ int bm1690_ep_int(struct platform_device *pdev)
ret = of_property_read_u64_index(dev_node, "c2c_config_range", 0, &sg_ep->c2c_config_base);
ret = of_property_read_u64_index(dev_node, "c2c_config_range", 1, &sg_ep->c2c_config_size);
if (sg_ep->ep_info.link_role == PCIE_DATA_LINK_C2C) {
sg_ep->perst_gpio = of_get_named_gpio(dev->of_node, "perst", 0);
if (sg_ep->perst_gpio < 0) {
pr_err("failed get perst gpio\n");
goto unmap_c2c_top;
sg_ep->perst_irqnr = platform_get_irq(pdev, 0);
if (sg_ep->perst_irqnr < 0) {
dev_err(dev, "not get mtli irq, so we try gpio irq\n");
sg_ep->perst_gpio = devm_gpiod_get_index(dev, "perst", 0, GPIOD_IN);
if (IS_ERR(sg_ep->perst_gpio)) {
pr_err("failed get perst gpio\n");
goto unmap_c2c_top;
}
gpiod_set_debounce(sg_ep->perst_gpio, 1000);
sg_ep->perst_irqnr = gpiod_to_irq(sg_ep->perst_gpio);
if (sg_ep->perst_irqnr < 0) {
pr_err("failed get pcie%d perst irq nr\n", (int)sg_ep->ep_info.pcie_id);
goto unmap_c2c_top;
} else {
dev_err(dev, "get gpio irq:%d\n", sg_ep->perst_irqnr);
}
} else {
ret = of_property_read_u64_index(dev_node, "clr-irq", 0, &clr_irq_pa);
ret = of_property_read_u64_index(dev_node, "clr-irq", 1, &sg_ep->clr_irq_data);
if (ret == 0) {
sg_ep->clr_irq = ioremap(clr_irq_pa, 0x4);
dev_err(dev, "get mtli irq:%d, clr irq pa:0x%llx, va:0x%llx\n", sg_ep->perst_irqnr,
clr_irq_pa, (uint64_t)sg_ep->clr_irq);
}
}
gpio_direction_input(sg_ep->perst_gpio);
sg_ep->phy = devm_of_phy_get(dev, dev->of_node, "pcie-phy");
}

4
drivers/soc/sophgo/pcie_ep/bm1690_ep_init.h
View File

@ -40,6 +40,7 @@
#define C2C_TOP_MSI_GEN_MODE_REG 0xd8
#define C2C_PCIE_DBI2_OFFSET 0x100000
#define SUBSYSTEM_ID_SUBSYTEM_VENDOR_DI_REG 0x2c
enum pcie_rst_status {
PCIE_RST_ASSERT = 0,
@ -47,4 +48,7 @@ enum pcie_rst_status {
PCIE_RST_STATUS_BUTT
};
#define PCIE_DATA_LINK_PCIE 0
#define PCIE_DATA_LINK_C2C 1
#endif