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ARM: tegra: device tree updates 

This branch contains all device tree updates for Tegra boards.
 
 The changes are:
 
 * Converted all DT files to use the C pre-processor, to support the use
   of named constants. This included use of defines for GPIO, IRQ, and
   clock constants.
 * Enabling new features such as:
   - SPI on Dalmore.
   - Audio on Dalmore and Beaver.
   - gpio-leds on Beaver.
   - Power-supply/batter linkage on Dalmore.
 * A minor fix to the RAM size node on Beaver.
 
 It is based on previous pull request tegra-for-3.11-deps-for-usb
 followed by a merge of tegra-for-3.11-deps-for-clk.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJRu0J2AAoJEMzrak5tbycxUEMP/iTyH5lQZ6NadMyR765G0++Y
 XzMrZDgkTu1tqbWo4NhKeYuRThoSwDReq+yfecTWLXGBHjxQ5SZ7mSi1arQLF2Gt
 rdKaOe0BibeFg55OM3S02XPG5wPz7vw/f0lXXz8nI2dq59QU59+dx1zfWDrXPAKc
 62AKTTx0Wnn5ZljNrvRgZd5wT17pj2CfSHyEV7tdJAxyW13V6aSoQFBxrJcStKrg
 N0i5WfOgmmoraNbu7zV+7iRyQc5cmJgjGNQ5lkThHQoFV4tSM64op5cCPWW/9ZC/
 USOWrGQLm3vexJnCm9Y7JmPZR4n+PgPffDYKVXHSidd74kM2t7qciHs39sEgIVRT
 DJb6AU1xxJw7Lbb8pcae+8Zy4xrcQPdbYzHj1LH08VliCNO4rC5PCwCPYB0AcA6u
 DSeU2eYALvnKxUoJga9cLeeUsDwfwjOcNvWM2YkAoSDe3h5hQhwVgq9HxTpKvMpz
 5MSsPjQ9zLSFAdU72SIRXJlnMLxezqok9j631dyk+3rLC24ARmklQbvBcpG7hc7Y
 lo9JJz4MBF3y55v71H5Ytz7dh+8cb2bPYckCI8CpxH9gx2qVFgqbK+gKucR8VbyY
 jJJe6Bvb/5BA9lQOh97HObewE9sJbh3olGZTFl3yOgML0tuUXNnpPKkqGpWYlgJS
 +us+/0GXZctU3vT2zlR0
 =4sJe
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-3.11-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt

From Stephen Warren:
ARM: tegra: device tree updates

This branch contains all device tree updates for Tegra boards.

The changes are:

* Converted all DT files to use the C pre-processor, to support the use
  of named constants. This included use of defines for GPIO, IRQ, and
  clock constants.
* Enabling new features such as:
  - SPI on Dalmore.
  - Audio on Dalmore and Beaver.
  - gpio-leds on Beaver.
  - Power-supply/batter linkage on Dalmore.
* A minor fix to the RAM size node on Beaver.

It is based on previous pull request tegra-for-3.11-deps-for-usb
followed by a merge of tegra-for-3.11-deps-for-clk.

* tag 'tegra-for-3.11-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (21 commits)
  ARM: tegra: enable audio on Beaver
  ARM: tegra: enable audio on Dalmore
  ARM: tegra: add power-supplies link between battery and charger
  ARM: tegra: add audio-related nodes to Tegra114 DT
  ARM: tegra114: convert device tree files to use CLK defines
  ARM: tegra30: convert device tree files to use CLK defines
  ARM: tegra20: convert device tree files to use CLK defines
  ARM: tegra: Add charger subnode to tps65090 node
  ARM: tegra: convert device tree files to use IRQ defines
  ARM: tegra: convert device tree files to use GPIO defines
  ARM: tegra: create a DT header defining GPIO IDs
  ARM: tegra: use #include for all device trees
  ARM: tegra: Add gpio-leds to Tegra30 Beaver
  ARM: tegra: fix memory size on Beaver
  ARM: tegra: enable spi4 on Dalmore
  ARM: tegra114: create a DT header defining CLK IDs
  ARM: tegra30: create a DT header defining CLK IDs
  ARM: tegra20: create a DT header defining CLK IDs
  ARM: tegra: update device trees for USB binding rework
  ARM: tegra: modify ULPI reset GPIO properties
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2013-06-14 18:09:41 -07:00
parent 3b2e6296ab 23037bbd96
commit 36d29fb57c
30 changed files with 1819 additions and 1182 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

252
Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
View File

@ -12,253 +12,9 @@ Required properties :
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the CAR.
The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
registers. These IDs often match those in the CAR's RST_DEVICES registers,
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
this case, those clocks are assigned IDs above 160 in order to highlight
this issue. Implementations that interpret these clock IDs as bit values
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
explicitly handle these special cases.
The balance of the clocks controlled by the CAR are assigned IDs of 160 and
above.
0 unassigned
1 unassigned
2 unassigned
3 unassigned
4 rtc
5 timer
6 uarta
7 unassigned (register bit affects uartb and vfir)
8 unassigned
9 sdmmc2
10 unassigned (register bit affects spdif_in and spdif_out)
11 i2s1
12 i2c1
13 ndflash
14 sdmmc1
15 sdmmc4
16 unassigned
17 pwm
18 i2s2
19 epp
20 unassigned (register bit affects vi and vi_sensor)
21 2d
22 usbd
23 isp
24 3d
25 unassigned
26 disp2
27 disp1
28 host1x
29 vcp
30 i2s0
31 unassigned
32 unassigned
33 unassigned
34 apbdma
35 unassigned
36 kbc
37 unassigned
38 unassigned
39 unassigned (register bit affects fuse and fuse_burn)
40 kfuse
41 sbc1
42 nor
43 unassigned
44 sbc2
45 unassigned
46 sbc3
47 i2c5
48 dsia
49 unassigned
50 mipi
51 hdmi
52 csi
53 unassigned
54 i2c2
55 uartc
56 mipi-cal
57 emc
58 usb2
59 usb3
60 msenc
61 vde
62 bsea
63 bsev
64 unassigned
65 uartd
66 unassigned
67 i2c3
68 sbc4
69 sdmmc3
70 unassigned
71 owr
72 afi
73 csite
74 unassigned
75 unassigned
76 la
77 trace
78 soc_therm
79 dtv
80 ndspeed
81 i2cslow
82 dsib
83 tsec
84 unassigned
85 unassigned
86 unassigned
87 unassigned
88 unassigned
89 xusb_host
90 unassigned
91 msenc
92 csus
93 unassigned
94 unassigned
95 unassigned (bit affects xusb_dev and xusb_dev_src)
96 unassigned
97 unassigned
98 unassigned
99 mselect
100 tsensor
101 i2s3
102 i2s4
103 i2c4
104 sbc5
105 sbc6
106 d_audio
107 apbif
108 dam0
109 dam1
110 dam2
111 hda2codec_2x
112 unassigned
113 audio0_2x
114 audio1_2x
115 audio2_2x
116 audio3_2x
117 audio4_2x
118 spdif_2x
119 actmon
120 extern1
121 extern2
122 extern3
123 unassigned
124 unassigned
125 hda
126 unassigned
127 se
128 hda2hdmi
129 unassigned
130 unassigned
131 unassigned
132 unassigned
133 unassigned
134 unassigned
135 unassigned
136 unassigned
137 unassigned
138 unassigned
139 unassigned
140 unassigned
141 unassigned
142 unassigned
143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
xusb_host_src and xusb_ss_src)
144 cilab
145 cilcd
146 cile
147 dsialp
148 dsiblp
149 unassigned
150 dds
151 unassigned
152 dp2
153 amx
154 adx
155 unassigned (bit affects dfll_ref and dfll_soc)
156 xusb_ss
192 uartb
193 vfir
194 spdif_in
195 spdif_out
196 vi
197 vi_sensor
198 fuse
199 fuse_burn
200 clk_32k
201 clk_m
202 clk_m_div2
203 clk_m_div4
204 pll_ref
205 pll_c
206 pll_c_out1
207 pll_c2
208 pll_c3
209 pll_m
210 pll_m_out1
211 pll_p
212 pll_p_out1
213 pll_p_out2
214 pll_p_out3
215 pll_p_out4
216 pll_a
217 pll_a_out0
218 pll_d
219 pll_d_out0
220 pll_d2
221 pll_d2_out0
222 pll_u
223 pll_u_480M
224 pll_u_60M
225 pll_u_48M
226 pll_u_12M
227 pll_x
228 pll_x_out0
229 pll_re_vco
230 pll_re_out
231 pll_e_out0
232 spdif_in_sync
233 i2s0_sync
234 i2s1_sync
235 i2s2_sync
236 i2s3_sync
237 i2s4_sync
238 vimclk_sync
239 audio0
240 audio1
241 audio2
242 audio3
243 audio4
244 spdif
245 clk_out_1
246 clk_out_2
247 clk_out_3
248 blink
252 xusb_host_src
253 xusb_falcon_src
254 xusb_fs_src
255 xusb_ss_src
256 xusb_dev_src
257 xusb_dev
258 xusb_hs_src
259 sclk
260 hclk
261 pclk
262 cclk_g
263 cclk_lp
264 dfll_ref
265 dfll_soc
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clock/tegra114-car.h>.
Example SoC include file:
@ -270,7 +26,7 @@ Example SoC include file:
};
usb@c5004000 {
clocks = <&tegra_car 58>; /* usb2 */
clocks = <&tegra_car TEGRA114_CLK_USB2>;
};
};

154
Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
View File

@ -12,155 +12,9 @@ Required properties :
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the CAR.
The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
registers. These IDs often match those in the CAR's RST_DEVICES registers,
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
this case, those clocks are assigned IDs above 95 in order to highlight
this issue. Implementations that interpret these clock IDs as bit values
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
explicitly handle these special cases.
The balance of the clocks controlled by the CAR are assigned IDs of 96 and
above.
0 cpu
1 unassigned
2 unassigned
3 ac97
4 rtc
5 tmr
6 uart1
7 unassigned (register bit affects uart2 and vfir)
8 gpio
9 sdmmc2
10 unassigned (register bit affects spdif_in and spdif_out)
11 i2s1
12 i2c1
13 ndflash
14 sdmmc1
15 sdmmc4
16 twc
17 pwm
18 i2s2
19 epp
20 unassigned (register bit affects vi and vi_sensor)
21 2d
22 usbd
23 isp
24 3d
25 ide
26 disp2
27 disp1
28 host1x
29 vcp
30 unassigned
31 cache2
32 mem
33 ahbdma
34 apbdma
35 unassigned
36 kbc
37 stat_mon
38 pmc
39 fuse
40 kfuse
41 sbc1
42 snor
43 spi1
44 sbc2
45 xio
46 sbc3
47 dvc
48 dsi
49 unassigned (register bit affects tvo and cve)
50 mipi
51 hdmi
52 csi
53 tvdac
54 i2c2
55 uart3
56 unassigned
57 emc
58 usb2
59 usb3
60 mpe
61 vde
62 bsea
63 bsev
64 speedo
65 uart4
66 uart5
67 i2c3
68 sbc4
69 sdmmc3
70 pcie
71 owr
72 afi
73 csite
74 unassigned
75 avpucq
76 la
77 unassigned
78 unassigned
79 unassigned
80 unassigned
81 unassigned
82 unassigned
83 unassigned
84 irama
85 iramb
86 iramc
87 iramd
88 cram2
89 audio_2x a/k/a audio_2x_sync_clk
90 clk_d
91 unassigned
92 sus
93 cdev2
94 cdev1
95 unassigned
96 uart2
97 vfir
98 spdif_in
99 spdif_out
100 vi
101 vi_sensor
102 tvo
103 cve
104 osc
105 clk_32k a/k/a clk_s
106 clk_m
107 sclk
108 cclk
109 hclk
110 pclk
111 blink
112 pll_a
113 pll_a_out0
114 pll_c
115 pll_c_out1
116 pll_d
117 pll_d_out0
118 pll_e
119 pll_m
120 pll_m_out1
121 pll_p
122 pll_p_out1
123 pll_p_out2
124 pll_p_out3
125 pll_p_out4
126 pll_s
127 pll_u
128 pll_x
129 cop a/k/a avp
130 audio a/k/a audio_sync_clk
131 pll_ref
132 twd
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clock/tegra20-car.h>.
Example SoC include file:
@ -172,7 +26,7 @@ Example SoC include file:
};
usb@c5004000 {
clocks = <&tegra_car 58>; /* usb2 */
clocks = <&tegra_car TEGRA20_CLK_USB2>;
};
};

211
Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
View File

@ -12,212 +12,9 @@ Required properties :
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the CAR.
The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
registers. These IDs often match those in the CAR's RST_DEVICES registers,
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
this case, those clocks are assigned IDs above 160 in order to highlight
this issue. Implementations that interpret these clock IDs as bit values
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
explicitly handle these special cases.
The balance of the clocks controlled by the CAR are assigned IDs of 160 and
above.
0 cpu
1 unassigned
2 unassigned
3 unassigned
4 rtc
5 timer
6 uarta
7 unassigned (register bit affects uartb and vfir)
8 gpio
9 sdmmc2
10 unassigned (register bit affects spdif_in and spdif_out)
11 i2s1
12 i2c1
13 ndflash
14 sdmmc1
15 sdmmc4
16 unassigned
17 pwm
18 i2s2
19 epp
20 unassigned (register bit affects vi and vi_sensor)
21 2d
22 usbd
23 isp
24 3d
25 unassigned
26 disp2
27 disp1
28 host1x
29 vcp
30 i2s0
31 cop_cache
32 mc
33 ahbdma
34 apbdma
35 unassigned
36 kbc
37 statmon
38 pmc
39 unassigned (register bit affects fuse and fuse_burn)
40 kfuse
41 sbc1
42 nor
43 unassigned
44 sbc2
45 unassigned
46 sbc3
47 i2c5
48 dsia
49 unassigned (register bit affects cve and tvo)
50 mipi
51 hdmi
52 csi
53 tvdac
54 i2c2
55 uartc
56 unassigned
57 emc
58 usb2
59 usb3
60 mpe
61 vde
62 bsea
63 bsev
64 speedo
65 uartd
66 uarte
67 i2c3
68 sbc4
69 sdmmc3
70 pcie
71 owr
72 afi
73 csite
74 pciex
75 avpucq
76 la
77 unassigned
78 unassigned
79 dtv
80 ndspeed
81 i2cslow
82 dsib
83 unassigned
84 irama
85 iramb
86 iramc
87 iramd
88 cram2
89 unassigned
90 audio_2x a/k/a audio_2x_sync_clk
91 unassigned
92 csus
93 cdev2
94 cdev1
95 unassigned
96 cpu_g
97 cpu_lp
98 3d2
99 mselect
100 tsensor
101 i2s3
102 i2s4
103 i2c4
104 sbc5
105 sbc6
106 d_audio
107 apbif
108 dam0
109 dam1
110 dam2
111 hda2codec_2x
112 atomics
113 audio0_2x
114 audio1_2x
115 audio2_2x
116 audio3_2x
117 audio4_2x
118 audio5_2x
119 actmon
120 extern1
121 extern2
122 extern3
123 sata_oob
124 sata
125 hda
127 se
128 hda2hdmi
129 sata_cold
160 uartb
161 vfir
162 spdif_in
163 spdif_out
164 vi
165 vi_sensor
166 fuse
167 fuse_burn
168 cve
169 tvo
170 clk_32k
171 clk_m
172 clk_m_div2
173 clk_m_div4
174 pll_ref
175 pll_c
176 pll_c_out1
177 pll_m
178 pll_m_out1
179 pll_p
180 pll_p_out1
181 pll_p_out2
182 pll_p_out3
183 pll_p_out4
184 pll_a
185 pll_a_out0
186 pll_d
187 pll_d_out0
188 pll_d2
189 pll_d2_out0
190 pll_u
191 pll_x
192 pll_x_out0
193 pll_e
194 spdif_in_sync
195 i2s0_sync
196 i2s1_sync
197 i2s2_sync
198 i2s3_sync
199 i2s4_sync
200 vimclk
201 audio0
202 audio1
203 audio2
204 audio3
205 audio4
206 audio5
207 clk_out_1 (extern1)
208 clk_out_2 (extern2)
209 clk_out_3 (extern3)
210 sclk
211 blink
212 cclk_g
213 cclk_lp
214 twd
215 cml0
216 cml1
217 hclk
218 pclk
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clock/tegra30-car.h>.
Example SoC include file:
@ -229,7 +26,7 @@ Example SoC include file:
};
usb@c5004000 {
clocks = <&tegra_car 58>; /* usb2 */
clocks = <&tegra_car TEGRA30_CLK_USB2>;
};
};

27
Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
View File

@ -6,27 +6,10 @@ Practice : Universal Serial Bus" with the following modifications
and additions :
Required properties :
- compatible : Should be "nvidia,tegra20-ehci" for USB controllers
used in host mode.
- phy_type : Should be one of "ulpi" or "utmi".
- nvidia,vbus-gpio : If present, specifies a gpio that needs to be
activated for the bus to be powered.
- nvidia,phy : phandle of the PHY instance, the controller is connected to.
Required properties for phy_type == ulpi:
- nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
- compatible : Should be "nvidia,tegra20-ehci".
- nvidia,phy : phandle of the PHY that the controller is connected to.
- clocks : Contains a single entry which defines the USB controller's clock.
Optional properties:
- dr_mode : dual role mode. Indicates the working mode for
nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral",
or "otg". Default to "host" if not defined for backward compatibility.
host means this is a host controller
peripheral means it is device controller
otg means it can operate as either ("on the go")
- nvidia,has-legacy-mode : boolean indicates whether this controller can
operate in legacy mode (as APX 2500 / 2600). In legacy mode some
registers are accessed through the APB_MISC base address instead of
the USB controller. Since this is a legacy issue it probably does not
warrant a compatible string of its own.
- nvidia,needs-double-reset : boolean is to be set for some of the Tegra2
USB ports, which need reset twice due to hardware issues.
- nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
USB ports, which need reset twice due to hardware issues.

41
Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
View File

@ -4,14 +4,49 @@ The device node for Tegra SOC USB PHY:
Required properties :
- compatible : Should be "nvidia,tegra20-usb-phy".
- reg : Address and length of the register set for the USB PHY interface.
- phy_type : Should be one of "ulpi" or "utmi".
- reg : Defines the following set of registers, in the order listed:
- The PHY's own register set.
Always present.
- The register set of the PHY containing the UTMI pad control registers.
Present if-and-only-if phy_type == utmi.
- phy_type : Should be one of "utmi", "ulpi" or "hsic".
- clocks : Defines the clocks listed in the clock-names property.
- clock-names : The following clock names must be present:
- reg: The clock needed to access the PHY's own registers. This is the
associated EHCI controller's clock. Always present.
- pll_u: PLL_U. Always present.
- timer: The timeout clock (clk_m). Present if phy_type == utmi.
- utmi-pads: The clock needed to access the UTMI pad control registers.
Present if phy_type == utmi.
- ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
Present if phy_type == ulpi, and ULPI link mode is in use.
Required properties for phy_type == ulpi:
- nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
Required PHY timing params for utmi phy:
- nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
start of sync launches RxActive
- nvidia,elastic-limit : Variable FIFO Depth of elastic input store
- nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
before declare IDLE.
- nvidia,term-range-adj : Range adjusment on terminations
- nvidia,xcvr-setup : HS driver output control
- nvidia,xcvr-lsfslew : LS falling slew rate control.
- nvidia,xcvr-lsrslew : LS rising slew rate control.
Optional properties:
- nvidia,has-legacy-mode : boolean indicates whether this controller can
operate in legacy mode (as APX 2500 / 2600). In legacy mode some
registers are accessed through the APB_MISC base address instead of
the USB controller.
the USB controller.
- nvidia,is-wired : boolean. Indicates whether we can do certain kind of power
optimizations for the devices that are always connected. e.g. modem.
- dr_mode : dual role mode. Indicates the working mode for the PHY. Can be
"host", "peripheral", or "otg". Defaults to "host" if not defined.
host means this is a host controller
peripheral means it is device controller
otg means it can operate as either ("on the go")
Required properties for dr_mode == otg:
- vbus-supply: regulator for VBUS

71
arch/arm/boot/dts/tegra114-dalmore.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra114.dtsi"
#include "tegra114.dtsi"
/ {
model = "NVIDIA Tegra114 Dalmore evaluation board";
@ -727,6 +727,16 @@
battery-name = "battery";
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <100>;
power-supplies = <&charger>;
};
rt5640: rt5640 {
compatible = "realtek,rt5640";
reg = <0x1c>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
realtek,ldo1-en-gpios =
<&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
};
};
@ -748,7 +758,7 @@
compatible = "ti,tps65090";
reg = <0x48>;
interrupt-parent = <&gpio>;
interrupts = <72 0x04>; /* gpio PJ0 */
interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
vsys1-supply = <&vdd_ac_bat_reg>;
vsys2-supply = <&vdd_ac_bat_reg>;
@ -763,6 +773,11 @@
vsys-l1-supply = <&vdd_ac_bat_reg>;
vsys-l2-supply = <&vdd_ac_bat_reg>;
charger: charger {
compatible = "ti,tps65090-charger";
ti,enable-low-current-chrg;
};
regulators {
tps65090_dcdc1_reg: dcdc1 {
regulator-name = "vdd-sys-5v0";
@ -823,12 +838,28 @@
};
};
spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
spi-flash@0 {
compatible = "winbond,w25q32dw";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
pmc {
nvidia,invert-interrupt;
};
ahub {
i2s@70080400 {
status = "okay";
};
};
sdhci@78000400 {
cd-gpios = <&gpio 170 1>; /* gpio PV2 */
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
@ -873,7 +904,7 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
gpio = <&gpio 61 0>; /* GPIO PH5 */
gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
};
lcd_bl_en_reg: regulator@2 {
@ -883,7 +914,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 58 0>; /* GPIO PH2 */
gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
};
usb1_vbus_reg: regulator@3 {
@ -893,7 +924,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 108 0>; /* GPIO PN4 */
gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&tps65090_dcdc1_reg>;
};
@ -905,7 +936,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 86 0>; /* GPIO PK6 */
gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&tps65090_dcdc1_reg>;
};
@ -917,8 +948,32 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 81 0>; /* GPIO PK1 */
gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
vin-supply = <&tps65090_dcdc1_reg>;
};
};
sound {
compatible = "nvidia,tegra-audio-rt5640-dalmore",
"nvidia,tegra-audio-rt5640";
nvidia,model = "NVIDIA Tegra Dalmore";
nvidia,audio-routing =
"Headphones", "HPOR",
"Headphones", "HPOL",
"Speakers", "SPORP",
"Speakers", "SPORN",
"Speakers", "SPOLP",
"Speakers", "SPOLN";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&rt5640>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
<&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA114_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

2
arch/arm/boot/dts/tegra114-pluto.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra114.dtsi"
#include "tegra114.dtsi"
/ {
model = "NVIDIA Tegra114 Pluto evaluation board";

277
arch/arm/boot/dts/tegra114.dtsi
View File

@ -1,4 +1,8 @@
/include/ "skeleton.dtsi"
#include <dt-bindings/clock/tegra114-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra114";
@ -19,19 +23,20 @@
<0x50042000 0x1000>,
<0x50044000 0x2000>,
<0x50046000 0x2000>;
interrupts = <1 9 0xf04>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
timer@60005000 {
compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
interrupts = <0 0 0x04
0 1 0x04
0 41 0x04
0 42 0x04
0 121 0x04
0 122 0x04>;
clocks = <&tegra_car 5>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_TIMER>;
};
tegra_car: clock {
@ -43,39 +48,39 @@
apbdma: dma {
compatible = "nvidia,tegra114-apbdma";
reg = <0x6000a000 0x1400>;
interrupts = <0 104 0x04
0 105 0x04
0 106 0x04
0 107 0x04
0 108 0x04
0 109 0x04
0 110 0x04
0 111 0x04
0 112 0x04
0 113 0x04
0 114 0x04
0 115 0x04
0 116 0x04
0 117 0x04
0 118 0x04
0 119 0x04
0 128 0x04
0 129 0x04
0 130 0x04
0 131 0x04
0 132 0x04
0 133 0x04
0 134 0x04
0 135 0x04
0 136 0x04
0 137 0x04
0 138 0x04
0 139 0x04
0 140 0x04
0 141 0x04
0 142 0x04
0 143 0x04>;
clocks = <&tegra_car 34>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
};
ahb: ahb {
@ -86,14 +91,14 @@
gpio: gpio {
compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
interrupts = <0 32 0x04
0 33 0x04
0 34 0x04
0 35 0x04
0 55 0x04
0 87 0x04
0 89 0x04
0 125 0x04>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
@ -118,57 +123,57 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 8>;
status = "disabled";
clocks = <&tegra_car 6>;
clocks = <&tegra_car TEGRA114_CLK_UARTA>;
};
uartb: serial@70006040 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
interrupts = <0 37 0x04>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>;
status = "disabled";
clocks = <&tegra_car 192>;
clocks = <&tegra_car TEGRA114_CLK_UARTB>;
};
uartc: serial@70006200 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
interrupts = <0 46 0x04>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>;
status = "disabled";
clocks = <&tegra_car 55>;
clocks = <&tegra_car TEGRA114_CLK_UARTC>;
};
uartd: serial@70006300 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
interrupts = <0 90 0x04>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>;
status = "disabled";
clocks = <&tegra_car 65>;
clocks = <&tegra_car TEGRA114_CLK_UARTD>;
};
pwm: pwm {
compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
clocks = <&tegra_car 17>;
clocks = <&tegra_car TEGRA114_CLK_PWM>;
status = "disabled";
};
i2c@7000c000 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>;
clocks = <&tegra_car TEGRA114_CLK_I2C1>;
clock-names = "div-clk";
status = "disabled";
};
@ -176,10 +181,10 @@
i2c@7000c400 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>;
clocks = <&tegra_car TEGRA114_CLK_I2C2>;
clock-names = "div-clk";
status = "disabled";
};
@ -187,10 +192,10 @@
i2c@7000c500 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>;
clocks = <&tegra_car TEGRA114_CLK_I2C3>;
clock-names = "div-clk";
status = "disabled";
};
@ -198,10 +203,10 @@
i2c@7000c700 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c700 0x100>;
interrupts = <0 120 0x04>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 103>;
clocks = <&tegra_car TEGRA114_CLK_I2C4>;
clock-names = "div-clk";
status = "disabled";
};
@ -209,10 +214,10 @@
i2c@7000d000 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000d000 0x100>;
interrupts = <0 53 0x04>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>;
clocks = <&tegra_car TEGRA114_CLK_I2C5>;
clock-names = "div-clk";
status = "disabled";
};
@ -220,11 +225,11 @@
spi@7000d400 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d400 0x200>;
interrupts = <0 59 0x04>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 41>;
clocks = <&tegra_car TEGRA114_CLK_SBC1>;
clock-names = "spi";
status = "disabled";
};
@ -232,11 +237,11 @@
spi@7000d600 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 44>;
clocks = <&tegra_car TEGRA114_CLK_SBC2>;
clock-names = "spi";
status = "disabled";
};
@ -244,11 +249,11 @@
spi@7000d800 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 46>;
clocks = <&tegra_car TEGRA114_CLK_SBC3>;
clock-names = "spi";
status = "disabled";
};
@ -256,11 +261,11 @@
spi@7000da00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000da00 0x200>;
interrupts = <0 93 0x04>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 68>;
clocks = <&tegra_car TEGRA114_CLK_SBC4>;
clock-names = "spi";
status = "disabled";
};
@ -268,11 +273,11 @@
spi@7000dc00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000dc00 0x200>;
interrupts = <0 94 0x04>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 27>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 104>;
clocks = <&tegra_car TEGRA114_CLK_SBC5>;
clock-names = "spi";
status = "disabled";
};
@ -280,11 +285,11 @@
spi@7000de00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000de00 0x200>;
interrupts = <0 79 0x04>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 28>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 105>;
clocks = <&tegra_car TEGRA114_CLK_SBC6>;
clock-names = "spi";
status = "disabled";
};
@ -292,22 +297,22 @@
rtc {
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <0 2 0x04>;
clocks = <&tegra_car 4>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_RTC>;
};
kbc {
compatible = "nvidia,tegra114-kbc";
reg = <0x7000e200 0x100>;
interrupts = <0 85 0x04>;
clocks = <&tegra_car 36>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_KBC>;
status = "disabled";
};
pmc {
compatible = "nvidia,tegra114-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car 261>, <&clk32k_in>;
clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
};
@ -322,35 +327,106 @@
nvidia,ahb = <&ahb>;
};
ahub {
compatible = "nvidia,tegra114-ahub";
reg = <0x70080000 0x200>,
<0x70080200 0x100>,
<0x70081000 0x200>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
<&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
<&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
<&apbdma 29>;
clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
<&tegra_car TEGRA114_CLK_APBIF>,
<&tegra_car TEGRA114_CLK_I2S0>,
<&tegra_car TEGRA114_CLK_I2S1>,
<&tegra_car TEGRA114_CLK_I2S2>,
<&tegra_car TEGRA114_CLK_I2S3>,
<&tegra_car TEGRA114_CLK_I2S4>,
<&tegra_car TEGRA114_CLK_DAM0>,
<&tegra_car TEGRA114_CLK_DAM1>,
<&tegra_car TEGRA114_CLK_DAM2>,
<&tegra_car TEGRA114_CLK_SPDIF_IN>,
<&tegra_car TEGRA114_CLK_AMX>,
<&tegra_car TEGRA114_CLK_ADX>;
clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
"i2s3", "i2s4", "dam0", "dam1", "dam2",
"spdif_in", "amx", "adx";
ranges;
#address-cells = <1>;
#size-cells = <1>;
tegra_i2s0: i2s@70080300 {
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
reg = <0x70080300 0x100>;
nvidia,ahub-cif-ids = <4 4>;
clocks = <&tegra_car TEGRA114_CLK_I2S0>;
status = "disabled";
};
tegra_i2s1: i2s@70080400 {
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
reg = <0x70080400 0x100>;
nvidia,ahub-cif-ids = <5 5>;
clocks = <&tegra_car TEGRA114_CLK_I2S1>;
status = "disabled";
};
tegra_i2s2: i2s@70080500 {
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
reg = <0x70080500 0x100>;
nvidia,ahub-cif-ids = <6 6>;
clocks = <&tegra_car TEGRA114_CLK_I2S2>;
status = "disabled";
};
tegra_i2s3: i2s@70080600 {
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
reg = <0x70080600 0x100>;
nvidia,ahub-cif-ids = <7 7>;
clocks = <&tegra_car TEGRA114_CLK_I2S3>;
status = "disabled";
};
tegra_i2s4: i2s@70080700 {
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
reg = <0x70080700 0x100>;
nvidia,ahub-cif-ids = <8 8>;
clocks = <&tegra_car TEGRA114_CLK_I2S4>;
status = "disabled";
};
};
sdhci@78000000 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000000 0x200>;
interrupts = <0 14 0x04>;
clocks = <&tegra_car 14>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
status = "disable";
};
sdhci@78000200 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000200 0x200>;
interrupts = <0 15 0x04>;
clocks = <&tegra_car 9>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
status = "disable";
};
sdhci@78000400 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000400 0x200>;
interrupts = <0 19 0x04>;
clocks = <&tegra_car 69>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
status = "disable";
};
sdhci@78000600 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000600 0x200>;
interrupts = <0 31 0x04>;
clocks = <&tegra_car 15>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
status = "disable";
};
@ -385,9 +461,14 @@
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
interrupts =
<GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};

29
arch/arm/boot/dts/tegra20-colibri-512.dtsi
View File

@ -1,4 +1,4 @@
/include/ "tegra20.dtsi"
#include "tegra20.dtsi"
/ {
model = "Toradex Colibri T20 512MB";
@ -14,7 +14,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&i2c_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
GPIO_ACTIVE_HIGH>;
};
};
@ -217,7 +218,7 @@
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
interrupts = <0 86 0x4>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
@ -443,17 +444,25 @@
ac97: ac97 {
status = "okay";
nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
GPIO_ACTIVE_HIGH>;
nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
GPIO_ACTIVE_HIGH>;
};
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
sdhci@c8000600 {
cd-gpios = <&gpio 23 1>; /* gpio PC7 */
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
};
clocks {
@ -483,7 +492,9 @@
nvidia,ac97-controller = <&ac97>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
@ -510,7 +521,7 @@
enable-active-high;
regulator-boot-on;
regulator-always-on;
gpio = <&gpio 217 0>;
gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
};
};
};

65
arch/arm/boot/dts/tegra20-harmony.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra20.dtsi"
#include "tegra20.dtsi"
/ {
model = "NVIDIA Tegra20 Harmony evaluation board";
@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
GPIO_ACTIVE_HIGH>;
};
};
@ -262,7 +263,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <187 0x04>;
interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -290,7 +291,7 @@
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
interrupts = <0 86 0x4>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
@ -428,32 +429,43 @@
status = "okay";
};
usb-phy@c5000000 {
status = "okay";
};
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
usb@c5008000 {
status = "okay";
};
usb-phy@c5004400 {
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
usb-phy@c5008000 {
status = "okay";
};
sdhci@c8000200 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 155 0>; /* gpio PT3 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@c8000600 {
status = "okay";
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};
@ -475,7 +487,7 @@
power {
label = "Power";
gpios = <&gpio 170 1>; /* gpio PV2, active low */
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
@ -618,7 +630,7 @@
regulator-name = "vdd_1v5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&pmic 0 0>;
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
regulator@2 {
@ -627,7 +639,7 @@
regulator-name = "vdd_1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
gpio = <&pmic 1 0>;
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@ -637,7 +649,7 @@
regulator-name = "vdd_1v05";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
gpio = <&pmic 2 0>;
gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
/* Hack until board-harmony-pcie.c is removed */
status = "disabled";
@ -649,7 +661,7 @@
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio 22 0>; /* gpio PC6 */
gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@ -659,7 +671,7 @@
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio 176 0>; /* gpio PW0 */
gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
@ -682,12 +694,17 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
GPIO_ACTIVE_HIGH>;
nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
GPIO_ACTIVE_HIGH>;
nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
GPIO_ACTIVE_HIGH>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

13
arch/arm/boot/dts/tegra20-iris-512.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra20-colibri-512.dtsi"
#include "tegra20-colibri-512.dtsi"
/ {
model = "Toradex Colibri T20 512MB on Iris";
@ -38,13 +38,20 @@
usb@c5000000 {
status = "okay";
dr_mode = "otg";
};
usb-phy@c5000000 {
status = "okay";
};
usb@c5008000 {
status = "okay";
};
usb-phy@c5008000 {
status = "okay";
};
serial@70006000 {
status = "okay";
};
@ -73,7 +80,7 @@
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
gpio = <&gpio 178 0>;
gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
};
vcc_sd_reg: regulator@1 {

12
arch/arm/boot/dts/tegra20-medcom-wide.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra20-tamonten.dtsi"
#include "tegra20-tamonten.dtsi"
/ {
model = "Avionic Design Medcom-Wide board";
@ -15,7 +15,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <187 0x04>;
interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -56,10 +56,12 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

48
arch/arm/boot/dts/tegra20-paz00.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra20.dtsi"
#include "tegra20.dtsi"
/ {
model = "Toshiba AC100 / Dynabook AZ";
@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
GPIO_ACTIVE_HIGH>;
};
};
@ -270,13 +271,14 @@
nvec {
compatible = "nvidia,nvec";
reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <80000>;
request-gpios = <&gpio 170 0>; /* gpio PV2 */
request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
slave-addr = <138>;
clocks = <&tegra_car 67>, <&tegra_car 124>;
clocks = <&tegra_car TEGRA20_CLK_I2C3>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
};
@ -287,7 +289,7 @@
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
interrupts = <0 86 0x4>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
@ -427,24 +429,35 @@
status = "okay";
};
usb-phy@c5000000 {
status = "okay";
};
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
GPIO_ACTIVE_LOW>;
};
usb@c5008000 {
status = "okay";
};
usb-phy@c5004400 {
nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
usb-phy@c5008000 {
status = "okay";
};
sdhci@c8000000 {
status = "okay";
cd-gpios = <&gpio 173 1>; /* gpio PV5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 169 0>; /* gpio PV1 */
cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -472,7 +485,7 @@
power {
label = "Power";
gpios = <&gpio 79 1>; /* gpio PJ7, active low */
gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
@ -483,7 +496,7 @@
wifi {
label = "wifi-led";
gpios = <&gpio 24 0>; /* gpio PD0 */
gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
linux,default-trigger = "rfkill0";
};
};
@ -520,9 +533,12 @@
nvidia,audio-codec = <&alc5632>;
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
GPIO_ACTIVE_HIGH>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

12
arch/arm/boot/dts/tegra20-plutux.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra20-tamonten.dtsi"
#include "tegra20-tamonten.dtsi"
/ {
model = "Avionic Design Plutux board";
@ -17,7 +17,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <187 0x04>;
interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -50,10 +50,12 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

69
arch/arm/boot/dts/tegra20-seaboard.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra20.dtsi"
#include "tegra20.dtsi"
/ {
model = "NVIDIA Seaboard";
@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
GPIO_ACTIVE_HIGH>;
};
};
@ -313,7 +314,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <187 0x04>;
interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -328,14 +329,14 @@
compatible = "isil,isl29018";
reg = <0x44>;
interrupt-parent = <&gpio>;
interrupts = <202 0x04>; /* GPIO PZ2 */
interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
};
gyrometer@68 {
compatible = "invn,mpu3050";
reg = <0x68>;
interrupt-parent = <&gpio>;
interrupts = <204 0x04>; /* gpio PZ4 */
interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
};
};
@ -388,7 +389,7 @@
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
interrupts = <0 86 0x4>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
@ -511,7 +512,7 @@
compatible = "ak,ak8975";
reg = <0xc>;
interrupt-parent = <&gpio>;
interrupts = <109 0x04>; /* gpio PN5 */
interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
};
};
@ -565,35 +566,48 @@
usb@c5000000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
dr_mode = "otg";
};
usb-phy@c5000000 {
status = "okay";
vbus-supply = <&vbus_reg>;
dr_mode = "otg";
};
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
usb@c5008000 {
status = "okay";
};
usb-phy@c5004400 {
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
usb-phy@c5008000 {
status = "okay";
};
sdhci@c8000000 {
status = "okay";
power-gpios = <&gpio 86 0>; /* gpio PK6 */
power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};
sdhci@c8000400 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -621,14 +635,14 @@
power {
label = "Power";
gpios = <&gpio 170 1>; /* gpio PV2, active low */
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
lid {
label = "Lid";
gpios = <&gpio 23 0>; /* gpio PC7 */
gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
linux,input-type = <5>; /* EV_SW */
linux,code = <0>; /* SW_LID */
debounce-interval = <1>;
@ -795,7 +809,7 @@
regulator-name = "vdd_1v5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&pmic 0 0>;
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
regulator@2 {
@ -804,9 +818,18 @@
regulator-name = "vdd_1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
gpio = <&pmic 1 0>;
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vbus_reg: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "vdd_vbus_wup1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio 24 0>; /* PD0 */
};
};
sound {
@ -827,10 +850,12 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

15
arch/arm/boot/dts/tegra20-tamonten.dtsi
View File

@ -1,4 +1,4 @@
/include/ "tegra20.dtsi"
#include "tegra20.dtsi"
/ {
model = "Avionic Design Tamonten SOM";
@ -14,7 +14,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
GPIO_ACTIVE_HIGH>;
};
};
@ -321,7 +322,7 @@
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
interrupts = <0 86 0x4>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
@ -470,9 +471,13 @@
status = "okay";
};
usb-phy@c5008000 {
status = "okay";
};
sdhci@c8000600 {
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
status = "okay";
};

13
arch/arm/boot/dts/tegra20-tec.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra20-tamonten.dtsi"
#include "tegra20-tamonten.dtsi"
/ {
model = "Avionic Design Tamonten Evaluation Carrier";
@ -17,7 +17,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <187 0x04>;
interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -50,10 +50,13 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
GPIO_ACTIVE_HIGH>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

46
arch/arm/boot/dts/tegra20-trimslice.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra20.dtsi"
#include "tegra20.dtsi"
/ {
model = "Compulab TrimSlice board";
@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
GPIO_ACTIVE_HIGH>;
};
};
@ -311,20 +312,32 @@
usb@c5000000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
};
usb-phy@c5000000 {
status = "okay";
vbus-supply = <&vbus_reg>;
};
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
GPIO_ACTIVE_LOW>;
};
usb@c5008000 {
status = "okay";
};
usb-phy@c5004400 {
nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
usb-phy@c5008000 {
status = "okay";
};
sdhci@c8000000 {
@ -334,8 +347,8 @@
sdhci@c8000600 {
status = "okay";
cd-gpios = <&gpio 121 1>; /* gpio PP1 */
wp-gpios = <&gpio 122 0>; /* gpio PP2 */
cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -357,7 +370,7 @@
power {
label = "Power";
gpios = <&gpio 190 1>; /* gpio PX6, active low */
gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
@ -365,7 +378,7 @@
poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio 191 1>; /* gpio PX7, active low */
gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
};
regulators {
@ -390,6 +403,15 @@
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vbus_reg: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio 170 0>; /* PV2 */
};
};
sound {
@ -397,7 +419,9 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&codec>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

60
arch/arm/boot/dts/tegra20-ventana.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra20.dtsi"
#include "tegra20.dtsi"
/ {
model = "NVIDIA Tegra20 Ventana evaluation board";
@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
GPIO_ACTIVE_HIGH>;
};
};
@ -310,7 +311,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <187 0x04>;
interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -325,7 +326,7 @@
compatible = "isil,isl29018";
reg = <0x44>;
interrupt-parent = <&gpio>;
interrupts = <202 0x04>; /*gpio PZ2 */
interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
};
};
@ -371,7 +372,7 @@
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
interrupts = <0 86 0x4>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
@ -505,31 +506,42 @@
status = "okay";
};
usb-phy@c5000000 {
status = "okay";
};
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
usb-phy@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_LOW>;
};
usb@c5008000 {
status = "okay";
};
usb-phy@c5004400 {
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
usb-phy@c5008000 {
status = "okay";
};
sdhci@c8000000 {
status = "okay";
power-gpios = <&gpio 86 0>; /* gpio PK6 */
power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};
sdhci@c8000400 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -557,7 +569,7 @@
power {
label = "Power";
gpios = <&gpio 170 1>; /* gpio PV2, active low */
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
@ -583,7 +595,7 @@
regulator-name = "vdd_1v5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&pmic 0 0>;
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
regulator@2 {
@ -592,7 +604,7 @@
regulator-name = "vdd_1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
gpio = <&pmic 1 0>;
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@ -602,7 +614,7 @@
regulator-name = "vdd_pnl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio 22 0>; /* gpio PC6 */
gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@ -612,7 +624,7 @@
regulator-name = "vdd_bl";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio 176 0>; /* gpio PW0 */
gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
@ -635,12 +647,16 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
GPIO_ACTIVE_HIGH>;
nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
GPIO_ACTIVE_HIGH>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

47
arch/arm/boot/dts/tegra20-whistler.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra20.dtsi"
#include "tegra20.dtsi"
/ {
model = "NVIDIA Tegra20 Whistler evaluation board";
@ -18,7 +18,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
GPIO_ACTIVE_HIGH>;
};
};
@ -281,7 +282,7 @@
max8907@3c {
compatible = "maxim,max8907";
reg = <0x3c>;
interrupts = <0 86 0x4>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
maxim,system-power-controller;
@ -508,18 +509,28 @@
usb@c5000000 {
status = "okay";
nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
nvidia,vbus-gpio = <&tca6416 0 GPIO_ACTIVE_HIGH>;
};
usb-phy@c5000000 {
status = "okay";
vbus-supply = <&vbus1_reg>;
};
usb@c5008000 {
status = "okay";
nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
nvidia,vbus-gpio = <&tca6416 1 GPIO_ACTIVE_HIGH>;
};
usb-phy@c5008000 {
status = "okay";
vbus-supply = <&vbus3_reg>;
};
sdhci@c8000400 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 173 0>; /* gpio PV5 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};
@ -568,6 +579,24 @@
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
vbus1_reg: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "vbus1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
};
vbus3_reg: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "vbus3";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
};
};
sound {
@ -584,7 +613,9 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&codec>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

285
arch/arm/boot/dts/tegra20.dtsi
View File

@ -1,4 +1,8 @@
/include/ "skeleton.dtsi"
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra20";
@ -15,9 +19,9 @@
host1x {
compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
interrupts = <0 65 0x04 /* mpcore syncpt */
0 67 0x04>; /* mpcore general */
clocks = <&tegra_car 28>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
#address-cells = <1>;
#size-cells = <1>;
@ -27,49 +31,50 @@
mpe {
compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <0 68 0x04>;
clocks = <&tegra_car 60>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_MPE>;
};
vi {
compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>;
interrupts = <0 69 0x04>;
clocks = <&tegra_car 100>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_VI>;
};
epp {
compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <0 70 0x04>;
clocks = <&tegra_car 19>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_EPP>;
};
isp {
compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>;
interrupts = <0 71 0x04>;
clocks = <&tegra_car 23>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_ISP>;
};
gr2d {
compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <0 72 0x04>;
clocks = <&tegra_car 21>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
};
gr3d {
compatible = "nvidia,tegra20-gr3d";
reg = <0x54180000 0x00040000>;
clocks = <&tegra_car 24>;
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
};
dc@54200000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
interrupts = <0 73 0x04>;
clocks = <&tegra_car 27>, <&tegra_car 121>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_DISP1>,
<&tegra_car TEGRA20_CLK_PLL_P>;
clock-names = "disp1", "parent";
rgb {
@ -80,8 +85,9 @@
dc@54240000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54240000 0x00040000>;
interrupts = <0 74 0x04>;
clocks = <&tegra_car 26>, <&tegra_car 121>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_DISP2>,
<&tegra_car TEGRA20_CLK_PLL_P>;
clock-names = "disp2", "parent";
rgb {
@ -92,8 +98,9 @@
hdmi {
compatible = "nvidia,tegra20-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <0 75 0x04>;
clocks = <&tegra_car 51>, <&tegra_car 117>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_HDMI>,
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
clock-names = "hdmi", "parent";
status = "disabled";
};
@ -101,15 +108,15 @@
tvo {
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <0 76 0x04>;
clocks = <&tegra_car 102>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_TVO>;
status = "disabled";
};
dsi {
compatible = "nvidia,tegra20-dsi";
reg = <0x54300000 0x00040000>;
clocks = <&tegra_car 48>;
clocks = <&tegra_car TEGRA20_CLK_DSI>;
status = "disabled";
};
};
@ -117,8 +124,9 @@
timer@50004600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>;
interrupts = <1 13 0x304>;
clocks = <&tegra_car 132>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&tegra_car TEGRA20_CLK_TWD>;
};
intc: interrupt-controller {
@ -141,11 +149,11 @@
timer@60005000 {
compatible = "nvidia,tegra20-timer";
reg = <0x60005000 0x60>;
interrupts = <0 0 0x04
0 1 0x04
0 41 0x04
0 42 0x04>;
clocks = <&tegra_car 5>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_TIMER>;
};
tegra_car: clock {
@ -157,23 +165,23 @@
apbdma: dma {
compatible = "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1200>;
interrupts = <0 104 0x04
0 105 0x04
0 106 0x04
0 107 0x04
0 108 0x04
0 109 0x04
0 110 0x04
0 111 0x04
0 112 0x04
0 113 0x04
0 114 0x04
0 115 0x04
0 116 0x04
0 117 0x04
0 118 0x04
0 119 0x04>;
clocks = <&tegra_car 34>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
};
ahb {
@ -184,13 +192,13 @@
gpio: gpio {
compatible = "nvidia,tegra20-gpio";
reg = <0x6000d000 0x1000>;
interrupts = <0 32 0x04
0 33 0x04
0 34 0x04
0 35 0x04
0 55 0x04
0 87 0x04
0 89 0x04>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
@ -213,27 +221,27 @@
tegra_ac97: ac97 {
compatible = "nvidia,tegra20-ac97";
reg = <0x70002000 0x200>;
interrupts = <0 81 0x04>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 12>;
clocks = <&tegra_car 3>;
clocks = <&tegra_car TEGRA20_CLK_AC97>;
status = "disabled";
};
tegra_i2s1: i2s@70002800 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002800 0x200>;
interrupts = <0 13 0x04>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 2>;
clocks = <&tegra_car 11>;
clocks = <&tegra_car TEGRA20_CLK_I2S1>;
status = "disabled";
};
tegra_i2s2: i2s@70002a00 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002a00 0x200>;
interrupts = <0 3 0x04>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 1>;
clocks = <&tegra_car 18>;
clocks = <&tegra_car TEGRA20_CLK_I2S2>;
status = "disabled";
};
@ -248,9 +256,9 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>;
clocks = <&tegra_car TEGRA20_CLK_UARTA>;
status = "disabled";
};
@ -258,9 +266,9 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
interrupts = <0 37 0x04>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 96>;
clocks = <&tegra_car TEGRA20_CLK_UARTB>;
status = "disabled";
};
@ -268,9 +276,9 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
interrupts = <0 46 0x04>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>;
clocks = <&tegra_car TEGRA20_CLK_UARTC>;
status = "disabled";
};
@ -278,9 +286,9 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
interrupts = <0 90 0x04>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>;
clocks = <&tegra_car TEGRA20_CLK_UARTD>;
status = "disabled";
};
@ -288,9 +296,9 @@
compatible = "nvidia,tegra20-uart";
reg = <0x70006400 0x100>;
reg-shift = <2>;
interrupts = <0 91 0x04>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>;
clocks = <&tegra_car TEGRA20_CLK_UARTE>;
status = "disabled";
};
@ -298,24 +306,25 @@
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
clocks = <&tegra_car 17>;
clocks = <&tegra_car TEGRA20_CLK_PWM>;
status = "disabled";
};
rtc {
compatible = "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <0 2 0x04>;
clocks = <&tegra_car 4>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_RTC>;
};
i2c@7000c000 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>, <&tegra_car 124>;
clocks = <&tegra_car TEGRA20_CLK_I2C1>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@ -323,21 +332,22 @@
spi@7000c380 {
compatible = "nvidia,tegra20-sflash";
reg = <0x7000c380 0x80>;
interrupts = <0 39 0x04>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 11>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 43>;
clocks = <&tegra_car TEGRA20_CLK_SPI>;
status = "disabled";
};
i2c@7000c400 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>, <&tegra_car 124>;
clocks = <&tegra_car TEGRA20_CLK_I2C2>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@ -345,10 +355,11 @@
i2c@7000c500 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>, <&tegra_car 124>;
clocks = <&tegra_car TEGRA20_CLK_I2C3>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@ -356,10 +367,11 @@
i2c@7000d000 {
compatible = "nvidia,tegra20-i2c-dvc";
reg = <0x7000d000 0x200>;
interrupts = <0 53 0x04>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>, <&tegra_car 124>;
clocks = <&tegra_car TEGRA20_CLK_DVC>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@ -367,59 +379,59 @@
spi@7000d400 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d400 0x200>;
interrupts = <0 59 0x04>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 41>;
clocks = <&tegra_car TEGRA20_CLK_SBC1>;
status = "disabled";
};
spi@7000d600 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 44>;
clocks = <&tegra_car TEGRA20_CLK_SBC2>;
status = "disabled";
};
spi@7000d800 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 46>;
clocks = <&tegra_car TEGRA20_CLK_SBC3>;
status = "disabled";
};
spi@7000da00 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000da00 0x200>;
interrupts = <0 93 0x04>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 68>;
clocks = <&tegra_car TEGRA20_CLK_SBC4>;
status = "disabled";
};
kbc {
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
interrupts = <0 85 0x04>;
clocks = <&tegra_car 36>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_KBC>;
status = "disabled";
};
pmc {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car 110>, <&clk32k_in>;
clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
};
@ -427,7 +439,7 @@
compatible = "nvidia,tegra20-mc";
reg = <0x7000f000 0x024
0x7000f03c 0x3c4>;
interrupts = <0 77 0x04>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
iommu {
@ -446,89 +458,114 @@
usb@c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>;
interrupts = <0 20 0x04>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
nvidia,has-legacy-mode;
clocks = <&tegra_car 22>;
clocks = <&tegra_car TEGRA20_CLK_USBD>;
nvidia,needs-double-reset;
nvidia,phy = <&phy1>;
status = "disabled";
};
phy1: usb-phy@c5000400 {
phy1: usb-phy@c5000000 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5000400 0x3c00>;
reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA20_CLK_USBD>,
<&tegra_car TEGRA20_CLK_PLL_U>,
<&tegra_car TEGRA20_CLK_CLK_M>,
<&tegra_car TEGRA20_CLK_USBD>;
clock-names = "reg", "pll_u", "timer", "utmi-pads";
nvidia,has-legacy-mode;
clocks = <&tegra_car 22>, <&tegra_car 127>;
clock-names = "phy", "pll_u";
hssync_start_delay = <9>;
idle_wait_delay = <17>;
elastic_limit = <16>;
term_range_adj = <6>;
xcvr_setup = <9>;
xcvr_lsfslew = <1>;
xcvr_lsrslew = <1>;
status = "disabled";
};
usb@c5004000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5004000 0x4000>;
interrupts = <0 21 0x04>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "ulpi";
clocks = <&tegra_car 58>;
clocks = <&tegra_car TEGRA20_CLK_USB2>;
nvidia,phy = <&phy2>;
status = "disabled";
};
phy2: usb-phy@c5004400 {
phy2: usb-phy@c5004000 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5004400 0x3c00>;
reg = <0xc5004000 0x4000>;
phy_type = "ulpi";
clocks = <&tegra_car 93>, <&tegra_car 127>;
clock-names = "phy", "pll_u";
clocks = <&tegra_car TEGRA20_CLK_USB2>,
<&tegra_car TEGRA20_CLK_PLL_U>,
<&tegra_car TEGRA20_CLK_CDEV2>;
clock-names = "reg", "pll_u", "ulpi-link";
status = "disabled";
};
usb@c5008000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5008000 0x4000>;
interrupts = <0 97 0x04>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car 59>;
clocks = <&tegra_car TEGRA20_CLK_USB3>;
nvidia,phy = <&phy3>;
status = "disabled";
};
phy3: usb-phy@c5008400 {
phy3: usb-phy@c5008000 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5008400 0x3c00>;
reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car 22>, <&tegra_car 127>;
clock-names = "phy", "pll_u";
clocks = <&tegra_car TEGRA20_CLK_USB3>,
<&tegra_car TEGRA20_CLK_PLL_U>,
<&tegra_car TEGRA20_CLK_CLK_M>,
<&tegra_car TEGRA20_CLK_USBD>;
clock-names = "reg", "pll_u", "timer", "utmi-pads";
hssync_start_delay = <9>;
idle_wait_delay = <17>;
elastic_limit = <16>;
term_range_adj = <6>;
xcvr_setup = <9>;
xcvr_lsfslew = <2>;
xcvr_lsrslew = <2>;
status = "disabled";
};
sdhci@c8000000 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>;
interrupts = <0 14 0x04>;
clocks = <&tegra_car 14>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
status = "disabled";
};
sdhci@c8000200 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000200 0x200>;
interrupts = <0 15 0x04>;
clocks = <&tegra_car 9>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
status = "disabled";
};
sdhci@c8000400 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000400 0x200>;
interrupts = <0 19 0x04>;
clocks = <&tegra_car 69>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
status = "disabled";
};
sdhci@c8000600 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000600 0x200>;
interrupts = <0 31 0x04>;
clocks = <&tegra_car 15>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
status = "disabled";
};
@ -551,7 +588,7 @@
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 56 0x04
0 57 0x04>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
};

68
arch/arm/boot/dts/tegra30-beaver.dts
View File

@ -1,13 +1,13 @@
/dts-v1/;
/include/ "tegra30.dtsi"
#include "tegra30.dtsi"
/ {
model = "NVIDIA Tegra30 Beaver evaluation board";
compatible = "nvidia,beaver", "nvidia,tegra30";
memory {
reg = <0x80000000 0x80000000>;
reg = <0x80000000 0x7ff00000>;
};
pinmux {
@ -116,6 +116,15 @@
status = "okay";
clock-frequency = <100000>;
rt5640: rt5640 {
compatible = "realtek,rt5640";
reg = <0x1c>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
realtek,ldo1-en-gpios =
<&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
};
tps62361 {
compatible = "ti,tps62361";
reg = <0x60>;
@ -133,7 +142,7 @@
compatible = "ti,tps65911";
reg = <0x2d>;
interrupts = <0 86 0x4>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
@ -264,9 +273,9 @@
sdhci@78000000 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
power-gpios = <&gpio 31 0>; /* gpio PD7 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -312,7 +321,7 @@
regulator-boot-on;
regulator-always-on;
enable-active-high;
gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
ddr_reg: regulator@2 {
@ -324,7 +333,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
vin-supply = <&vdd_5v_in_reg>;
};
@ -337,7 +346,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio 30 0>; /* gpio PD6 */
gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
vin-supply = <&vdd_5v_in_reg>;
};
@ -348,7 +357,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 68 0>; /* GPIO PI4 */
gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v_in_reg>;
};
@ -360,7 +369,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 63 0>; /* GPIO PH7 */
gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v_in_reg>;
};
@ -374,7 +383,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vdd_5v_in_reg>;
};
@ -387,8 +396,41 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio 95 0>; /* gpio PL7 */
gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
};
gpio-leds {
compatible = "gpio-leds";
gpled1 {
label = "LED1"; /* CR5A1 (blue) */
gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
};
gpled2 {
label = "LED2"; /* CR4A2 (green) */
gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
};
};
sound {
compatible = "nvidia,tegra-audio-rt5640-beaver",
"nvidia,tegra-audio-rt5640";
nvidia,model = "NVIDIA Tegra Beaver";
nvidia,audio-routing =
"Headphones", "HPOR",
"Headphones", "HPOL";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&rt5640>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA30_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

16
arch/arm/boot/dts/tegra30-cardhu-a02.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra30-cardhu.dtsi"
#include "tegra30-cardhu.dtsi"
/* This dts file support the cardhu A02 version of board */
@ -22,7 +22,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&pmic 6 0>;
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
};
sys_3v3_reg: regulator@101 {
@ -34,7 +34,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&pmic 7 0>;
gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
};
usb1_vbus_reg: regulator@102 {
@ -44,7 +44,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 68 0>; /* GPIO PI4 */
gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@ -56,7 +56,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 63 0>; /* GPIO PH7 */
gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@ -68,7 +68,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&pmic 2 0>;
gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
};
vdd_bl_reg: regulator@105 {
@ -80,13 +80,13 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio 83 0>; /* GPIO PK3 */
gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
};
};
sdhci@78000400 {
status = "okay";
power-gpios = <&gpio 28 0>; /* gpio PD4 */
power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};

18
arch/arm/boot/dts/tegra30-cardhu-a04.dts
View File

@ -1,6 +1,6 @@
/dts-v1/;
/include/ "tegra30-cardhu.dtsi"
#include "tegra30-cardhu.dtsi"
/* This dts file support the cardhu A04 and later versions of board */
@ -22,7 +22,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&pmic 7 0>;
gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
};
sys_3v3_reg: regulator@101 {
@ -34,7 +34,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&pmic 6 0>;
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
};
usb1_vbus_reg: regulator@102 {
@ -44,7 +44,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 238 0>; /* GPIO PDD6 */
gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@ -56,7 +56,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 236 0>; /* GPIO PDD4 */
gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@ -68,7 +68,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&pmic 8 0>;
gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
};
vdd_bl_reg: regulator@105 {
@ -80,7 +80,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio 234 0>; /* GPIO PDD2 */
gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
};
vdd_bl2_reg: regulator@106 {
@ -92,13 +92,13 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio 232 0>; /* GPIO PDD0 */
gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
};
};
sdhci@78000400 {
status = "okay";
power-gpios = <&gpio 27 0>; /* gpio PD3 */
power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};

47
arch/arm/boot/dts/tegra30-cardhu.dtsi
View File

@ -1,4 +1,4 @@
/include/ "tegra30.dtsi"
#include "tegra30.dtsi"
/**
* This file contains common DT entry for all fab version of Cardhu.
@ -146,7 +146,7 @@
compatible = "isil,isl29028";
reg = <0x44>;
interrupt-parent = <&gpio>;
interrupts = <88 0x04>; /*gpio PL0 */
interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
};
};
@ -163,7 +163,7 @@
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <179 0x04>; /* gpio PW3 */
interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -190,7 +190,7 @@
compatible = "ti,tps65911";
reg = <0x2d>;
interrupts = <0 86 0x4>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
@ -318,9 +318,9 @@
sdhci@78000000 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
power-gpios = <&gpio 31 0>; /* gpio PD7 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -364,7 +364,7 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
gpio = <&gpio 220 0>; /* gpio PBB4 */
gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
vin-supply = <&vio_reg>;
};
@ -377,7 +377,7 @@
regulator-boot-on;
regulator-always-on;
enable-active-high;
gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
};
emmc_3v3_reg: regulator@3 {
@ -389,7 +389,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio 25 0>; /* gpio PD1 */
gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@ -400,7 +400,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&gpio 30 0>; /* gpio PD6 */
gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
};
pex_hvdd_3v3_reg: regulator@5 {
@ -410,7 +410,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&gpio 95 0>; /* gpio PL7 */
gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@ -421,7 +421,7 @@
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
enable-active-high;
gpio = <&gpio 142 0>; /* gpio PR6 */
gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@ -432,7 +432,7 @@
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
enable-active-high;
gpio = <&gpio 143 0>; /* gpio PR7 */
gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@ -443,7 +443,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&gpio 144 0>; /* gpio PS0 */
gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@ -456,7 +456,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio 24 0>; /* gpio PD0 */
gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@ -467,7 +467,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&gpio 94 0>; /* gpio PL6 */
gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@ -480,7 +480,7 @@
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio 92 0>; /* gpio PL4 */
gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
vin-supply = <&sys_3v3_reg>;
};
@ -491,7 +491,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 152 0>; /* GPIO PT0 */
gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
vin-supply = <&vdd_5v0_reg>;
};
@ -515,10 +515,13 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
GPIO_ACTIVE_HIGH>;
clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA30_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

288
arch/arm/boot/dts/tegra30.dtsi
View File

@ -1,4 +1,8 @@
/include/ "skeleton.dtsi"
#include <dt-bindings/clock/tegra30-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra30";
@ -15,9 +19,9 @@
host1x {
compatible = "nvidia,tegra30-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
interrupts = <0 65 0x04 /* mpcore syncpt */
0 67 0x04>; /* mpcore general */
clocks = <&tegra_car 28>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
#address-cells = <1>;
#size-cells = <1>;
@ -27,36 +31,36 @@
mpe {
compatible = "nvidia,tegra30-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <0 68 0x04>;
clocks = <&tegra_car 60>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_MPE>;
};
vi {
compatible = "nvidia,tegra30-vi";
reg = <0x54080000 0x00040000>;
interrupts = <0 69 0x04>;
clocks = <&tegra_car 164>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_VI>;
};
epp {
compatible = "nvidia,tegra30-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <0 70 0x04>;
clocks = <&tegra_car 19>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_EPP>;
};
isp {
compatible = "nvidia,tegra30-isp";
reg = <0x54100000 0x00040000>;
interrupts = <0 71 0x04>;
clocks = <&tegra_car 23>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_ISP>;
};
gr2d {
compatible = "nvidia,tegra30-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <0 72 0x04>;
clocks = <&tegra_car 21>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_GR2D>;
};
gr3d {
@ -69,8 +73,9 @@
dc@54200000 {
compatible = "nvidia,tegra30-dc";
reg = <0x54200000 0x00040000>;
interrupts = <0 73 0x04>;
clocks = <&tegra_car 27>, <&tegra_car 179>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_DISP1>,
<&tegra_car TEGRA30_CLK_PLL_P>;
clock-names = "disp1", "parent";
rgb {
@ -81,8 +86,9 @@
dc@54240000 {
compatible = "nvidia,tegra30-dc";
reg = <0x54240000 0x00040000>;
interrupts = <0 74 0x04>;
clocks = <&tegra_car 26>, <&tegra_car 179>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_DISP2>,
<&tegra_car TEGRA30_CLK_PLL_P>;
clock-names = "disp2", "parent";
rgb {
@ -93,8 +99,9 @@
hdmi {
compatible = "nvidia,tegra30-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <0 75 0x04>;
clocks = <&tegra_car 51>, <&tegra_car 189>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_HDMI>,
<&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
clock-names = "hdmi", "parent";
status = "disabled";
};
@ -102,15 +109,15 @@
tvo {
compatible = "nvidia,tegra30-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <0 76 0x04>;
clocks = <&tegra_car 169>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_TVO>;
status = "disabled";
};
dsi {
compatible = "nvidia,tegra30-dsi";
reg = <0x54300000 0x00040000>;
clocks = <&tegra_car 48>;
clocks = <&tegra_car TEGRA30_CLK_DSIA>;
status = "disabled";
};
};
@ -118,8 +125,9 @@
timer@50004600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>;
interrupts = <1 13 0xf04>;
clocks = <&tegra_car 214>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&tegra_car TEGRA30_CLK_TWD>;
};
intc: interrupt-controller {
@ -142,13 +150,13 @@
timer@60005000 {
compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
interrupts = <0 0 0x04
0 1 0x04
0 41 0x04
0 42 0x04
0 121 0x04
0 122 0x04>;
clocks = <&tegra_car 5>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_TIMER>;
};
tegra_car: clock {
@ -160,39 +168,39 @@
apbdma: dma {
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1400>;
interrupts = <0 104 0x04
0 105 0x04
0 106 0x04
0 107 0x04
0 108 0x04
0 109 0x04
0 110 0x04
0 111 0x04
0 112 0x04
0 113 0x04
0 114 0x04
0 115 0x04
0 116 0x04
0 117 0x04
0 118 0x04
0 119 0x04
0 128 0x04
0 129 0x04
0 130 0x04
0 131 0x04
0 132 0x04
0 133 0x04
0 134 0x04
0 135 0x04
0 136 0x04
0 137 0x04
0 138 0x04
0 139 0x04
0 140 0x04
0 141 0x04
0 142 0x04
0 143 0x04>;
clocks = <&tegra_car 34>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
};
ahb: ahb {
@ -203,14 +211,14 @@
gpio: gpio {
compatible = "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
interrupts = <0 32 0x04
0 33 0x04
0 34 0x04
0 35 0x04
0 55 0x04
0 87 0x04
0 89 0x04
0 125 0x04>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
@ -235,9 +243,9 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>;
clocks = <&tegra_car TEGRA30_CLK_UARTA>;
status = "disabled";
};
@ -245,9 +253,9 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
interrupts = <0 37 0x04>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 160>;
clocks = <&tegra_car TEGRA30_CLK_UARTB>;
status = "disabled";
};
@ -255,9 +263,9 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
interrupts = <0 46 0x04>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>;
clocks = <&tegra_car TEGRA30_CLK_UARTC>;
status = "disabled";
};
@ -265,9 +273,9 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
interrupts = <0 90 0x04>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>;
clocks = <&tegra_car TEGRA30_CLK_UARTD>;
status = "disabled";
};
@ -275,9 +283,9 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006400 0x100>;
reg-shift = <2>;
interrupts = <0 91 0x04>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>;
clocks = <&tegra_car TEGRA30_CLK_UARTE>;
status = "disabled";
};
@ -285,24 +293,25 @@
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
clocks = <&tegra_car 17>;
clocks = <&tegra_car TEGRA30_CLK_PWM>;
status = "disabled";
};
rtc {
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <0 2 0x04>;
clocks = <&tegra_car 4>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_RTC>;
};
i2c@7000c000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>, <&tegra_car 182>;
clocks = <&tegra_car TEGRA30_CLK_I2C1>,
<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@ -310,10 +319,11 @@
i2c@7000c400 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>, <&tegra_car 182>;
clocks = <&tegra_car TEGRA30_CLK_I2C2>,
<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@ -321,10 +331,11 @@
i2c@7000c500 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>, <&tegra_car 182>;
clocks = <&tegra_car TEGRA30_CLK_I2C3>,
<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@ -332,10 +343,11 @@
i2c@7000c700 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c700 0x100>;
interrupts = <0 120 0x04>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 103>, <&tegra_car 182>;
clocks = <&tegra_car TEGRA30_CLK_I2C4>,
<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@ -343,10 +355,11 @@
i2c@7000d000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000d000 0x100>;
interrupts = <0 53 0x04>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>, <&tegra_car 182>;
clocks = <&tegra_car TEGRA30_CLK_I2C5>,
<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
@ -354,81 +367,81 @@
spi@7000d400 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d400 0x200>;
interrupts = <0 59 0x04>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 41>;
clocks = <&tegra_car TEGRA30_CLK_SBC1>;
status = "disabled";
};
spi@7000d600 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 44>;
clocks = <&tegra_car TEGRA30_CLK_SBC2>;
status = "disabled";
};
spi@7000d800 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 46>;
clocks = <&tegra_car TEGRA30_CLK_SBC3>;
status = "disabled";
};
spi@7000da00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000da00 0x200>;
interrupts = <0 93 0x04>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 68>;
clocks = <&tegra_car TEGRA30_CLK_SBC4>;
status = "disabled";
};
spi@7000dc00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000dc00 0x200>;
interrupts = <0 94 0x04>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 27>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 104>;
clocks = <&tegra_car TEGRA30_CLK_SBC5>;
status = "disabled";
};
spi@7000de00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000de00 0x200>;
interrupts = <0 79 0x04>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 28>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 105>;
clocks = <&tegra_car TEGRA30_CLK_SBC6>;
status = "disabled";
};
kbc {
compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
interrupts = <0 85 0x04>;
clocks = <&tegra_car 36>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_KBC>;
status = "disabled";
};
pmc {
compatible = "nvidia,tegra30-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car 218>, <&clk32k_in>;
clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
};
@ -438,7 +451,7 @@
0x7000f03c 0x1b4
0x7000f200 0x028
0x7000f284 0x17c>;
interrupts = <0 77 0x04>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
iommu {
@ -455,12 +468,19 @@
compatible = "nvidia,tegra30-ahub";
reg = <0x70080000 0x200
0x70080200 0x100>;
interrupts = <0 103 0x04>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 1>;
clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
<&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
<&tegra_car 110>, <&tegra_car 162>;
clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
<&tegra_car TEGRA30_CLK_APBIF>,
<&tegra_car TEGRA30_CLK_I2S0>,
<&tegra_car TEGRA30_CLK_I2S1>,
<&tegra_car TEGRA30_CLK_I2S2>,
<&tegra_car TEGRA30_CLK_I2S3>,
<&tegra_car TEGRA30_CLK_I2S4>,
<&tegra_car TEGRA30_CLK_DAM0>,
<&tegra_car TEGRA30_CLK_DAM1>,
<&tegra_car TEGRA30_CLK_DAM2>,
<&tegra_car TEGRA30_CLK_SPDIF_IN>;
clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
"i2s3", "i2s4", "dam0", "dam1", "dam2",
"spdif_in";
@ -472,7 +492,7 @@
compatible = "nvidia,tegra30-i2s";
reg = <0x70080300 0x100>;
nvidia,ahub-cif-ids = <4 4>;
clocks = <&tegra_car 30>;
clocks = <&tegra_car TEGRA30_CLK_I2S0>;
status = "disabled";
};
@ -480,7 +500,7 @@
compatible = "nvidia,tegra30-i2s";
reg = <0x70080400 0x100>;
nvidia,ahub-cif-ids = <5 5>;
clocks = <&tegra_car 11>;
clocks = <&tegra_car TEGRA30_CLK_I2S1>;
status = "disabled";
};
@ -488,7 +508,7 @@
compatible = "nvidia,tegra30-i2s";
reg = <0x70080500 0x100>;
nvidia,ahub-cif-ids = <6 6>;
clocks = <&tegra_car 18>;
clocks = <&tegra_car TEGRA30_CLK_I2S2>;
status = "disabled";
};
@ -496,7 +516,7 @@
compatible = "nvidia,tegra30-i2s";
reg = <0x70080600 0x100>;
nvidia,ahub-cif-ids = <7 7>;
clocks = <&tegra_car 101>;
clocks = <&tegra_car TEGRA30_CLK_I2S3>;
status = "disabled";
};
@ -504,7 +524,7 @@
compatible = "nvidia,tegra30-i2s";
reg = <0x70080700 0x100>;
nvidia,ahub-cif-ids = <8 8>;
clocks = <&tegra_car 102>;
clocks = <&tegra_car TEGRA30_CLK_I2S4>;
status = "disabled";
};
};
@ -512,32 +532,32 @@
sdhci@78000000 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000000 0x200>;
interrupts = <0 14 0x04>;
clocks = <&tegra_car 14>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
status = "disabled";
};
sdhci@78000200 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000200 0x200>;
interrupts = <0 15 0x04>;
clocks = <&tegra_car 9>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
status = "disabled";
};
sdhci@78000400 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000400 0x200>;
interrupts = <0 19 0x04>;
clocks = <&tegra_car 69>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
status = "disabled";
};
sdhci@78000600 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000600 0x200>;
interrupts = <0 31 0x04>;
clocks = <&tegra_car 15>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
status = "disabled";
};
@ -572,9 +592,9 @@
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 144 0x04
0 145 0x04
0 146 0x04
0 147 0x04>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
};
};

342
include/dt-bindings/clock/tegra114-car.h Normal file
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@ -0,0 +1,342 @@
/*
* This header provides constants for binding nvidia,tegra114-car.
*
* The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 160 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
/* 0 */
/* 1 */
/* 2 */
/* 3 */
#define TEGRA114_CLK_RTC 4
#define TEGRA114_CLK_TIMER 5
#define TEGRA114_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
/* 8 */
#define TEGRA114_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA114_CLK_I2S1 11
#define TEGRA114_CLK_I2C1 12
#define TEGRA114_CLK_NDFLASH 13
#define TEGRA114_CLK_SDMMC1 14
#define TEGRA114_CLK_SDMMC4 15
/* 16 */
#define TEGRA114_CLK_PWM 17
#define TEGRA114_CLK_I2S2 18
#define TEGRA114_CLK_EPP 19
/* 20 (register bit affects vi and vi_sensor) */
#define TEGRA114_CLK_GR_2D 21
#define TEGRA114_CLK_USBD 22
#define TEGRA114_CLK_ISP 23
#define TEGRA114_CLK_GR_3D 24
/* 25 */
#define TEGRA114_CLK_DISP2 26
#define TEGRA114_CLK_DISP1 27
#define TEGRA114_CLK_HOST1X 28
#define TEGRA114_CLK_VCP 29
#define TEGRA114_CLK_I2S0 30
/* 31 */
/* 32 */
/* 33 */
#define TEGRA114_CLK_APBDMA 34
/* 35 */
#define TEGRA114_CLK_KBC 36
/* 37 */
/* 38 */
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA114_CLK_KFUSE 40
#define TEGRA114_CLK_SBC1 41
#define TEGRA114_CLK_NOR 42
/* 43 */
#define TEGRA114_CLK_SBC2 44
/* 45 */
#define TEGRA114_CLK_SBC3 46
#define TEGRA114_CLK_I2C5 47
#define TEGRA114_CLK_DSIA 48
/* 49 */
#define TEGRA114_CLK_MIPI 50
#define TEGRA114_CLK_HDMI 51
#define TEGRA114_CLK_CSI 52
/* 53 */
#define TEGRA114_CLK_I2C2 54
#define TEGRA114_CLK_UARTC 55
#define TEGRA114_CLK_MIPI_CAL 56
#define TEGRA114_CLK_EMC 57
#define TEGRA114_CLK_USB2 58
#define TEGRA114_CLK_USB3 59
/* 60 */
#define TEGRA114_CLK_VDE 61
#define TEGRA114_CLK_BSEA 62
#define TEGRA114_CLK_BSEV 63
/* 64 */
#define TEGRA114_CLK_UARTD 65
/* 66 */
#define TEGRA114_CLK_I2C3 67
#define TEGRA114_CLK_SBC4 68
#define TEGRA114_CLK_SDMMC3 69
/* 70 */
#define TEGRA114_CLK_OWR 71
/* 72 */
#define TEGRA114_CLK_CSITE 73
/* 74 */
/* 75 */
#define TEGRA114_CLK_LA 76
#define TEGRA114_CLK_TRACE 77
#define TEGRA114_CLK_SOC_THERM 78
#define TEGRA114_CLK_DTV 79
#define TEGRA114_CLK_NDSPEED 80
#define TEGRA114_CLK_I2CSLOW 81
#define TEGRA114_CLK_DSIB 82
#define TEGRA114_CLK_TSEC 83
/* 84 */
/* 85 */
/* 86 */
/* 87 */
/* 88 */
#define TEGRA114_CLK_XUSB_HOST 89
/* 90 */
#define TEGRA114_CLK_MSENC 91
#define TEGRA114_CLK_CSUS 92
/* 93 */
/* 94 */
/* 95 (bit affects xusb_dev and xusb_dev_src) */
/* 96 */
/* 97 */
/* 98 */
#define TEGRA114_CLK_MSELECT 99
#define TEGRA114_CLK_TSENSOR 100
#define TEGRA114_CLK_I2S3 101
#define TEGRA114_CLK_I2S4 102
#define TEGRA114_CLK_I2C4 103
#define TEGRA114_CLK_SBC5 104
#define TEGRA114_CLK_SBC6 105
#define TEGRA114_CLK_D_AUDIO 106
#define TEGRA114_CLK_APBIF 107
#define TEGRA114_CLK_DAM0 108
#define TEGRA114_CLK_DAM1 109
#define TEGRA114_CLK_DAM2 110
#define TEGRA114_CLK_HDA2CODEC_2X 111
/* 112 */
#define TEGRA114_CLK_AUDIO0_2X 113
#define TEGRA114_CLK_AUDIO1_2X 114
#define TEGRA114_CLK_AUDIO2_2X 115
#define TEGRA114_CLK_AUDIO3_2X 116
#define TEGRA114_CLK_AUDIO4_2X 117
#define TEGRA114_CLK_SPDIF_2X 118
#define TEGRA114_CLK_ACTMON 119
#define TEGRA114_CLK_EXTERN1 120
#define TEGRA114_CLK_EXTERN2 121
#define TEGRA114_CLK_EXTERN3 122
/* 123 */
/* 124 */
#define TEGRA114_CLK_HDA 125
/* 126 */
#define TEGRA114_CLK_SE 127
#define TEGRA114_CLK_HDA2HDMI 128
/* 129 */
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
/* xusb_host_src and xusb_ss_src) */
#define TEGRA114_CLK_CILAB 144
#define TEGRA114_CLK_CILCD 145
#define TEGRA114_CLK_CILE 146
#define TEGRA114_CLK_DSIALP 147
#define TEGRA114_CLK_DSIBLP 148
/* 149 */
#define TEGRA114_CLK_DDS 150
/* 151 */
#define TEGRA114_CLK_DP2 152
#define TEGRA114_CLK_AMX 153
#define TEGRA114_CLK_ADX 154
/* 155 (bit affects dfll_ref and dfll_soc) */
#define TEGRA114_CLK_XUSB_SS 156
/* 157 */
/* 158 */
/* 159 */
/* 160 */
/* 161 */
/* 162 */
/* 163 */
/* 164 */
/* 165 */
/* 166 */
/* 167 */
/* 168 */
/* 169 */
/* 170 */
/* 171 */
/* 172 */
/* 173 */
/* 174 */
/* 175 */
/* 176 */
/* 177 */
/* 178 */
/* 179 */
/* 180 */
/* 181 */
/* 182 */
/* 183 */
/* 184 */
/* 185 */
/* 186 */
/* 187 */
/* 188 */
/* 189 */
/* 190 */
/* 191 */
#define TEGRA114_CLK_UARTB 192
#define TEGRA114_CLK_VFIR 193
#define TEGRA114_CLK_SPDIF_IN 194
#define TEGRA114_CLK_SPDIF_OUT 195
#define TEGRA114_CLK_VI 196
#define TEGRA114_CLK_VI_SENSOR 197
#define TEGRA114_CLK_FUSE 198
#define TEGRA114_CLK_FUSE_BURN 199
#define TEGRA114_CLK_CLK_32K 200
#define TEGRA114_CLK_CLK_M 201
#define TEGRA114_CLK_CLK_M_DIV2 202
#define TEGRA114_CLK_CLK_M_DIV4 203
#define TEGRA114_CLK_PLL_REF 204
#define TEGRA114_CLK_PLL_C 205
#define TEGRA114_CLK_PLL_C_OUT1 206
#define TEGRA114_CLK_PLL_C2 207
#define TEGRA114_CLK_PLL_C3 208
#define TEGRA114_CLK_PLL_M 209
#define TEGRA114_CLK_PLL_M_OUT1 210
#define TEGRA114_CLK_PLL_P 211
#define TEGRA114_CLK_PLL_P_OUT1 212
#define TEGRA114_CLK_PLL_P_OUT2 213
#define TEGRA114_CLK_PLL_P_OUT3 214
#define TEGRA114_CLK_PLL_P_OUT4 215
#define TEGRA114_CLK_PLL_A 216
#define TEGRA114_CLK_PLL_A_OUT0 217
#define TEGRA114_CLK_PLL_D 218
#define TEGRA114_CLK_PLL_D_OUT0 219
#define TEGRA114_CLK_PLL_D2 220
#define TEGRA114_CLK_PLL_D2_OUT0 221
#define TEGRA114_CLK_PLL_U 222
#define TEGRA114_CLK_PLL_U_480M 223
#define TEGRA114_CLK_PLL_U_60M 224
#define TEGRA114_CLK_PLL_U_48M 225
#define TEGRA114_CLK_PLL_U_12M 226
#define TEGRA114_CLK_PLL_X 227
#define TEGRA114_CLK_PLL_X_OUT0 228
#define TEGRA114_CLK_PLL_RE_VCO 229
#define TEGRA114_CLK_PLL_RE_OUT 230
#define TEGRA114_CLK_PLL_E_OUT0 231
#define TEGRA114_CLK_SPDIF_IN_SYNC 232
#define TEGRA114_CLK_I2S0_SYNC 233
#define TEGRA114_CLK_I2S1_SYNC 234
#define TEGRA114_CLK_I2S2_SYNC 235
#define TEGRA114_CLK_I2S3_SYNC 236
#define TEGRA114_CLK_I2S4_SYNC 237
#define TEGRA114_CLK_VIMCLK_SYNC 238
#define TEGRA114_CLK_AUDIO0 239
#define TEGRA114_CLK_AUDIO1 240
#define TEGRA114_CLK_AUDIO2 241
#define TEGRA114_CLK_AUDIO3 242
#define TEGRA114_CLK_AUDIO4 243
#define TEGRA114_CLK_SPDIF 244
#define TEGRA114_CLK_CLK_OUT_1 245
#define TEGRA114_CLK_CLK_OUT_2 246
#define TEGRA114_CLK_CLK_OUT_3 247
#define TEGRA114_CLK_BLINK 248
/* 249 */
/* 250 */
/* 251 */
#define TEGRA114_CLK_XUSB_HOST_SRC 252
#define TEGRA114_CLK_XUSB_FALCON_SRC 253
#define TEGRA114_CLK_XUSB_FS_SRC 254
#define TEGRA114_CLK_XUSB_SS_SRC 255
#define TEGRA114_CLK_XUSB_DEV_SRC 256
#define TEGRA114_CLK_XUSB_DEV 257
#define TEGRA114_CLK_XUSB_HS_SRC 258
#define TEGRA114_CLK_SCLK 259
#define TEGRA114_CLK_HCLK 260
#define TEGRA114_CLK_PCLK 261
#define TEGRA114_CLK_CCLK_G 262
#define TEGRA114_CLK_CCLK_LP 263
/* 264 */
/* 265 */
/* 266 */
/* 267 */
/* 268 */
/* 269 */
/* 270 */
/* 271 */
/* 272 */
/* 273 */
/* 274 */
/* 275 */
/* 276 */
/* 277 */
/* 278 */
/* 279 */
/* 280 */
/* 281 */
/* 282 */
/* 283 */
/* 284 */
/* 285 */
/* 286 */
/* 287 */
/* 288 */
/* 289 */
/* 290 */
/* 291 */
/* 292 */
/* 293 */
/* 294 */
/* 295 */
/* 296 */
/* 297 */
/* 298 */
/* 299 */
#define TEGRA114_CLK_AUDIO0_MUX 300
#define TEGRA114_CLK_AUDIO1_MUX 301
#define TEGRA114_CLK_AUDIO2_MUX 302
#define TEGRA114_CLK_AUDIO3_MUX 303
#define TEGRA114_CLK_AUDIO4_MUX 304
#define TEGRA114_CLK_SPDIF_MUX 305
#define TEGRA114_CLK_CLK_OUT_1_MUX 306
#define TEGRA114_CLK_CLK_OUT_2_MUX 307
#define TEGRA114_CLK_CLK_OUT_3_MUX 308
#define TEGRA114_CLK_DSIA_MUX 309
#define TEGRA114_CLK_DSIB_MUX 310
#define TEGRA114_CLK_CLK_MAX 311
#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */

158
include/dt-bindings/clock/tegra20-car.h Normal file
View File

@ -0,0 +1,158 @@
/*
* This header provides constants for binding nvidia,tegra20-car.
*
* The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 95 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 96 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
#define TEGRA20_CLK_CPU 0
/* 1 */
/* 2 */
#define TEGRA20_CLK_AC97 3
#define TEGRA20_CLK_RTC 4
#define TEGRA20_CLK_TIMER 5
#define TEGRA20_CLK_UARTA 6
/* 7 (register bit affects uart2 and vfir) */
#define TEGRA20_CLK_GPIO 8
#define TEGRA20_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA20_CLK_I2S1 11
#define TEGRA20_CLK_I2C1 12
#define TEGRA20_CLK_NDFLASH 13
#define TEGRA20_CLK_SDMMC1 14
#define TEGRA20_CLK_SDMMC4 15
#define TEGRA20_CLK_TWC 16
#define TEGRA20_CLK_PWM 17
#define TEGRA20_CLK_I2S2 18
#define TEGRA20_CLK_EPP 19
/* 20 (register bit affects vi and vi_sensor) */
#define TEGRA20_CLK_GR2D 21
#define TEGRA20_CLK_USBD 22
#define TEGRA20_CLK_ISP 23
#define TEGRA20_CLK_GR3D 24
#define TEGRA20_CLK_IDE 25
#define TEGRA20_CLK_DISP2 26
#define TEGRA20_CLK_DISP1 27
#define TEGRA20_CLK_HOST1X 28
#define TEGRA20_CLK_VCP 29
/* 30 */
#define TEGRA20_CLK_CACHE2 31
#define TEGRA20_CLK_MEM 32
#define TEGRA20_CLK_AHBDMA 33
#define TEGRA20_CLK_APBDMA 34
/* 35 */
#define TEGRA20_CLK_KBC 36
#define TEGRA20_CLK_STAT_MON 37
#define TEGRA20_CLK_PMC 38
#define TEGRA20_CLK_FUSE 39
#define TEGRA20_CLK_KFUSE 40
#define TEGRA20_CLK_SBC1 41
#define TEGRA20_CLK_NOR 42
#define TEGRA20_CLK_SPI 43
#define TEGRA20_CLK_SBC2 44
#define TEGRA20_CLK_XIO 45
#define TEGRA20_CLK_SBC3 46
#define TEGRA20_CLK_DVC 47
#define TEGRA20_CLK_DSI 48
/* 49 (register bit affects tvo and cve) */
#define TEGRA20_CLK_MIPI 50
#define TEGRA20_CLK_HDMI 51
#define TEGRA20_CLK_CSI 52
#define TEGRA20_CLK_TVDAC 53
#define TEGRA20_CLK_I2C2 54
#define TEGRA20_CLK_UARTC 55
/* 56 */
#define TEGRA20_CLK_EMC 57
#define TEGRA20_CLK_USB2 58
#define TEGRA20_CLK_USB3 59
#define TEGRA20_CLK_MPE 60
#define TEGRA20_CLK_VDE 61
#define TEGRA20_CLK_BSEA 62
#define TEGRA20_CLK_BSEV 63
#define TEGRA20_CLK_SPEEDO 64
#define TEGRA20_CLK_UARTD 65
#define TEGRA20_CLK_UARTE 66
#define TEGRA20_CLK_I2C3 67
#define TEGRA20_CLK_SBC4 68
#define TEGRA20_CLK_SDMMC3 69
#define TEGRA20_CLK_PEX 70
#define TEGRA20_CLK_OWR 71
#define TEGRA20_CLK_AFI 72
#define TEGRA20_CLK_CSITE 73
#define TEGRA20_CLK_PCIE_XCLK 74
#define TEGRA20_CLK_AVPUCQ 75
#define TEGRA20_CLK_LA 76
/* 77 */
/* 78 */
/* 79 */
/* 80 */
/* 81 */
/* 82 */
/* 83 */
#define TEGRA20_CLK_IRAMA 84
#define TEGRA20_CLK_IRAMB 85
#define TEGRA20_CLK_IRAMC 86
#define TEGRA20_CLK_IRAMD 87
#define TEGRA20_CLK_CRAM2 88
#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
#define TEGRA20_CLK_CLK_D 90
/* 91 */
#define TEGRA20_CLK_CSUS 92
#define TEGRA20_CLK_CDEV2 93
#define TEGRA20_CLK_CDEV1 94
/* 95 */
#define TEGRA20_CLK_UARTB 96
#define TEGRA20_CLK_VFIR 97
#define TEGRA20_CLK_SPDIF_IN 98
#define TEGRA20_CLK_SPDIF_OUT 99
#define TEGRA20_CLK_VI 100
#define TEGRA20_CLK_VI_SENSOR 101
#define TEGRA20_CLK_TVO 102
#define TEGRA20_CLK_CVE 103
#define TEGRA20_CLK_OSC 104
#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
#define TEGRA20_CLK_CLK_M 106
#define TEGRA20_CLK_SCLK 107
#define TEGRA20_CLK_CCLK 108
#define TEGRA20_CLK_HCLK 109
#define TEGRA20_CLK_PCLK 110
#define TEGRA20_CLK_BLINK 111
#define TEGRA20_CLK_PLL_A 112
#define TEGRA20_CLK_PLL_A_OUT0 113
#define TEGRA20_CLK_PLL_C 114
#define TEGRA20_CLK_PLL_C_OUT1 115
#define TEGRA20_CLK_PLL_D 116
#define TEGRA20_CLK_PLL_D_OUT0 117
#define TEGRA20_CLK_PLL_E 118
#define TEGRA20_CLK_PLL_M 119
#define TEGRA20_CLK_PLL_M_OUT1 120
#define TEGRA20_CLK_PLL_P 121
#define TEGRA20_CLK_PLL_P_OUT1 122
#define TEGRA20_CLK_PLL_P_OUT2 123
#define TEGRA20_CLK_PLL_P_OUT3 124
#define TEGRA20_CLK_PLL_P_OUT4 125
#define TEGRA20_CLK_PLL_S 126
#define TEGRA20_CLK_PLL_U 127
#define TEGRA20_CLK_PLL_X 128
#define TEGRA20_CLK_COP 129 /* a/k/a avp */
#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
#define TEGRA20_CLK_PLL_REF 131
#define TEGRA20_CLK_TWD 132
#define TEGRA20_CLK_CLK_MAX 133
#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */

265
include/dt-bindings/clock/tegra30-car.h Normal file
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@ -0,0 +1,265 @@
/*
* This header provides constants for binding nvidia,tegra30-car.
*
* The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 160 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
#define TEGRA30_CLK_CPU 0
/* 1 */
/* 2 */
/* 3 */
#define TEGRA30_CLK_RTC 4
#define TEGRA30_CLK_TIMER 5
#define TEGRA30_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
#define TEGRA30_CLK_GPIO 8
#define TEGRA30_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA30_CLK_I2S1 11
#define TEGRA30_CLK_I2C1 12
#define TEGRA30_CLK_NDFLASH 13
#define TEGRA30_CLK_SDMMC1 14
#define TEGRA30_CLK_SDMMC4 15
/* 16 */
#define TEGRA30_CLK_PWM 17
#define TEGRA30_CLK_I2S2 18
#define TEGRA30_CLK_EPP 19
/* 20 (register bit affects vi and vi_sensor) */
#define TEGRA30_CLK_GR2D 21
#define TEGRA30_CLK_USBD 22
#define TEGRA30_CLK_ISP 23
#define TEGRA30_CLK_GR3D 24
/* 25 */
#define TEGRA30_CLK_DISP2 26
#define TEGRA30_CLK_DISP1 27
#define TEGRA30_CLK_HOST1X 28
#define TEGRA30_CLK_VCP 29
#define TEGRA30_CLK_I2S0 30
#define TEGRA30_CLK_COP_CACHE 31
#define TEGRA30_CLK_MC 32
#define TEGRA30_CLK_AHBDMA 33
#define TEGRA30_CLK_APBDMA 34
/* 35 */
#define TEGRA30_CLK_KBC 36
#define TEGRA30_CLK_STATMON 37
#define TEGRA30_CLK_PMC 38
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA30_CLK_KFUSE 40
#define TEGRA30_CLK_SBC1 41
#define TEGRA30_CLK_NOR 42
/* 43 */
#define TEGRA30_CLK_SBC2 44
/* 45 */
#define TEGRA30_CLK_SBC3 46
#define TEGRA30_CLK_I2C5 47
#define TEGRA30_CLK_DSIA 48
/* 49 (register bit affects cve and tvo) */
#define TEGRA30_CLK_MIPI 50
#define TEGRA30_CLK_HDMI 51
#define TEGRA30_CLK_CSI 52
#define TEGRA30_CLK_TVDAC 53
#define TEGRA30_CLK_I2C2 54
#define TEGRA30_CLK_UARTC 55
/* 56 */
#define TEGRA30_CLK_EMC 57
#define TEGRA30_CLK_USB2 58
#define TEGRA30_CLK_USB3 59
#define TEGRA30_CLK_MPE 60
#define TEGRA30_CLK_VDE 61
#define TEGRA30_CLK_BSEA 62
#define TEGRA30_CLK_BSEV 63
#define TEGRA30_CLK_SPEEDO 64
#define TEGRA30_CLK_UARTD 65
#define TEGRA30_CLK_UARTE 66
#define TEGRA30_CLK_I2C3 67
#define TEGRA30_CLK_SBC4 68
#define TEGRA30_CLK_SDMMC3 69
#define TEGRA30_CLK_PCIE 70
#define TEGRA30_CLK_OWR 71
#define TEGRA30_CLK_AFI 72
#define TEGRA30_CLK_CSITE 73
#define TEGRA30_CLK_PCIEX 74
#define TEGRA30_CLK_AVPUCQ 75
#define TEGRA30_CLK_LA 76
/* 77 */
/* 78 */
#define TEGRA30_CLK_DTV 79
#define TEGRA30_CLK_NDSPEED 80
#define TEGRA30_CLK_I2CSLOW 81
#define TEGRA30_CLK_DSIB 82
/* 83 */
#define TEGRA30_CLK_IRAMA 84
#define TEGRA30_CLK_IRAMB 85
#define TEGRA30_CLK_IRAMC 86
#define TEGRA30_CLK_IRAMD 87
#define TEGRA30_CLK_CRAM2 88
/* 89 */
#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
/* 91 */
#define TEGRA30_CLK_CSUS 92
#define TEGRA30_CLK_CDEV2 93
#define TEGRA30_CLK_CDEV1 94
/* 95 */
#define TEGRA30_CLK_CPU_G 96
#define TEGRA30_CLK_CPU_LP 97
#define TEGRA30_CLK_GR3D2 98
#define TEGRA30_CLK_MSELECT 99
#define TEGRA30_CLK_TSENSOR 100
#define TEGRA30_CLK_I2S3 101
#define TEGRA30_CLK_I2S4 102
#define TEGRA30_CLK_I2C4 103
#define TEGRA30_CLK_SBC5 104
#define TEGRA30_CLK_SBC6 105
#define TEGRA30_CLK_D_AUDIO 106
#define TEGRA30_CLK_APBIF 107
#define TEGRA30_CLK_DAM0 108
#define TEGRA30_CLK_DAM1 109
#define TEGRA30_CLK_DAM2 110
#define TEGRA30_CLK_HDA2CODEC_2X 111
#define TEGRA30_CLK_ATOMICS 112
#define TEGRA30_CLK_AUDIO0_2X 113
#define TEGRA30_CLK_AUDIO1_2X 114
#define TEGRA30_CLK_AUDIO2_2X 115
#define TEGRA30_CLK_AUDIO3_2X 116
#define TEGRA30_CLK_AUDIO4_2X 117
#define TEGRA30_CLK_SPDIF_2X 118
#define TEGRA30_CLK_ACTMON 119
#define TEGRA30_CLK_EXTERN1 120
#define TEGRA30_CLK_EXTERN2 121
#define TEGRA30_CLK_EXTERN3 122
#define TEGRA30_CLK_SATA_OOB 123
#define TEGRA30_CLK_SATA 124
#define TEGRA30_CLK_HDA 125
/* 126 */
#define TEGRA30_CLK_SE 127
#define TEGRA30_CLK_HDA2HDMI 128
#define TEGRA30_CLK_SATA_COLD 129
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* 143 */
/* 144 */
/* 145 */
/* 146 */
/* 147 */
/* 148 */
/* 149 */
/* 150 */
/* 151 */
/* 152 */
/* 153 */
/* 154 */
/* 155 */
/* 156 */
/* 157 */
/* 158 */
/* 159 */
#define TEGRA30_CLK_UARTB 160
#define TEGRA30_CLK_VFIR 161
#define TEGRA30_CLK_SPDIF_IN 162
#define TEGRA30_CLK_SPDIF_OUT 163
#define TEGRA30_CLK_VI 164
#define TEGRA30_CLK_VI_SENSOR 165
#define TEGRA30_CLK_FUSE 166
#define TEGRA30_CLK_FUSE_BURN 167
#define TEGRA30_CLK_CVE 168
#define TEGRA30_CLK_TVO 169
#define TEGRA30_CLK_CLK_32K 170
#define TEGRA30_CLK_CLK_M 171
#define TEGRA30_CLK_CLK_M_DIV2 172
#define TEGRA30_CLK_CLK_M_DIV4 173
#define TEGRA30_CLK_PLL_REF 174
#define TEGRA30_CLK_PLL_C 175
#define TEGRA30_CLK_PLL_C_OUT1 176
#define TEGRA30_CLK_PLL_M 177
#define TEGRA30_CLK_PLL_M_OUT1 178
#define TEGRA30_CLK_PLL_P 179
#define TEGRA30_CLK_PLL_P_OUT1 180
#define TEGRA30_CLK_PLL_P_OUT2 181
#define TEGRA30_CLK_PLL_P_OUT3 182
#define TEGRA30_CLK_PLL_P_OUT4 183
#define TEGRA30_CLK_PLL_A 184
#define TEGRA30_CLK_PLL_A_OUT0 185
#define TEGRA30_CLK_PLL_D 186
#define TEGRA30_CLK_PLL_D_OUT0 187
#define TEGRA30_CLK_PLL_D2 188
#define TEGRA30_CLK_PLL_D2_OUT0 189
#define TEGRA30_CLK_PLL_U 190
#define TEGRA30_CLK_PLL_X 191
#define TEGRA30_CLK_PLL_X_OUT0 192
#define TEGRA30_CLK_PLL_E 193
#define TEGRA30_CLK_SPDIF_IN_SYNC 194
#define TEGRA30_CLK_I2S0_SYNC 195
#define TEGRA30_CLK_I2S1_SYNC 196
#define TEGRA30_CLK_I2S2_SYNC 197
#define TEGRA30_CLK_I2S3_SYNC 198
#define TEGRA30_CLK_I2S4_SYNC 199
#define TEGRA30_CLK_VIMCLK_SYNC 200
#define TEGRA30_CLK_AUDIO0 201
#define TEGRA30_CLK_AUDIO1 202
#define TEGRA30_CLK_AUDIO2 203
#define TEGRA30_CLK_AUDIO3 204
#define TEGRA30_CLK_AUDIO4 205
#define TEGRA30_CLK_SPDIF 206
#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
#define TEGRA30_CLK_SCLK 210
#define TEGRA30_CLK_BLINK 211
#define TEGRA30_CLK_CCLK_G 212
#define TEGRA30_CLK_CCLK_LP 213
#define TEGRA30_CLK_TWD 214
#define TEGRA30_CLK_CML0 215
#define TEGRA30_CLK_CML1 216
#define TEGRA30_CLK_HCLK 217
#define TEGRA30_CLK_PCLK 218
/* 219 */
/* 220 */
/* 221 */
/* 222 */
/* 223 */
/* 288 */
/* 289 */
/* 290 */
/* 291 */
/* 292 */
/* 293 */
/* 294 */
/* 295 */
/* 296 */
/* 297 */
/* 298 */
/* 299 */
#define TEGRA30_CLK_CLK_OUT_1_MUX 300
#define TEGRA30_CLK_CLK_MAX 301
#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */

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include/dt-bindings/gpio/tegra-gpio.h Normal file
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/*
* This header provides constants for binding nvidia,tegra*-gpio.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
#include <dt-bindings/gpio/gpio.h>
#define TEGRA_GPIO_BANK_ID_A 0
#define TEGRA_GPIO_BANK_ID_B 1
#define TEGRA_GPIO_BANK_ID_C 2
#define TEGRA_GPIO_BANK_ID_D 3
#define TEGRA_GPIO_BANK_ID_E 4
#define TEGRA_GPIO_BANK_ID_F 5
#define TEGRA_GPIO_BANK_ID_G 6
#define TEGRA_GPIO_BANK_ID_H 7
#define TEGRA_GPIO_BANK_ID_I 8
#define TEGRA_GPIO_BANK_ID_J 9
#define TEGRA_GPIO_BANK_ID_K 10
#define TEGRA_GPIO_BANK_ID_L 11
#define TEGRA_GPIO_BANK_ID_M 12
#define TEGRA_GPIO_BANK_ID_N 13
#define TEGRA_GPIO_BANK_ID_O 14
#define TEGRA_GPIO_BANK_ID_P 15
#define TEGRA_GPIO_BANK_ID_Q 16
#define TEGRA_GPIO_BANK_ID_R 17
#define TEGRA_GPIO_BANK_ID_S 18
#define TEGRA_GPIO_BANK_ID_T 19
#define TEGRA_GPIO_BANK_ID_U 20
#define TEGRA_GPIO_BANK_ID_V 21
#define TEGRA_GPIO_BANK_ID_W 22
#define TEGRA_GPIO_BANK_ID_X 23
#define TEGRA_GPIO_BANK_ID_Y 24
#define TEGRA_GPIO_BANK_ID_Z 25
#define TEGRA_GPIO_BANK_ID_AA 26
#define TEGRA_GPIO_BANK_ID_BB 27
#define TEGRA_GPIO_BANK_ID_CC 28
#define TEGRA_GPIO_BANK_ID_DD 29
#define TEGRA_GPIO_BANK_ID_EE 30
#define TEGRA_GPIO(bank, offset) \
((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
#endif