clk: ti: omap5: Add missing AESS clock
Looks like we're missing AESS clock for omap5. This is similar to what omap4 has. Cc: H. Nikolaus Schaller <hns@goldelico.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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@ -35,6 +35,20 @@ static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst =
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{ 0 },
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};
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static const char * const omap5_aess_fclk_parents[] __initconst = {
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"abe_clk",
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NULL,
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};
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static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = {
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.max_div = 2,
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};
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static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
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{ 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data },
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{ 0 },
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};
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static const char * const omap5_dmic_gfclk_parents[] __initconst = {
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"abe_cm:clk:0018:26",
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"pad_clks_ck",
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@ -122,6 +136,7 @@ static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst =
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static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
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{ OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
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{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
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{ OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
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{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
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{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
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@ -16,6 +16,7 @@
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/* abe clocks */
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#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
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#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
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#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
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