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arm-soc: sparse IRQ conversion 

The I.MX platform is getting converted to use sparse IRQs. We are doing
 this for all platforms over time, because this is one of the
 requirements for building a multiplatform kernel, and generally a good
 idea.
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Merge tag 'irq' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc sparse IRQ conversion from Arnd Bergmann:
 "The I.MX platform is getting converted to use sparse IRQs.  We are
  doing this for all platforms over time, because this is one of the
  requirements for building a multiplatform kernel, and generally a good
  idea."

* tag 'irq' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: imx: select USE_OF
  ARM: imx: Fix build error due to missing irqs.h include
  ARM: imx: enable SPARSE_IRQ for imx platform
  ARM: fiq: change FIQ_START to a variable
  tty: serial: imx: remove the use of MXC_INTERNAL_IRQS
  ARM: imx: remove unneeded mach/irq.h inclusion
  i2c: imx: remove unneeded mach/irqs.h inclusion
  ARM: imx: add a legacy irqdomain for mx31ads
  ARM: imx: add a legacy irqdomain for 3ds_debugboard
  ARM: imx: pass gpio than irq number into mxc_expio_init
  ARM: imx: leave irq_base of wm8350_platform_data uninitialized
  dma: ipu: remove the use of ipu_platform_data
  ARM: imx: move irq_domain_add_legacy call into avic driver
  ARM: imx: move irq_domain_add_legacy call into tzic driver
  gpio/mxc: move irq_domain_add_legacy call into gpio driver
  ARM: imx: eliminate macro IRQ_GPIOx()
  ARM: imx: eliminate macro IOMUX_TO_IRQ()
  ARM: imx: eliminate macro IMX_GPIO_TO_IRQ()
This commit is contained in:
Linus Torvalds 2012-07-23 17:36:02 -07:00
parent f1d2c07d33 c7b0807b9d
commit 3645f0cd96
79 changed files with 1052 additions and 1131 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/Kconfig
View File

@ -470,6 +470,8 @@ config ARCH_MXC
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
select USE_OF
help
Support for Freescale MXC/iMX-based family of processors

2
arch/arm/include/asm/mach/irq.h
View File

@ -17,7 +17,7 @@ struct seq_file;
/*
* This is internal. Do not use it.
*/
extern void init_FIQ(void);
extern void init_FIQ(int);
extern int show_fiq_list(struct seq_file *, int);
#ifdef CONFIG_MULTI_IRQ_HANDLER

9
arch/arm/kernel/fiq.c
View File

@ -122,14 +122,16 @@ void release_fiq(struct fiq_handler *f)
while (current_fiq->fiq_op(current_fiq->dev_id, 0));
}
static int fiq_start;
void enable_fiq(int fiq)
{
enable_irq(fiq + FIQ_START);
enable_irq(fiq + fiq_start);
}
void disable_fiq(int fiq)
{
disable_irq(fiq + FIQ_START);
disable_irq(fiq + fiq_start);
}
EXPORT_SYMBOL(set_fiq_handler);
@ -140,7 +142,8 @@ EXPORT_SYMBOL(release_fiq);
EXPORT_SYMBOL(enable_fiq);
EXPORT_SYMBOL(disable_fiq);
void __init init_FIQ(void)
void __init init_FIQ(int start)
{
no_fiq_insn = *(unsigned long *)0xffff001c;
fiq_start = start;
}

4
arch/arm/mach-imx/Kconfig
View File

@ -382,7 +382,6 @@ config MACH_IMX27IPCAM
config MACH_IMX27_DT
bool "Support i.MX27 platforms from device tree"
select SOC_IMX27
select USE_OF
help
Include support for Freescale i.MX27 based platforms
using the device tree for discovery
@ -674,7 +673,6 @@ comment "i.MX51 machines:"
config MACH_IMX51_DT
bool "Support i.MX51 platforms from device tree"
select SOC_IMX51
select USE_OF
select MACH_MX51_BABBAGE
help
Include support for Freescale i.MX51 based platforms
@ -770,7 +768,6 @@ comment "i.MX53 machines:"
config MACH_IMX53_DT
bool "Support i.MX53 platforms from device tree"
select SOC_IMX53
select USE_OF
select MACH_MX53_ARD
select MACH_MX53_EVK
select MACH_MX53_LOCO
@ -845,7 +842,6 @@ config SOC_IMX6Q
select MFD_ANATOP
select PINCTRL
select PINCTRL_IMX6Q
select USE_OF
help
This enables support for Freescale i.MX6 Quad processor.

4
arch/arm/mach-imx/devices-imx31.h
View File

@ -42,8 +42,8 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[];
#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
extern const struct imx_ipu_core_data imx31_ipu_core_data;
#define imx31_add_ipu_core(pdata) \
imx_add_ipu_core(&imx31_ipu_core_data, pdata)
#define imx31_add_ipu_core() \
imx_add_ipu_core(&imx31_ipu_core_data)
#define imx31_alloc_mx3_camera(pdata) \
imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata)
#define imx31_add_mx3_sdc_fb(pdata) \

4
arch/arm/mach-imx/devices-imx35.h
View File

@ -50,8 +50,8 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[];
#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
extern const struct imx_ipu_core_data imx35_ipu_core_data;
#define imx35_add_ipu_core(pdata) \
imx_add_ipu_core(&imx35_ipu_core_data, pdata)
#define imx35_add_ipu_core() \
imx_add_ipu_core(&imx35_ipu_core_data)
#define imx35_alloc_mx3_camera(pdata) \
imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata)
#define imx35_add_mx3_sdc_fb(pdata) \

3
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
View File

@ -266,7 +266,7 @@ static struct spi_board_info __maybe_unused
.bus_num = 0,
.chip_select = 0,
.max_speed_hz = 1500000,
.irq = IRQ_GPIOD(25),
/* irq number is run-time assigned */
.platform_data = &ads7846_config,
.mode = SPI_MODE_2,
},
@ -329,6 +329,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
/* SPI_CS0 init */
mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
eukrea_mbimx27_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(4, 25));
spi_register_board_info(eukrea_mbimx27_spi_board_info,
ARRAY_SIZE(eukrea_mbimx27_spi_board_info));

6
arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
View File

@ -95,10 +95,6 @@ static const struct fb_videomode fb_modedb[] = {
},
};
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "CMO-QVGA",
.mode = fb_modedb,
@ -287,7 +283,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
printk(KERN_ERR "error setting mbimxsd pads !\n");
imx35_add_imx_uart1(&uart_pdata);
imx35_add_ipu_core(&mx3_ipu_data);
imx35_add_ipu_core();
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);

28
arch/arm/mach-imx/imx27-dt.c
View File

@ -10,7 +10,6 @@
*/
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
@ -33,35 +32,8 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
{ /* sentinel */ }
};
static int __init imx27_avic_add_irq_domain(struct device_node *np,
struct device_node *interrupt_parent)
{
irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
return 0;
}
static int __init imx27_gpio_add_irq_domain(struct device_node *np,
struct device_node *interrupt_parent)
{
static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
gpio_irq_base -= 32;
irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
NULL);
return 0;
}
static const struct of_device_id imx27_irq_match[] __initconst = {
{ .compatible = "fsl,imx27-avic", .data = imx27_avic_add_irq_domain, },
{ .compatible = "fsl,imx27-gpio", .data = imx27_gpio_add_irq_domain, },
{ /* sentinel */ }
};
static void __init imx27_dt_init(void)
{
of_irq_init(imx27_irq_match);
of_platform_populate(NULL, of_default_bus_match_table,
imx27_auxdata_lookup, NULL);
}

27
arch/arm/mach-imx/imx51-dt.c
View File

@ -11,7 +11,6 @@
*/
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/machine.h>
@ -45,30 +44,6 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
{ /* sentinel */ }
};
static int __init imx51_tzic_add_irq_domain(struct device_node *np,
struct device_node *interrupt_parent)
{
irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
return 0;
}
static int __init imx51_gpio_add_irq_domain(struct device_node *np,
struct device_node *interrupt_parent)
{
static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
gpio_irq_base -= 32;
irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
return 0;
}
static const struct of_device_id imx51_irq_match[] __initconst = {
{ .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
{ .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
{ /* sentinel */ }
};
static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
{ .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
{ /* sentinel */ }
@ -80,8 +55,6 @@ static void __init imx51_dt_init(void)
const struct of_device_id *of_id;
void (*func)(void);
of_irq_init(imx51_irq_match);
pinctrl_provide_dummies();
node = of_find_matching_node(NULL, imx51_iomuxc_of_match);

27
arch/arm/mach-imx/imx53-dt.c
View File

@ -15,7 +15,6 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/machine.h>
@ -52,30 +51,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
{ /* sentinel */ }
};
static int __init imx53_tzic_add_irq_domain(struct device_node *np,
struct device_node *interrupt_parent)
{
irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
return 0;
}
static int __init imx53_gpio_add_irq_domain(struct device_node *np,
struct device_node *interrupt_parent)
{
static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
gpio_irq_base -= 32;
irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
return 0;
}
static const struct of_device_id imx53_irq_match[] __initconst = {
{ .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
{ .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
{ /* sentinel */ }
};
static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
{ .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
{ .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
@ -103,8 +78,6 @@ static void __init imx53_dt_init(void)
const struct of_device_id *of_id;
void (*func)(void);
of_irq_init(imx53_irq_match);
pinctrl_provide_dummies();
node = of_find_matching_node(NULL, imx53_iomuxc_of_match);

7
arch/arm/mach-imx/mach-apf9328.c
View File

@ -18,6 +18,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/dm9000.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
@ -26,7 +27,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/iomux-mx1.h>
#include "devices-imx1.h"
@ -87,8 +87,7 @@ static struct resource dm9000_resources[] = {
.end = MX1_CS4_PHYS + 0x00C00003,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_GPIOB(14),
.end = IRQ_GPIOB(14),
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
@ -129,6 +128,8 @@ static void __init apf9328_init(void)
imx1_add_imx_i2c(&apf9328_i2c_data);
dm9000_resources[2].start = gpio_to_irq(IMX_GPIO_NR(2, 14));
dm9000_resources[2].end = gpio_to_irq(IMX_GPIO_NR(2, 14));
platform_add_devices(devices, ARRAY_SIZE(devices));
}

18
arch/arm/mach-imx/mach-armadillo5x0.c
View File

@ -367,10 +367,6 @@ static const struct fb_videomode fb_modedb[] = {
},
};
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "CRT-VGA",
.mode = fb_modedb,
@ -408,7 +404,8 @@ static int armadillo5x0_sdhc1_init(struct device *dev,
gpio_direction_input(gpio_wp);
/* When supported the trigger type have to be BOTH */
ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), detect_irq,
ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)),
detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"sdhc-detect", data);
@ -429,7 +426,7 @@ err_gpio_free:
static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
{
free_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), data);
free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), data);
gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK));
gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
}
@ -450,8 +447,7 @@ static struct resource armadillo5x0_smc911x_resources[] = {
.end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
.end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
@ -498,6 +494,10 @@ static void __init armadillo5x0_init(void)
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
armadillo5x0_smc911x_resources[1].start =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
armadillo5x0_smc911x_resources[1].end =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
platform_add_devices(devices, ARRAY_SIZE(devices));
imx_add_gpio_keys(&armadillo5x0_button_data);
imx31_add_imx_i2c1(NULL);
@ -513,7 +513,7 @@ static void __init armadillo5x0_init(void)
imx31_add_mxc_mmc(0, &sdhc_pdata);
/* Register FB */
imx31_add_ipu_core(&mx3_ipu_data);
imx31_add_ipu_core();
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* Register NOR Flash */

12
arch/arm/mach-imx/mach-cpuimx27.c
View File

@ -169,28 +169,28 @@ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
static struct plat_serial8250_port serial_platform_data[] = {
{
.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
.irq = IRQ_GPIOB(23),
/* irq number is run-time assigned */
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
.irq = IRQ_GPIOB(22),
/* irq number is run-time assigned */
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
.irq = IRQ_GPIOB(27),
/* irq number is run-time assigned */
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
.irq = IRQ_GPIOB(30),
/* irq number is run-time assigned */
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
@ -279,6 +279,10 @@ static void __init eukrea_cpuimx27_init(void)
#endif
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
serial_platform_data[0].irq = IMX_GPIO_NR(2, 23);
serial_platform_data[1].irq = IMX_GPIO_NR(2, 22);
serial_platform_data[2].irq = IMX_GPIO_NR(2, 27);
serial_platform_data[3].irq = IMX_GPIO_NR(2, 30);
platform_device_register(&serial_device);
#endif

3
arch/arm/mach-imx/mach-cpuimx35.c
View File

@ -71,7 +71,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
}, {
I2C_BOARD_INFO("tsc2007", 0x48),
.platform_data = &tsc2007_info,
.irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
/* irq number is run-time assigned */
},
};
@ -172,6 +172,7 @@ static void __init eukrea_cpuimx35_init(void)
imx35_add_imx_uart0(&uart_pdata);
imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
eukrea_cpuimx35_i2c_devices[1].irq = gpio_to_irq(TSC2007_IRQGPIO);
i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);

3
arch/arm/mach-imx/mach-cpuimx51sd.c
View File

@ -258,7 +258,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
.mode = SPI_MODE_0,
.chip_select = 0,
.platform_data = &mcp251x_info,
.irq = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
/* irq number is run-time assigned */
},
};
@ -309,6 +309,7 @@ static void __init eukrea_cpuimx51sd_init(void)
msleep(20);
gpio_set_value(CAN_RST, 1);
imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
spi_register_board_info(cpuimx51sd_spi_device,
ARRAY_SIZE(cpuimx51sd_spi_device));

9
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
View File

@ -40,6 +40,7 @@
#include <asm/mach/time.h>
#include <asm/system_info.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include "devices-imx27.h"
@ -47,7 +48,7 @@
#define TVP5150_RSTN (GPIO_PORTC + 18)
#define TVP5150_PWDN (GPIO_PORTC + 19)
#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
#define SDHC1_IRQ IRQ_GPIOB(25)
#define SDHC1_IRQ_GPIO IMX_GPIO_NR(2, 25)
#define MOTHERBOARD_BIT2 (GPIO_PORTD + 31)
#define MOTHERBOARD_BIT1 (GPIO_PORTD + 30)
@ -307,14 +308,14 @@ static int visstrim_m10_sdhc1_init(struct device *dev,
{
int ret;
ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING,
"mmc-detect", data);
ret = request_irq(gpio_to_irq(SDHC1_IRQ_GPIO), detect_irq,
IRQF_TRIGGER_FALLING, "mmc-detect", data);
return ret;
}
static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
{
free_irq(SDHC1_IRQ, data);
free_irq(gpio_to_irq(SDHC1_IRQ_GPIO), data);
}
static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = {

14
arch/arm/mach-imx/mach-imx6q.c
View File

@ -16,7 +16,6 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@ -177,21 +176,8 @@ static void __init imx6q_map_io(void)
imx6q_clock_map_io();
}
static int __init imx6q_gpio_add_irq_domain(struct device_node *np,
struct device_node *interrupt_parent)
{
static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
gpio_irq_base -= 32;
irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
NULL);
return 0;
}
static const struct of_device_id imx6q_irq_match[] __initconst = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
{ .compatible = "fsl,imx6q-gpio", .data = imx6q_gpio_add_irq_domain, },
{ /* sentinel */ }
};

20
arch/arm/mach-imx/mach-kzm_arm11_01.c
View File

@ -73,7 +73,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
{
.membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
.mapbase = KZM_ARM11_16550,
.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
/* irq number is run-time assigned */
.irqflags = IRQ_TYPE_EDGE_RISING,
.uartclk = 14745600,
.regshift = 0,
@ -91,8 +91,7 @@ static struct resource serial8250_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
.end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ,
},
};
@ -125,6 +124,13 @@ static int __init kzm_init_ext_uart(void)
tmp |= 0x2;
__raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
serial_platform_data[0].irq =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
serial8250_resources[1].start =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
serial8250_resources[1].end =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
return platform_device_register(&serial_device);
}
#else
@ -152,8 +158,7 @@ static struct resource kzm_smsc9118_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
.end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};
@ -184,6 +189,11 @@ static int __init kzm_init_smsc9118(void)
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
kzm_smsc9118_resources[1].start =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
kzm_smsc9118_resources[1].end =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
return platform_device_register(&kzm_smsc9118_device);
}
#else

1
arch/arm/mach-imx/mach-mx1ads.c
View File

@ -26,7 +26,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx1.h>
#include <mach/irqs.h>
#include "devices-imx1.h"

16
arch/arm/mach-imx/mach-mx21ads.c
View File

@ -38,7 +38,7 @@
(MX21ADS_MMIO_BASE_ADDR + (offset))
#define MX21ADS_CS8900A_MMIO_SIZE 0x200000
#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
#define MX21ADS_CS8900A_IRQ_GPIO IMX_GPIO_NR(5, 11)
#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
@ -159,9 +159,10 @@ static struct platform_device mx21ads_nor_mtd_device = {
.resource = &mx21ads_flash_resource,
};
static const struct resource mx21ads_cs8900_resources[] __initconst = {
static struct resource mx21ads_cs8900_resources[] __initdata = {
DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE),
DEFINE_RES_IRQ(MX21ADS_CS8900A_IRQ),
/* irq number is run-time assigned */
DEFINE_RES_IRQ(-1),
};
static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = {
@ -241,13 +242,13 @@ static int mx21ads_sdhc_get_ro(struct device *dev)
static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
return request_irq(IRQ_GPIOD(25), detect_irq,
return request_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), detect_irq,
IRQF_TRIGGER_FALLING, "mmc-detect", data);
}
static void mx21ads_sdhc_exit(struct device *dev, void *data)
{
free_irq(IRQ_GPIOD(25), data);
free_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), data);
}
static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
@ -304,6 +305,11 @@ static void __init mx21ads_board_init(void)
imx21_add_mxc_nand(&mx21ads_nand_board_info);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
mx21ads_cs8900_resources[1].start =
gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
mx21ads_cs8900_resources[1].end =
gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
platform_device_register_full(&mx21ads_cs8900_devinfo);
}

7
arch/arm/mach-imx/mach-mx27_3ds.c
View File

@ -40,7 +40,6 @@
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/ulpi.h>
#include <mach/irqs.h>
#include <mach/3ds_debugboard.h>
#include "devices-imx27.h"
@ -48,7 +47,6 @@
#define SD1_EN_GPIO IMX_GPIO_NR(2, 25)
#define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23)
#define SPI2_SS0 IMX_GPIO_NR(4, 21)
#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(3, 28))
#define PMIC_INT IMX_GPIO_NR(3, 14)
#define SPI1_SS0 IMX_GPIO_NR(4, 28)
#define SD1_CD IMX_GPIO_NR(2, 26)
@ -445,7 +443,7 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
.bus_num = 1,
.chip_select = 0, /* SS0 */
.platform_data = &mc13783_pdata,
.irq = IMX_GPIO_TO_IRQ(PMIC_INT),
/* irq number is run-time assigned */
.mode = SPI_CS_HIGH,
}, {
.modalias = "l4f00242t03",
@ -496,10 +494,11 @@ static void __init mx27pdk_init(void)
imx27_add_spi_imx1(&spi2_pdata);
imx27_add_spi_imx0(&spi1_pdata);
mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT);
spi_register_board_info(mx27_3ds_spi_devs,
ARRAY_SIZE(mx27_3ds_spi_devs));
if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28)))
pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
platform_add_devices(devices, ARRAY_SIZE(devices));

12
arch/arm/mach-imx/mach-mx27ads.c
View File

@ -246,25 +246,25 @@ static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
"sdhc1-card-detect", data);
return request_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), detect_irq,
IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
}
static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
"sdhc2-card-detect", data);
return request_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), detect_irq,
IRQF_TRIGGER_RISING, "sdhc2-card-detect", data);
}
static void mx27ads_sdhc1_exit(struct device *dev, void *data)
{
free_irq(IRQ_GPIOE(21), data);
free_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), data);
}
static void mx27ads_sdhc2_exit(struct device *dev, void *data)
{
free_irq(IRQ_GPIOB(7), data);
free_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), data);
}
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {

18
arch/arm/mach-imx/mach-mx31_3ds.c
View File

@ -44,9 +44,6 @@
#include "devices-imx31.h"
/* CPLD IRQ line for external uart, external ethernet etc */
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
static int mx31_3ds_pins[] = {
/* UART1 */
MX31_PIN_CTS1__CTS1,
@ -277,10 +274,6 @@ static const struct fb_videomode fb_modedb[] = {
},
};
static struct ipu_platform_data mx3_ipu_data = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "Epson-VGA",
.mode = fb_modedb,
@ -317,7 +310,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
return ret;
}
ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)),
detect_irq, IRQF_DISABLED |
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
"sdhc1-detect", data);
@ -336,7 +329,7 @@ gpio_free:
static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
{
free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data);
gpio_free_array(mx31_3ds_sdhc1_gpios,
ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
}
@ -539,7 +532,7 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
.bus_num = 1,
.chip_select = 1, /* SS2 */
.platform_data = &mc13783_pdata,
.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
/* irq number is run-time assigned */
.mode = SPI_CS_HIGH,
}, {
.modalias = "l4f00242t03",
@ -714,6 +707,7 @@ static void __init mx31_3ds_init(void)
imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
imx31_add_spi_imx1(&spi1_pdata);
mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
spi_register_board_info(mx31_3ds_spi_devs,
ARRAY_SIZE(mx31_3ds_spi_devs));
@ -736,7 +730,7 @@ static void __init mx31_3ds_init(void)
if (!otg_mode_host)
imx31_add_fsl_usb2_udc(&usbotg_pdata);
if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
if (mxc_expio_init(MX31_CS5_BASE_ADDR, IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)))
printk(KERN_WARNING "Init of the debug board failed, all "
"devices on the debug board are unusable.\n");
imx31_add_imx2_wdt();
@ -744,7 +738,7 @@ static void __init mx31_3ds_init(void)
imx31_add_mxc_mmc(0, &sdhc1_pdata);
imx31_add_spi_imx0(&spi0_pdata);
imx31_add_ipu_core(&mx3_ipu_data);
imx31_add_ipu_core();
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* CSI */

63
arch/arm/mach-imx/mach-mx31ads.c
View File

@ -21,6 +21,7 @@
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -62,20 +63,18 @@
#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
#define MXC_EXP_IO_BASE MXC_BOARD_IRQ_START
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
#define EXPIO_INT_XUART_INTA 10
#define EXPIO_INT_XUART_INTB 11
#define MXC_MAX_EXP_IO_LINES 16
/* CS8900 */
#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
#define EXPIO_INT_ENET_INT 8
#define CS4_CS8900_MMIO_START 0x20000
static struct irq_domain *domain;
/*
* The serial port definition structure.
*/
@ -83,7 +82,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
{
.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
.irq = EXPIO_INT_XUART_INTA,
.uartclk = 14745600,
.regshift = 0,
.iotype = UPIO_MEM,
@ -91,7 +89,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
}, {
.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
.irq = EXPIO_INT_XUART_INTB,
.uartclk = 14745600,
.regshift = 0,
.iotype = UPIO_MEM,
@ -108,9 +105,9 @@ static struct platform_device serial_device = {
},
};
static const struct resource mx31ads_cs8900_resources[] __initconst = {
static struct resource mx31ads_cs8900_resources[] __initdata = {
DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
DEFINE_RES_IRQ(EXPIO_INT_ENET_INT),
DEFINE_RES_IRQ(-1),
};
static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
@ -122,11 +119,19 @@ static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
static int __init mxc_init_extuart(void)
{
serial_platform_data[0].irq = irq_find_mapping(domain,
EXPIO_INT_XUART_INTA);
serial_platform_data[1].irq = irq_find_mapping(domain,
EXPIO_INT_XUART_INTB);
return platform_device_register(&serial_device);
}
static void __init mxc_init_ext_ethernet(void)
{
mx31ads_cs8900_resources[1].start =
irq_find_mapping(domain, EXPIO_INT_ENET_INT);
mx31ads_cs8900_resources[1].end =
irq_find_mapping(domain, EXPIO_INT_ENET_INT);
platform_device_register_full(
(struct platform_device_info *)&mx31ads_cs8900_devinfo);
}
@ -157,12 +162,12 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
imr_val = __raw_readw(PBC_INTMASK_SET_REG);
int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
expio_irq = MXC_EXP_IO_BASE;
expio_irq = 0;
for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
if ((int_valid & 1) == 0)
continue;
generic_handle_irq(expio_irq);
generic_handle_irq(irq_find_mapping(domain, expio_irq));
}
}
@ -172,7 +177,7 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
*/
static void expio_mask_irq(struct irq_data *d)
{
u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
u32 expio = d->hwirq;
/* mask the interrupt */
__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
__raw_readw(PBC_INTMASK_CLEAR_REG);
@ -184,7 +189,7 @@ static void expio_mask_irq(struct irq_data *d)
*/
static void expio_ack_irq(struct irq_data *d)
{
u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
u32 expio = d->hwirq;
/* clear the interrupt status */
__raw_writew(1 << expio, PBC_INTSTATUS_REG);
}
@ -195,7 +200,7 @@ static void expio_ack_irq(struct irq_data *d)
*/
static void expio_unmask_irq(struct irq_data *d)
{
u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
u32 expio = d->hwirq;
/* unmask the interrupt */
__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
}
@ -209,7 +214,8 @@ static struct irq_chip expio_irq_chip = {
static void __init mx31ads_init_expio(void)
{
int i;
int irq_base;
int i, irq;
printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
@ -221,13 +227,21 @@ static void __init mx31ads_init_expio(void)
/* disable the interrupt and clear the status */
__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
i++) {
irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
WARN_ON(irq_base < 0);
domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
&irq_domain_simple_ops, NULL);
WARN_ON(!domain);
for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
irq_set_chained_handler(irq, mx31ads_expio_irq_handler);
}
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@ -479,7 +493,6 @@ static int mx31_wm8350_init(struct wm8350 *wm8350)
static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
.init = mx31_wm8350_init,
.irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
};
#endif
@ -488,13 +501,17 @@ static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
{
I2C_BOARD_INFO("wm8350", 0x1a),
.platform_data = &mx31_wm8350_pdata,
.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
/* irq number is run-time assigned */
},
#endif
};
static void __init mxc_init_i2c(void)
{
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
mx31ads_i2c1_devices[0].irq =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
#endif
i2c_register_board_info(1, mx31ads_i2c1_devices,
ARRAY_SIZE(mx31ads_i2c1_devices));

10
arch/arm/mach-imx/mach-mx31lilly.c
View File

@ -65,8 +65,7 @@ static struct resource smsc91x_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
.end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
}
};
@ -233,7 +232,7 @@ static struct spi_board_info mc13783_dev __initdata = {
.bus_num = 1,
.chip_select = 0,
.platform_data = &mc13783_pdata,
.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
/* irq number is run-time assigned */
};
static struct platform_device *devices[] __initdata = {
@ -285,10 +284,15 @@ static void __init mx31lilly_board_init(void)
imx31_add_spi_imx0(&spi0_pdata);
imx31_add_spi_imx1(&spi1_pdata);
mc13783_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
spi_register_board_info(&mc13783_dev, 1);
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
smsc91x_resources[1].start =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
smsc91x_resources[1].end =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
platform_add_devices(devices, ARRAY_SIZE(devices));
/* USB */

11
arch/arm/mach-imx/mach-mx31lite.c
View File

@ -43,7 +43,6 @@
#include <mach/common.h>
#include <mach/board-mx31lite.h>
#include <mach/iomux-mx3.h>
#include <mach/irqs.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
@ -83,8 +82,7 @@ static struct resource smsc911x_resources[] = {
.end = MX31_CS4_BASE_ADDR + 0x100,
.flags = IORESOURCE_MEM,
}, {
.start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
.end = IOMUX_TO_IRQ(MX31_PIN_SFS6),
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ,
},
};
@ -124,7 +122,7 @@ static struct spi_board_info mc13783_spi_dev __initdata = {
.bus_num = 1,
.chip_select = 0,
.platform_data = &mc13783_pdata,
.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
/* irq number is run-time assigned */
};
/*
@ -258,6 +256,7 @@ static void __init mx31lite_init(void)
imx31_add_mxc_nand(&mx31lite_nand_board_info);
imx31_add_spi_imx1(&spi1_pdata);
mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
spi_register_board_info(&mc13783_spi_dev, 1);
/* USB */
@ -274,6 +273,10 @@ static void __init mx31lite_init(void)
pr_warning("could not get LAN irq gpio\n");
else {
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
smsc911x_resources[1].start =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
smsc911x_resources[1].end =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
platform_device_register(&smsc911x_device);
}
}

10
arch/arm/mach-imx/mach-mx31moboard.c
View File

@ -303,7 +303,7 @@ static struct imx_ssi_platform_data moboard_ssi_pdata = {
static struct spi_board_info moboard_spi_board_info[] __initdata = {
{
.modalias = "mc13783",
.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
/* irq number is run-time assigned */
.max_speed_hz = 300000,
.bus_num = 1,
.chip_select = 0,
@ -473,10 +473,6 @@ static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = {
.leds = mx31moboard_leds,
};
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct platform_device *devices[] __initdata = {
&mx31moboard_flash,
};
@ -494,7 +490,7 @@ static int __init mx31moboard_init_cam(void)
int dma, ret = -ENOMEM;
struct platform_device *pdev;
imx31_add_ipu_core(&mx3_ipu_data);
imx31_add_ipu_core();
pdev = imx31_alloc_mx3_camera(&camera_pdata);
if (IS_ERR(pdev))
@ -557,6 +553,8 @@ static void __init mx31moboard_init(void)
gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
moboard_spi_board_info[0].irq =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
spi_register_board_info(moboard_spi_board_info,
ARRAY_SIZE(moboard_spi_board_info));

18
arch/arm/mach-imx/mach-mx35_3ds.c
View File

@ -46,7 +46,6 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/irqs.h>
#include <mach/3ds_debugboard.h>
#include <video/platform_lcd.h>
@ -80,10 +79,6 @@ static const struct fb_videomode fb_modedb[] = {
},
};
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "Ceramate-CLAA070VC01",
.mode = fb_modedb,
@ -136,8 +131,6 @@ static struct platform_device mx35_3ds_lcd = {
.dev.platform_data = &mx35_3ds_lcd_data,
};
#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 1))
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
@ -297,10 +290,6 @@ err:
return ret;
}
static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct i2c_board_info mx35_3ds_i2c_camera = {
I2C_BOARD_INFO("ov2640", 0x30),
};
@ -492,7 +481,7 @@ static struct i2c_board_info mx35_3ds_i2c_mc13892 = {
I2C_BOARD_INFO("mc13892", 0x08),
.platform_data = &mx35_3ds_mc13892_data,
.irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
/* irq number is run-time assigned */
};
static void __init imx35_3ds_init_mc13892(void)
@ -504,6 +493,7 @@ static void __init imx35_3ds_init_mc13892(void)
return;
}
mx35_3ds_i2c_mc13892.irq = gpio_to_irq(GPIO_PMIC_INT);
i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1);
}
@ -588,7 +578,7 @@ static void __init mx35_3ds_init(void)
imx35_add_mxc_nand(&mx35pdk_nand_board_info);
imx35_add_sdhci_esdhc_imx(0, NULL);
if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
if (mxc_expio_init(MX35_CS5_BASE_ADDR, IMX_GPIO_NR(1, 1)))
pr_warn("Init of the debugboard failed, all "
"devices on the debugboard are unusable.\n");
imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
@ -596,7 +586,7 @@ static void __init mx35_3ds_init(void)
i2c_register_board_info(
0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
imx35_add_ipu_core(&mx35_3ds_ipu_data);
imx35_add_ipu_core();
platform_device_register(&mx35_3ds_ov2640);
imx35_3ds_init_camera();

3
arch/arm/mach-imx/mach-mx51_3ds.c
View File

@ -26,7 +26,6 @@
#include "devices-imx51.h"
#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 6))
#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
static iomux_v3_cfg_t mx51_3ds_pads[] = {
@ -148,7 +147,7 @@ static void __init mx51_3ds_init(void)
spi_register_board_info(mx51_3ds_spi_nor_device,
ARRAY_SIZE(mx51_3ds_spi_nor_device));
if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
if (mxc_expio_init(MX51_CS5_BASE_ADDR, IMX_GPIO_NR(1, 6)))
printk(KERN_WARNING "Init of the debugboard failed, all "
"devices on the board are unusable.\n");

5
arch/arm/mach-imx/mach-mx53_ard.c
View File

@ -135,8 +135,7 @@ static struct resource ard_smsc911x_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
.end = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ,
},
};
@ -240,6 +239,8 @@ static void __init mx53_ard_board_init(void)
imx53_ard_common_init();
mx53_ard_io_init();
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B);
ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B);
platform_add_devices(devices, ARRAY_SIZE(devices));
imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);

6
arch/arm/mach-imx/mach-mxt_td60.c
View File

@ -213,13 +213,13 @@ static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
return request_irq(IRQ_GPIOF(8), detect_irq, IRQF_TRIGGER_FALLING,
"sdhc1-card-detect", data);
return request_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), detect_irq,
IRQF_TRIGGER_FALLING, "sdhc1-card-detect", data);
}
static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
{
free_irq(IRQ_GPIOF(8), data);
free_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), data);
}
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {

5
arch/arm/mach-imx/mach-pca100.c
View File

@ -36,7 +36,6 @@
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <asm/mach/time.h>
#include <mach/irqs.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
@ -245,7 +244,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
{
int ret;
ret = request_irq(IRQ_GPIOC(29), detect_irq,
ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"imx-mmc-detect", data);
if (ret)
@ -257,7 +256,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
static void pca100_sdhc2_exit(struct device *dev, void *data)
{
free_irq(IRQ_GPIOC(29), data);
free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
}
static const struct imxmmc_platform_data sdhc_pdata __initconst = {

24
arch/arm/mach-imx/mach-pcm037.c
View File

@ -225,8 +225,7 @@ static struct resource smsc911x_resources[] = {
.end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
.end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
@ -371,7 +370,7 @@ static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
gpio_direction_input(SDHC1_GPIO_WP);
#endif
ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"sdhc-detect", data);
if (ret)
@ -391,7 +390,7 @@ err_gpio_free:
static void pcm970_sdhc1_exit(struct device *dev, void *data)
{
free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data);
gpio_free(SDHC1_GPIO_DET);
gpio_free(SDHC1_GPIO_WP);
}
@ -442,10 +441,6 @@ static struct platform_device *devices[] __initdata = {
&pcm037_mt9v022,
};
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static const struct fb_videomode fb_modedb[] = {
{
/* 240x320 @ 60 Hz Sharp */
@ -511,8 +506,7 @@ static struct resource pcm970_sja1000_resources[] = {
.end = MX31_CS5_BASE_ADDR + 0x100 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
.end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
@ -633,6 +627,10 @@ static void __init pcm037_init(void)
pr_warning("could not get LAN irq gpio\n");
else {
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
smsc911x_resources[1].start =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
smsc911x_resources[1].end =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
platform_device_register(&pcm037_eth);
}
@ -646,7 +644,7 @@ static void __init pcm037_init(void)
imx31_add_mxc_nand(&pcm037_nand_board_info);
imx31_add_mxc_mmc(0, &sdhc_pdata);
imx31_add_ipu_core(&mx3_ipu_data);
imx31_add_ipu_core();
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* CSI */
@ -659,6 +657,10 @@ static void __init pcm037_init(void)
pcm037_init_camera();
pcm970_sja1000_resources[1].start =
gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
pcm970_sja1000_resources[1].end =
gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
platform_device_register(&pcm970_sja1000);
if (otg_mode_host) {

4
arch/arm/mach-imx/mach-pcm038.c
View File

@ -27,6 +27,7 @@
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -274,7 +275,7 @@ static struct mc13xxx_platform_data pcm038_pmic = {
static struct spi_board_info pcm038_spi_board_info[] __initdata = {
{
.modalias = "mc13783",
.irq = IRQ_GPIOB(23),
/* irq number is run-time assigned */
.max_speed_hz = 300000,
.bus_num = 0,
.chip_select = 0,
@ -325,6 +326,7 @@ static void __init pcm038_init(void)
mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
imx27_add_spi_imx0(&pcm038_spi0_data);
pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(2, 23));
spi_register_board_info(pcm038_spi_board_info,
ARRAY_SIZE(pcm038_spi_board_info));

6
arch/arm/mach-imx/mach-pcm043.c
View File

@ -76,10 +76,6 @@ static const struct fb_videomode fb_modedb[] = {
},
};
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "Sharp-LQ035Q7",
.mode = fb_modedb,
@ -376,7 +372,7 @@ static void __init pcm043_init(void)
imx35_add_imx_i2c0(&pcm043_i2c0_data);
imx35_add_ipu_core(&mx3_ipu_data);
imx35_add_ipu_core();
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
if (otg_mode_host) {

10
arch/arm/mach-imx/mach-qong.c
View File

@ -22,7 +22,6 @@
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
@ -51,8 +50,6 @@
(QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
#define QONG_DNET_SIZE 0x00001000
#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
@ -78,8 +75,7 @@ static struct resource dnet_resources[] = {
.end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
.flags = IORESOURCE_MEM,
}, {
.start = QONG_FPGA_IRQ,
.end = QONG_FPGA_IRQ,
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ,
},
};
@ -95,6 +91,10 @@ static int __init qong_init_dnet(void)
{
int ret;
dnet_resources[1].start =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
dnet_resources[1].end =
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
ret = platform_device_register(&dnet_device);
return ret;
}

7
arch/arm/mach-imx/mach-scb9328.c
View File

@ -14,6 +14,7 @@
#include <linux/mtd/physmap.h>
#include <linux/interrupt.h>
#include <linux/dm9000.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -21,7 +22,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/iomux-mx1.h>
#include "devices-imx1.h"
@ -78,8 +78,7 @@ static struct resource dm9000x_resources[] = {
.end = MX1_CS5_PHYS + 5,
.flags = IORESOURCE_MEM, /* data access */
}, {
.start = IRQ_GPIOC(3),
.end = IRQ_GPIOC(3),
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
@ -123,6 +122,8 @@ static void __init scb9328_init(void)
imx1_add_imx_uart0(&uart_pdata);
printk(KERN_INFO"Scb9328: Adding devices\n");
dm9000x_resources[2].start = gpio_to_irq(IMX_GPIO_NR(3, 3));
dm9000x_resources[2].end = gpio_to_irq(IMX_GPIO_NR(3, 3));
platform_add_devices(devices, ARRAY_SIZE(devices));
}

10
arch/arm/mach-imx/mach-vpr200.c
View File

@ -31,7 +31,6 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/irqs.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
@ -87,10 +86,6 @@ static const struct fb_videomode fb_modedb[] = {
}
};
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "PT0708048",
.mode = fb_modedb,
@ -162,7 +157,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
}, {
I2C_BOARD_INFO("mc13892", 0x08),
.platform_data = &vpr200_pmic,
.irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
/* irq number is run-time assigned */
}
};
@ -290,7 +285,7 @@ static void __init vpr200_board_init(void)
imx35_add_imx_uart0(NULL);
imx35_add_imx_uart2(NULL);
imx35_add_ipu_core(&mx3_ipu_data);
imx35_add_ipu_core();
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
imx35_add_fsl_usb2_udc(&otg_device_pdata);
@ -299,6 +294,7 @@ static void __init vpr200_board_init(void)
imx35_add_mxc_nand(&vpr200_nand_board_info);
imx35_add_sdhci_esdhc_imx(0, NULL);
vpr200_i2c_devices[1].irq = gpio_to_irq(GPIO_PMIC_INT);
i2c_register_board_info(0, vpr200_i2c_devices,
ARRAY_SIZE(vpr200_i2c_devices));

1
arch/arm/mach-imx/mm-imx1.c
View File

@ -24,7 +24,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/iomux-v1.h>
static struct map_desc imx_io_desc[] __initdata = {

1
arch/arm/mach-imx/mm-imx21.c
View File

@ -26,7 +26,6 @@
#include <mach/devices-common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <mach/irqs.h>
#include <mach/iomux-v1.h>
/* MX21 memory map definition */

1
arch/arm/mach-imx/mm-imx25.c
View File

@ -29,7 +29,6 @@
#include <mach/hardware.h>
#include <mach/mx25.h>
#include <mach/iomux-v3.h>
#include <mach/irqs.h>
/*
* This table defines static virtual address mappings for I/O regions.

1
arch/arm/mach-imx/mm-imx27.c
View File

@ -26,7 +26,6 @@
#include <mach/devices-common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <mach/irqs.h>
#include <mach/iomux-v1.h>
/* MX27 memory map definition */

1
arch/arm/mach-imx/mm-imx3.c
View File

@ -30,7 +30,6 @@
#include <mach/devices-common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/irqs.h>
#include "crmregs-imx3.h"

11
arch/arm/mach-imx/mx31lilly-db.c
View File

@ -130,7 +130,8 @@ static int mxc_mmc1_init(struct device *dev,
gpio_direction_input(gpio_det);
gpio_direction_input(gpio_wp);
ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), detect_irq,
ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)),
detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"MMC detect", data);
if (ret)
@ -151,7 +152,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
{
gpio_free(gpio_det);
gpio_free(gpio_wp);
free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), data);
}
static const struct imxmmc_platform_data mmc_pdata __initconst = {
@ -161,10 +162,6 @@ static const struct imxmmc_platform_data mmc_pdata __initconst = {
};
/* Framebuffer support */
static const struct ipu_platform_data ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static const struct fb_videomode fb_modedb = {
/* 640x480 TFT panel (IPS-056T) */
.name = "CRT-VGA",
@ -198,7 +195,7 @@ static void __init mx31lilly_init_fb(void)
return;
}
imx31_add_ipu_core(&ipu_data);
imx31_add_ipu_core();
imx31_add_mx3_sdc_fb(&fb_pdata);
gpio_direction_output(LCD_VCC_EN_GPIO, 1);
}

5
arch/arm/mach-imx/mx31lite-db.c
View File

@ -116,7 +116,8 @@ static int mxc_mmc1_init(struct device *dev,
gpio_direction_input(gpio_det);
gpio_direction_input(gpio_wp);
ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)),
detect_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC detect", data);
if (ret)
@ -137,7 +138,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
{
gpio_free(gpio_det);
gpio_free(gpio_wp);
free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)), data);
}
static const struct imxmmc_platform_data mmc_pdata __initconst = {

3
arch/arm/mach-imx/mx51_efika.c
View File

@ -587,7 +587,7 @@ static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
.bus_num = 0,
.chip_select = 0,
.platform_data = &mx51_efika_mc13892_data,
.irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
/* irq number is run-time assigned */
},
};
@ -620,6 +620,7 @@ void __init efika_board_common_init(void)
gpio_request(EFIKAMX_PMIC, "pmic irq");
gpio_direction_input(EFIKAMX_PMIC);
mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC);
spi_register_board_info(mx51_efika_spi_board_info,
ARRAY_SIZE(mx51_efika_spi_board_info));
imx51_add_ecspi(0, &mx51_efika_spi_pdata);

13
arch/arm/mach-imx/pcm970-baseboard.c
View File

@ -95,14 +95,14 @@ static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void
{
int ret;
ret = request_irq(IRQ_GPIOC(29), detect_irq, IRQF_TRIGGER_FALLING,
"imx-mmc-detect", data);
ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
if (ret)
return ret;
ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
if (ret) {
free_irq(IRQ_GPIOC(29), data);
free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
return ret;
}
@ -113,7 +113,7 @@ static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void
static void pcm970_sdhc2_exit(struct device *dev, void *data)
{
free_irq(IRQ_GPIOC(29), data);
free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
gpio_free(GPIO_PORTC + 28);
}
@ -192,8 +192,7 @@ static struct resource pcm970_sja1000_resources[] = {
.end = MX27_CS4_BASE_ADDR + 0x100 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_GPIOE(19),
.end = IRQ_GPIOE(19),
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
@ -227,5 +226,7 @@ void __init pcm970_baseboard_init(void)
imx27_add_imx_fb(&pcm038_fb_data);
mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
imx27_add_mxc_mmc(1, &sdhc_pdata);
pcm970_sja1000_resources[1].start = gpio_to_irq(IMX_GPIO_NR(5, 19));
pcm970_sja1000_resources[1].end = gpio_to_irq(IMX_GPIO_NR(5, 19));
platform_device_register(&pcm970_sja1000);
}

2
arch/arm/mach-rpc/irq.c
View File

@ -163,6 +163,6 @@ void __init rpc_init_irq(void)
}
}
init_FIQ();
init_FIQ(FIQ_START);
}

50
arch/arm/plat-mxc/3ds_debugboard.c
View File

@ -12,9 +12,11 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/smsc911x.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
@ -48,27 +50,22 @@
/* CPU ID and Personality ID */
#define MCU_BOARD_ID_REG 0x68
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_BOARD_IRQ_START)
#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_INTERNAL_IRQS)
#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define MXC_MAX_EXP_IO_LINES 16
/* interrupts like external uart , external ethernet etc*/
#define EXPIO_INT_ENET (MXC_BOARD_IRQ_START + 0)
#define EXPIO_INT_XUART_A (MXC_BOARD_IRQ_START + 1)
#define EXPIO_INT_XUART_B (MXC_BOARD_IRQ_START + 2)
#define EXPIO_INT_BUTTON_A (MXC_BOARD_IRQ_START + 3)
#define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4)
#define EXPIO_INT_ENET 0
#define EXPIO_INT_XUART_A 1
#define EXPIO_INT_XUART_B 2
#define EXPIO_INT_BUTTON_A 3
#define EXPIO_INT_BUTTON_B 4
static void __iomem *brd_io;
static struct irq_domain *domain;
static struct resource smsc911x_resources[] = {
{
.flags = IORESOURCE_MEM,
} , {
.start = EXPIO_INT_ENET,
.end = EXPIO_INT_ENET,
.flags = IORESOURCE_IRQ,
},
};
@ -100,11 +97,11 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
imr_val = __raw_readw(brd_io + INTR_MASK_REG);
int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
expio_irq = MXC_BOARD_IRQ_START;
expio_irq = 0;
for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
if ((int_valid & 1) == 0)
continue;
generic_handle_irq(expio_irq);
generic_handle_irq(irq_find_mapping(domain, expio_irq));
}
desc->irq_data.chip->irq_ack(&desc->irq_data);
@ -118,7 +115,7 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
static void expio_mask_irq(struct irq_data *d)
{
u16 reg;
u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
u32 expio = d->hwirq;
reg = __raw_readw(brd_io + INTR_MASK_REG);
reg |= (1 << expio);
@ -127,7 +124,7 @@ static void expio_mask_irq(struct irq_data *d)
static void expio_ack_irq(struct irq_data *d)
{
u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
u32 expio = d->hwirq;
__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
__raw_writew(0, brd_io + INTR_RESET_REG);
@ -137,7 +134,7 @@ static void expio_ack_irq(struct irq_data *d)
static void expio_unmask_irq(struct irq_data *d)
{
u16 reg;
u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
u32 expio = d->hwirq;
reg = __raw_readw(brd_io + INTR_MASK_REG);
reg &= ~(1 << expio);
@ -155,8 +152,10 @@ static struct regulator_consumer_supply dummy_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x"),
};
int __init mxc_expio_init(u32 base, u32 p_irq)
int __init mxc_expio_init(u32 base, u32 intr_gpio)
{
u32 p_irq = gpio_to_irq(intr_gpio);
int irq_base;
int i;
brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
@ -178,16 +177,23 @@ int __init mxc_expio_init(u32 base, u32 p_irq)
/*
* Configure INT line as GPIO input
*/
gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
gpio_request(intr_gpio, "expio_pirq");
gpio_direction_input(intr_gpio);
/* disable the interrupt and clear the status */
__raw_writew(0, brd_io + INTR_MASK_REG);
__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
__raw_writew(0, brd_io + INTR_RESET_REG);
__raw_writew(0x1F, brd_io + INTR_MASK_REG);
for (i = MXC_EXP_IO_BASE;
i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
WARN_ON(irq_base < 0);
domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
&irq_domain_simple_ops, NULL);
WARN_ON(!domain);
for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
@ -199,6 +205,8 @@ int __init mxc_expio_init(u32 base, u32 p_irq)
smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
smsc911x_resources[1].start = irq_find_mapping(domain, EXPIO_INT_ENET);
smsc911x_resources[1].end = irq_find_mapping(domain, EXPIO_INT_ENET);
platform_device_register(&smsc_lan9217_device);
return 0;

35
arch/arm/plat-mxc/avic.c
View File

@ -19,11 +19,14 @@
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
#include <mach/common.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include "irq-common.h"
@ -50,15 +53,19 @@
#define AVIC_NUM_IRQS 64
void __iomem *avic_base;
static struct irq_domain *domain;
static u32 avic_saved_mask_reg[2];
#ifdef CONFIG_MXC_IRQ_PRIOR
static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
{
struct irq_data *d = irq_get_irq_data(irq);
unsigned int temp;
unsigned int mask = 0x0F << irq % 8 * 4;
irq = d->hwirq;
if (irq >= AVIC_NUM_IRQS)
return -EINVAL;
@ -75,8 +82,11 @@ static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
#ifdef CONFIG_FIQ
static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
{
struct irq_data *d = irq_get_irq_data(irq);
unsigned int irqt;
irq = d->hwirq;
if (irq >= AVIC_NUM_IRQS)
return -EINVAL;
@ -108,7 +118,7 @@ static void avic_irq_suspend(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = gc->chip_types;
int idx = gc->irq_base >> 5;
int idx = d->hwirq >> 5;
avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
__raw_writel(gc->wake_active, avic_base + ct->regs.mask);
@ -118,7 +128,7 @@ static void avic_irq_resume(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = gc->chip_types;
int idx = gc->irq_base >> 5;
int idx = d->hwirq >> 5;
__raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
}
@ -128,11 +138,10 @@ static void avic_irq_resume(struct irq_data *d)
#define avic_irq_resume NULL
#endif
static __init void avic_init_gc(unsigned int irq_start)
static __init void avic_init_gc(int idx, unsigned int irq_start)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
int idx = irq_start >> 5;
gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
handle_level_irq);
@ -161,7 +170,7 @@ asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
if (nivector == 0xffff)
break;
handle_IRQ(nivector, regs);
handle_IRQ(irq_find_mapping(domain, nivector), regs);
} while (1);
}
@ -172,6 +181,8 @@ asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
*/
void __init mxc_init_irq(void __iomem *irqbase)
{
struct device_node *np;
int irq_base;
int i;
avic_base = irqbase;
@ -190,8 +201,16 @@ void __init mxc_init_irq(void __iomem *irqbase)
__raw_writel(0, avic_base + AVIC_INTTYPEH);
__raw_writel(0, avic_base + AVIC_INTTYPEL);
for (i = 0; i < AVIC_NUM_IRQS; i += 32)
avic_init_gc(i);
irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
WARN_ON(irq_base < 0);
np = of_find_compatible_node(NULL, NULL, "fsl,avic");
domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
&irq_domain_simple_ops, NULL);
WARN_ON(!domain);
for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
avic_init_gc(i, irq_base);
/* Set default priority value (0) for all IRQ's */
for (i = 0; i < 8; i++)
@ -199,7 +218,7 @@ void __init mxc_init_irq(void __iomem *irqbase)
#ifdef CONFIG_FIQ
/* Initialize FIQ */
init_FIQ();
init_FIQ(FIQ_START);
#endif
printk(KERN_INFO "MXC IRQ initialized\n");

5
arch/arm/plat-mxc/devices/platform-ipu-core.c
View File

@ -30,8 +30,7 @@ const struct imx_ipu_core_data imx35_ipu_core_data __initconst =
static struct platform_device *imx_ipu_coredev __initdata;
struct platform_device *__init imx_add_ipu_core(
const struct imx_ipu_core_data *data,
const struct ipu_platform_data *pdata)
const struct imx_ipu_core_data *data)
{
/* The resource order is important! */
struct resource res[] = {
@ -55,7 +54,7 @@ struct platform_device *__init imx_add_ipu_core(
};
return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1,
res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
res, ARRAY_SIZE(res), NULL, 0);
}
struct platform_device *__init imx_alloc_mx3_camera(

2
arch/arm/plat-mxc/include/mach/3ds_debugboard.h
View File

@ -13,6 +13,6 @@
#ifndef __ASM_ARCH_MXC_3DS_DB_H__
#define __ASM_ARCH_MXC_3DS_DB_H__
extern int __init mxc_expio_init(u32 base, u32 p_irq);
extern int __init mxc_expio_init(u32 base, u32 intr_gpio);
#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */

4
arch/arm/plat-mxc/include/mach/devices-common.h
View File

@ -183,7 +183,6 @@ struct platform_device *__init imx_add_imx_udc(
const struct imx_imx_udc_data *data,
const struct imxusb_platform_data *pdata);
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/mx3_camera.h>
struct imx_ipu_core_data {
@ -192,8 +191,7 @@ struct imx_ipu_core_data {
resource_size_t errirq;
};
struct platform_device *__init imx_add_ipu_core(
const struct imx_ipu_core_data *data,
const struct ipu_platform_data *pdata);
const struct imx_ipu_core_data *data);
struct platform_device *__init imx_alloc_mx3_camera(
const struct imx_ipu_core_data *data,
const struct mx3_camera_pdata *pdata);

2
arch/arm/plat-mxc/include/mach/hardware.h
View File

@ -128,6 +128,4 @@
/* range e.g. GPIO_1_5 is gpio 5 under linux */
#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
#define IMX_GPIO_TO_IRQ(gpio) (MXC_GPIO_IRQ_START + (gpio))
#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */

3
arch/arm/plat-mxc/include/mach/iomux-mx3.h
View File

@ -160,9 +160,6 @@ int mxc_iomux_mode(unsigned int pin_mode);
#define IOMUX_TO_GPIO(iomux_pin) \
((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
#define IOMUX_TO_IRQ(iomux_pin) \
(((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
MXC_GPIO_IRQ_START)
/*
* This enumeration is constructed based on the Section

7
arch/arm/plat-mxc/include/mach/iomux-v1.h
View File

@ -85,13 +85,6 @@
#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x)
extern int mxc_gpio_mode(int gpio_mode);
extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
const char *label);

4
arch/arm/plat-mxc/include/mach/ipu.h
View File

@ -110,10 +110,6 @@ enum ipu_rotate_mode {
IPU_ROTATE_90_LEFT = 7,
};
struct ipu_platform_data {
unsigned int irq_base;
};
/*
* Enumeration of DI ports for ADC.
*/

44
arch/arm/plat-mxc/include/mach/irqs.h
View File

@ -11,50 +11,6 @@
#ifndef __ASM_ARCH_MXC_IRQS_H__
#define __ASM_ARCH_MXC_IRQS_H__
#include <asm-generic/gpio.h>
/*
* SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
* have 128 IRQs, and those with AVIC have 64.
*
* To support single image, the biggest number should be defined on
* top of the list.
*/
#if defined CONFIG_ARM_GIC
#define MXC_INTERNAL_IRQS 160
#elif defined CONFIG_MXC_TZIC
#define MXC_INTERNAL_IRQS 128
#else
#define MXC_INTERNAL_IRQS 64
#endif
#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
/*
* The next 16 interrupts are for board specific purposes. Since
* the kernel can only run on one machine at a time, we can re-use
* these. If you need more, increase MXC_BOARD_IRQS, but keep it
* within sensible limits.
*/
#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS)
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
#define MXC_BOARD_IRQS 80
#else
#define MXC_BOARD_IRQS 16
#endif
#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
#ifdef CONFIG_MX3_IPU_IRQS
#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
#else
#define MX3_IPU_IRQS 0
#endif
/* REVISIT: Add IPU irqs on IMX51 */
#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
/* all normal IRQs can be FIQs */

111
arch/arm/plat-mxc/include/mach/mx1.h
View File

@ -78,61 +78,62 @@
#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
/* fixed interrput numbers */
#define MX1_INT_SOFTINT 0
#define MX1_INT_CSI 6
#define MX1_DSPA_MAC_INT 7
#define MX1_DSPA_INT 8
#define MX1_COMP_INT 9
#define MX1_MSHC_XINT 10
#define MX1_GPIO_INT_PORTA 11
#define MX1_GPIO_INT_PORTB 12
#define MX1_GPIO_INT_PORTC 13
#define MX1_INT_LCDC 14
#define MX1_SIM_INT 15
#define MX1_SIM_DATA_INT 16
#define MX1_RTC_INT 17
#define MX1_RTC_SAMINT 18
#define MX1_INT_UART2PFERR 19
#define MX1_INT_UART2RTS 20
#define MX1_INT_UART2DTR 21
#define MX1_INT_UART2UARTC 22
#define MX1_INT_UART2TX 23
#define MX1_INT_UART2RX 24
#define MX1_INT_UART1PFERR 25
#define MX1_INT_UART1RTS 26
#define MX1_INT_UART1DTR 27
#define MX1_INT_UART1UARTC 28
#define MX1_INT_UART1TX 29
#define MX1_INT_UART1RX 30
#define MX1_VOICE_DAC_INT 31
#define MX1_VOICE_ADC_INT 32
#define MX1_PEN_DATA_INT 33
#define MX1_PWM_INT 34
#define MX1_SDHC_INT 35
#define MX1_INT_I2C 39
#define MX1_INT_CSPI2 40
#define MX1_INT_CSPI1 41
#define MX1_SSI_TX_INT 42
#define MX1_SSI_TX_ERR_INT 43
#define MX1_SSI_RX_INT 44
#define MX1_SSI_RX_ERR_INT 45
#define MX1_TOUCH_INT 46
#define MX1_INT_USBD0 47
#define MX1_INT_USBD1 48
#define MX1_INT_USBD2 49
#define MX1_INT_USBD3 50
#define MX1_INT_USBD4 51
#define MX1_INT_USBD5 52
#define MX1_INT_USBD6 53
#define MX1_BTSYS_INT 55
#define MX1_BTTIM_INT 56
#define MX1_BTWUI_INT 57
#define MX1_TIM2_INT 58
#define MX1_TIM1_INT 59
#define MX1_DMA_ERR 60
#define MX1_DMA_INT 61
#define MX1_GPIO_INT_PORTD 62
#define MX1_WDT_INT 63
#include <asm/irq.h>
#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)
#define MX1_INT_CSI (NR_IRQS_LEGACY + 6)
#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)
#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)
#define MX1_COMP_INT (NR_IRQS_LEGACY + 9)
#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)
#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)
#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)
#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)
#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)
#define MX1_SIM_INT (NR_IRQS_LEGACY + 15)
#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16)
#define MX1_RTC_INT (NR_IRQS_LEGACY + 17)
#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18)
#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19)
#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20)
#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21)
#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22)
#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23)
#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24)
#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25)
#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26)
#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27)
#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28)
#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29)
#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30)
#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31)
#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32)
#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33)
#define MX1_PWM_INT (NR_IRQS_LEGACY + 34)
#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35)
#define MX1_INT_I2C (NR_IRQS_LEGACY + 39)
#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40)
#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41)
#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42)
#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43)
#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44)
#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45)
#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46)
#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47)
#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48)
#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49)
#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50)
#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51)
#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52)
#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53)
#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55)
#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56)
#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57)
#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58)
#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60)
#define MX1_DMA_INT (NR_IRQS_LEGACY + 61)
#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62)
#define MX1_WDT_INT (NR_IRQS_LEGACY + 63)
/* DMA */
#define MX1_DMA_REQ_UART3_T 2

107
arch/arm/plat-mxc/include/mach/mx21.h
View File

@ -99,59 +99,60 @@
#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
/* fixed interrupt numbers */
#define MX21_INT_CSPI3 6
#define MX21_INT_GPIO 8
#define MX21_INT_FIRI 9
#define MX21_INT_SDHC2 10
#define MX21_INT_SDHC1 11
#define MX21_INT_I2C 12
#define MX21_INT_SSI2 13
#define MX21_INT_SSI1 14
#define MX21_INT_CSPI2 15
#define MX21_INT_CSPI1 16
#define MX21_INT_UART4 17
#define MX21_INT_UART3 18
#define MX21_INT_UART2 19
#define MX21_INT_UART1 20
#define MX21_INT_KPP 21
#define MX21_INT_RTC 22
#define MX21_INT_PWM 23
#define MX21_INT_GPT3 24
#define MX21_INT_GPT2 25
#define MX21_INT_GPT1 26
#define MX21_INT_WDOG 27
#define MX21_INT_PCMCIA 28
#define MX21_INT_NFC 29
#define MX21_INT_BMI 30
#define MX21_INT_CSI 31
#define MX21_INT_DMACH0 32
#define MX21_INT_DMACH1 33
#define MX21_INT_DMACH2 34
#define MX21_INT_DMACH3 35
#define MX21_INT_DMACH4 36
#define MX21_INT_DMACH5 37
#define MX21_INT_DMACH6 38
#define MX21_INT_DMACH7 39
#define MX21_INT_DMACH8 40
#define MX21_INT_DMACH9 41
#define MX21_INT_DMACH10 42
#define MX21_INT_DMACH11 43
#define MX21_INT_DMACH12 44
#define MX21_INT_DMACH13 45
#define MX21_INT_DMACH14 46
#define MX21_INT_DMACH15 47
#define MX21_INT_EMMAENC 49
#define MX21_INT_EMMADEC 50
#define MX21_INT_EMMAPRP 51
#define MX21_INT_EMMAPP 52
#define MX21_INT_USBWKUP 53
#define MX21_INT_USBDMA 54
#define MX21_INT_USBHOST 55
#define MX21_INT_USBFUNC 56
#define MX21_INT_USBMNP 57
#define MX21_INT_USBCTRL 58
#define MX21_INT_SLCDC 60
#define MX21_INT_LCDC 61
#include <asm/irq.h>
#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6)
#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8)
#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9)
#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10)
#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11)
#define MX21_INT_I2C (NR_IRQS_LEGACY + 12)
#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13)
#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14)
#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15)
#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16)
#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17)
#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18)
#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19)
#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20)
#define MX21_INT_KPP (NR_IRQS_LEGACY + 21)
#define MX21_INT_RTC (NR_IRQS_LEGACY + 22)
#define MX21_INT_PWM (NR_IRQS_LEGACY + 23)
#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24)
#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25)
#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27)
#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28)
#define MX21_INT_NFC (NR_IRQS_LEGACY + 29)
#define MX21_INT_BMI (NR_IRQS_LEGACY + 30)
#define MX21_INT_CSI (NR_IRQS_LEGACY + 31)
#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32)
#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33)
#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34)
#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35)
#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36)
#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37)
#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38)
#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39)
#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40)
#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41)
#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42)
#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43)
#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44)
#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45)
#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46)
#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47)
#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49)
#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50)
#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52)
#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53)
#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54)
#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55)
#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56)
#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57)
#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58)
#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60)
#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61)
/* fixed DMA request numbers */
#define MX21_DMA_REQ_CSPI3_RX 1

72
arch/arm/plat-mxc/include/mach/mx25.h
View File

@ -61,40 +61,44 @@
#define MX25_IO_P2V(x) IMX_IO_P2V(x)
#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
#define MX25_INT_CSPI3 0
#define MX25_INT_I2C1 3
#define MX25_INT_I2C2 4
#define MX25_INT_UART4 5
#define MX25_INT_ESDHC2 8
#define MX25_INT_ESDHC1 9
#define MX25_INT_I2C3 10
#define MX25_INT_SSI2 11
#define MX25_INT_SSI1 12
#define MX25_INT_CSPI2 13
#define MX25_INT_CSPI1 14
#define MX25_INT_GPIO3 16
#define MX25_INT_CSI 17
#define MX25_INT_UART3 18
#define MX25_INT_GPIO4 23
#define MX25_INT_KPP 24
#define MX25_INT_DRYICE 25
#define MX25_INT_PWM1 26
#define MX25_INT_UART2 32
#define MX25_INT_NFC 33
#define MX25_INT_SDMA 34
#define MX25_INT_USB_HS 35
#define MX25_INT_PWM2 36
#define MX25_INT_USB_OTG 37
#define MX25_INT_LCDC 39
#define MX25_INT_UART5 40
#define MX25_INT_PWM3 41
#define MX25_INT_PWM4 42
#define MX25_INT_CAN1 43
#define MX25_INT_CAN2 44
#define MX25_INT_UART1 45
#define MX25_INT_GPIO2 51
#define MX25_INT_GPIO1 52
#define MX25_INT_FEC 57
/*
* Interrupt numbers
*/
#include <asm/irq.h>
#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0)
#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3)
#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4)
#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5)
#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9)
#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10)
#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11)
#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12)
#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13)
#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14)
#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16)
#define MX25_INT_CSI (NR_IRQS_LEGACY + 17)
#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18)
#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23)
#define MX25_INT_KPP (NR_IRQS_LEGACY + 24)
#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25)
#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26)
#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32)
#define MX25_INT_NFC (NR_IRQS_LEGACY + 33)
#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34)
#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35)
#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36)
#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37)
#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39)
#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40)
#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41)
#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42)
#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43)
#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44)
#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
#define MX25_DMA_REQ_SSI2_RX1 22
#define MX25_DMA_REQ_SSI2_TX1 23

127
arch/arm/plat-mxc/include/mach/mx27.h
View File

@ -128,69 +128,70 @@
#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
/* fixed interrupt numbers */
#define MX27_INT_I2C2 1
#define MX27_INT_GPT6 2
#define MX27_INT_GPT5 3
#define MX27_INT_GPT4 4
#define MX27_INT_RTIC 5
#define MX27_INT_CSPI3 6
#define MX27_INT_SDHC 7
#define MX27_INT_GPIO 8
#define MX27_INT_SDHC3 9
#define MX27_INT_SDHC2 10
#define MX27_INT_SDHC1 11
#define MX27_INT_I2C1 12
#define MX27_INT_SSI2 13
#define MX27_INT_SSI1 14
#define MX27_INT_CSPI2 15
#define MX27_INT_CSPI1 16
#define MX27_INT_UART4 17
#define MX27_INT_UART3 18
#define MX27_INT_UART2 19
#define MX27_INT_UART1 20
#define MX27_INT_KPP 21
#define MX27_INT_RTC 22
#define MX27_INT_PWM 23
#define MX27_INT_GPT3 24
#define MX27_INT_GPT2 25
#define MX27_INT_GPT1 26
#define MX27_INT_WDOG 27
#define MX27_INT_PCMCIA 28
#define MX27_INT_NFC 29
#define MX27_INT_ATA 30
#define MX27_INT_CSI 31
#define MX27_INT_DMACH0 32
#define MX27_INT_DMACH1 33
#define MX27_INT_DMACH2 34
#define MX27_INT_DMACH3 35
#define MX27_INT_DMACH4 36
#define MX27_INT_DMACH5 37
#define MX27_INT_DMACH6 38
#define MX27_INT_DMACH7 39
#define MX27_INT_DMACH8 40
#define MX27_INT_DMACH9 41
#define MX27_INT_DMACH10 42
#define MX27_INT_DMACH11 43
#define MX27_INT_DMACH12 44
#define MX27_INT_DMACH13 45
#define MX27_INT_DMACH14 46
#define MX27_INT_DMACH15 47
#define MX27_INT_UART6 48
#define MX27_INT_UART5 49
#define MX27_INT_FEC 50
#define MX27_INT_EMMAPRP 51
#define MX27_INT_EMMAPP 52
#define MX27_INT_VPU 53
#define MX27_INT_USB_HS1 54
#define MX27_INT_USB_HS2 55
#define MX27_INT_USB_OTG 56
#define MX27_INT_SCC_SMN 57
#define MX27_INT_SCC_SCM 58
#define MX27_INT_SAHARA 59
#define MX27_INT_SLCDC 60
#define MX27_INT_LCDC 61
#define MX27_INT_IIM 62
#define MX27_INT_CCM 63
#include <asm/irq.h>
#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)
#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)
#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)
#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7)
#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11)
#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12)
#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13)
#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14)
#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15)
#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16)
#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17)
#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18)
#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19)
#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20)
#define MX27_INT_KPP (NR_IRQS_LEGACY + 21)
#define MX27_INT_RTC (NR_IRQS_LEGACY + 22)
#define MX27_INT_PWM (NR_IRQS_LEGACY + 23)
#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24)
#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25)
#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27)
#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28)
#define MX27_INT_NFC (NR_IRQS_LEGACY + 29)
#define MX27_INT_ATA (NR_IRQS_LEGACY + 30)
#define MX27_INT_CSI (NR_IRQS_LEGACY + 31)
#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32)
#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33)
#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34)
#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35)
#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36)
#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37)
#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38)
#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39)
#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40)
#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41)
#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42)
#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43)
#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44)
#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45)
#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46)
#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47)
#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48)
#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49)
#define MX27_INT_FEC (NR_IRQS_LEGACY + 50)
#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52)
#define MX27_INT_VPU (NR_IRQS_LEGACY + 53)
#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54)
#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55)
#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56)
#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57)
#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58)
#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59)
#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60)
#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61)
#define MX27_INT_IIM (NR_IRQS_LEGACY + 62)
#define MX27_INT_CCM (NR_IRQS_LEGACY + 63)
/* fixed DMA request numbers */
#define MX27_DMA_REQ_CSPI3_RX 1

87
arch/arm/plat-mxc/include/mach/mx2x.h
View File

@ -68,49 +68,50 @@
#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
/* fixed interrupt numbers */
#define MX2x_INT_CSPI3 6
#define MX2x_INT_GPIO 8
#define MX2x_INT_SDHC2 10
#define MX2x_INT_SDHC1 11
#define MX2x_INT_I2C 12
#define MX2x_INT_SSI2 13
#define MX2x_INT_SSI1 14
#define MX2x_INT_CSPI2 15
#define MX2x_INT_CSPI1 16
#define MX2x_INT_UART4 17
#define MX2x_INT_UART3 18
#define MX2x_INT_UART2 19
#define MX2x_INT_UART1 20
#define MX2x_INT_KPP 21
#define MX2x_INT_RTC 22
#define MX2x_INT_PWM 23
#define MX2x_INT_GPT3 24
#define MX2x_INT_GPT2 25
#define MX2x_INT_GPT1 26
#define MX2x_INT_WDOG 27
#define MX2x_INT_PCMCIA 28
#define MX2x_INT_NANDFC 29
#define MX2x_INT_CSI 31
#define MX2x_INT_DMACH0 32
#define MX2x_INT_DMACH1 33
#define MX2x_INT_DMACH2 34
#define MX2x_INT_DMACH3 35
#define MX2x_INT_DMACH4 36
#define MX2x_INT_DMACH5 37
#define MX2x_INT_DMACH6 38
#define MX2x_INT_DMACH7 39
#define MX2x_INT_DMACH8 40
#define MX2x_INT_DMACH9 41
#define MX2x_INT_DMACH10 42
#define MX2x_INT_DMACH11 43
#define MX2x_INT_DMACH12 44
#define MX2x_INT_DMACH13 45
#define MX2x_INT_DMACH14 46
#define MX2x_INT_DMACH15 47
#define MX2x_INT_EMMAPRP 51
#define MX2x_INT_EMMAPP 52
#define MX2x_INT_SLCDC 60
#define MX2x_INT_LCDC 61
#include <asm/irq.h>
#define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)
#define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)
#define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)
#define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)
#define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)
#define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)
#define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)
#define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)
#define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)
#define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)
#define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18)
#define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19)
#define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20)
#define MX2x_INT_KPP (NR_IRQS_LEGACY + 21)
#define MX2x_INT_RTC (NR_IRQS_LEGACY + 22)
#define MX2x_INT_PWM (NR_IRQS_LEGACY + 23)
#define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24)
#define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25)
#define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26)
#define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27)
#define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28)
#define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29)
#define MX2x_INT_CSI (NR_IRQS_LEGACY + 31)
#define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32)
#define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33)
#define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34)
#define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35)
#define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36)
#define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37)
#define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38)
#define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39)
#define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40)
#define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41)
#define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42)
#define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43)
#define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44)
#define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45)
#define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46)
#define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47)
#define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
#define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52)
#define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60)
#define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61)
/* fixed DMA request numbers */
#define MX2x_DMA_REQ_CSPI3_RX 1

118
arch/arm/plat-mxc/include/mach/mx31.h
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@ -118,63 +118,67 @@
#define MX31_IO_P2V(x) IMX_IO_P2V(x)
#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
#define MX31_INT_I2C3 3
#define MX31_INT_I2C2 4
#define MX31_INT_MPEG4_ENCODER 5
#define MX31_INT_RTIC 6
#define MX31_INT_FIRI 7
#define MX31_INT_SDHC2 8
#define MX31_INT_SDHC1 9
#define MX31_INT_I2C1 10
#define MX31_INT_SSI2 11
#define MX31_INT_SSI1 12
#define MX31_INT_CSPI2 13
#define MX31_INT_CSPI1 14
#define MX31_INT_ATA 15
#define MX31_INT_MBX 16
#define MX31_INT_CSPI3 17
#define MX31_INT_UART3 18
#define MX31_INT_IIM 19
#define MX31_INT_SIM2 20
#define MX31_INT_SIM1 21
#define MX31_INT_RNGA 22
#define MX31_INT_EVTMON 23
#define MX31_INT_KPP 24
#define MX31_INT_RTC 25
#define MX31_INT_PWM 26
#define MX31_INT_EPIT2 27
#define MX31_INT_EPIT1 28
#define MX31_INT_GPT 29
#define MX31_INT_POWER_FAIL 30
#define MX31_INT_CCM_DVFS 31
#define MX31_INT_UART2 32
#define MX31_INT_NFC 33
#define MX31_INT_SDMA 34
#define MX31_INT_USB_HS1 35
#define MX31_INT_USB_HS2 36
#define MX31_INT_USB_OTG 37
#define MX31_INT_MSHC1 39
#define MX31_INT_MSHC2 40
#define MX31_INT_IPU_ERR 41
#define MX31_INT_IPU_SYN 42
#define MX31_INT_UART1 45
#define MX31_INT_UART4 46
#define MX31_INT_UART5 47
#define MX31_INT_ECT 48
#define MX31_INT_SCC_SCM 49
#define MX31_INT_SCC_SMN 50
#define MX31_INT_GPIO2 51
#define MX31_INT_GPIO1 52
#define MX31_INT_CCM 53
#define MX31_INT_PCMCIA 54
#define MX31_INT_WDOG 55
#define MX31_INT_GPIO3 56
#define MX31_INT_EXT_POWER 58
#define MX31_INT_EXT_TEMPER 59
#define MX31_INT_EXT_SENSOR60 60
#define MX31_INT_EXT_SENSOR61 61
#define MX31_INT_EXT_WDOG 62
#define MX31_INT_EXT_TV 63
/*
* Interrupt numbers
*/
#include <asm/irq.h>
#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)
#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)
#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)
#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)
#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)
#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)
#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)
#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)
#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)
#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)
#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13)
#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14)
#define MX31_INT_ATA (NR_IRQS_LEGACY + 15)
#define MX31_INT_MBX (NR_IRQS_LEGACY + 16)
#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17)
#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18)
#define MX31_INT_IIM (NR_IRQS_LEGACY + 19)
#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20)
#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21)
#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22)
#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23)
#define MX31_INT_KPP (NR_IRQS_LEGACY + 24)
#define MX31_INT_RTC (NR_IRQS_LEGACY + 25)
#define MX31_INT_PWM (NR_IRQS_LEGACY + 26)
#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27)
#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28)
#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31)
#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32)
#define MX31_INT_NFC (NR_IRQS_LEGACY + 33)
#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34)
#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35)
#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36)
#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37)
#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39)
#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40)
#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45)
#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46)
#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47)
#define MX31_INT_ECT (NR_IRQS_LEGACY + 48)
#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51)
#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52)
#define MX31_INT_CCM (NR_IRQS_LEGACY + 53)
#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54)
#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55)
#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56)
#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63)
#define MX31_DMA_REQ_SDHC1 20
#define MX31_DMA_REQ_SDHC2 21

109
arch/arm/plat-mxc/include/mach/mx35.h
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@ -120,60 +120,61 @@
/*
* Interrupt numbers
*/
#define MX35_INT_OWIRE 2
#define MX35_INT_I2C3 3
#define MX35_INT_I2C2 4
#define MX35_INT_RTIC 6
#define MX35_INT_ESDHC1 7
#define MX35_INT_ESDHC2 8
#define MX35_INT_ESDHC3 9
#define MX35_INT_I2C1 10
#define MX35_INT_SSI1 11
#define MX35_INT_SSI2 12
#define MX35_INT_CSPI2 13
#define MX35_INT_CSPI1 14
#define MX35_INT_ATA 15
#define MX35_INT_GPU2D 16
#define MX35_INT_ASRC 17
#define MX35_INT_UART3 18
#define MX35_INT_IIM 19
#define MX35_INT_RNGA 22
#define MX35_INT_EVTMON 23
#define MX35_INT_KPP 24
#define MX35_INT_RTC 25
#define MX35_INT_PWM 26
#define MX35_INT_EPIT2 27
#define MX35_INT_EPIT1 28
#define MX35_INT_GPT 29
#define MX35_INT_POWER_FAIL 30
#define MX35_INT_UART2 32
#define MX35_INT_NFC 33
#define MX35_INT_SDMA 34
#define MX35_INT_USB_HS 35
#define MX35_INT_USB_OTG 37
#define MX35_INT_MSHC1 39
#define MX35_INT_ESAI 40
#define MX35_INT_IPU_ERR 41
#define MX35_INT_IPU_SYN 42
#define MX35_INT_CAN1 43
#define MX35_INT_CAN2 44
#define MX35_INT_UART1 45
#define MX35_INT_MLB 46
#define MX35_INT_SPDIF 47
#define MX35_INT_ECT 48
#define MX35_INT_SCC_SCM 49
#define MX35_INT_SCC_SMN 50
#define MX35_INT_GPIO2 51
#define MX35_INT_GPIO1 52
#define MX35_INT_WDOG 55
#define MX35_INT_GPIO3 56
#define MX35_INT_FEC 57
#define MX35_INT_EXT_POWER 58
#define MX35_INT_EXT_TEMPER 59
#define MX35_INT_EXT_SENSOR60 60
#define MX35_INT_EXT_SENSOR61 61
#define MX35_INT_EXT_WDOG 62
#define MX35_INT_EXT_TV 63
#include <asm/irq.h>
#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)
#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)
#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)
#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)
#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)
#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)
#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)
#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)
#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)
#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13)
#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14)
#define MX35_INT_ATA (NR_IRQS_LEGACY + 15)
#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16)
#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17)
#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18)
#define MX35_INT_IIM (NR_IRQS_LEGACY + 19)
#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22)
#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23)
#define MX35_INT_KPP (NR_IRQS_LEGACY + 24)
#define MX35_INT_RTC (NR_IRQS_LEGACY + 25)
#define MX35_INT_PWM (NR_IRQS_LEGACY + 26)
#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27)
#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28)
#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32)
#define MX35_INT_NFC (NR_IRQS_LEGACY + 33)
#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34)
#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35)
#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37)
#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39)
#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40)
#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43)
#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44)
#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45)
#define MX35_INT_MLB (NR_IRQS_LEGACY + 46)
#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47)
#define MX35_INT_ECT (NR_IRQS_LEGACY + 48)
#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51)
#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52)
#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55)
#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56)
#define MX35_INT_FEC (NR_IRQS_LEGACY + 57)
#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63)
#define MX35_DMA_REQ_SSI2_RX1 22
#define MX35_DMA_REQ_SSI2_TX1 23

77
arch/arm/plat-mxc/include/mach/mx3x.h
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@ -143,44 +143,45 @@
/*
* Interrupt numbers
*/
#define MX3x_INT_I2C3 3
#define MX3x_INT_I2C2 4
#define MX3x_INT_RTIC 6
#define MX3x_INT_I2C 10
#define MX3x_INT_CSPI2 13
#define MX3x_INT_CSPI1 14
#define MX3x_INT_ATA 15
#define MX3x_INT_UART3 18
#define MX3x_INT_IIM 19
#define MX3x_INT_RNGA 22
#define MX3x_INT_EVTMON 23
#define MX3x_INT_KPP 24
#define MX3x_INT_RTC 25
#define MX3x_INT_PWM 26
#define MX3x_INT_EPIT2 27
#define MX3x_INT_EPIT1 28
#define MX3x_INT_GPT 29
#define MX3x_INT_POWER_FAIL 30
#define MX3x_INT_UART2 32
#define MX3x_INT_NANDFC 33
#define MX3x_INT_SDMA 34
#define MX3x_INT_MSHC1 39
#define MX3x_INT_IPU_ERR 41
#define MX3x_INT_IPU_SYN 42
#define MX3x_INT_UART1 45
#define MX3x_INT_ECT 48
#define MX3x_INT_SCC_SCM 49
#define MX3x_INT_SCC_SMN 50
#define MX3x_INT_GPIO2 51
#define MX3x_INT_GPIO1 52
#define MX3x_INT_WDOG 55
#define MX3x_INT_GPIO3 56
#define MX3x_INT_EXT_POWER 58
#define MX3x_INT_EXT_TEMPER 59
#define MX3x_INT_EXT_SENSOR60 60
#define MX3x_INT_EXT_SENSOR61 61
#define MX3x_INT_EXT_WDOG 62
#define MX3x_INT_EXT_TV 63
#include <asm/irq.h>
#define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3)
#define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4)
#define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6)
#define MX3x_INT_I2C (NR_IRQS_LEGACY + 10)
#define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13)
#define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14)
#define MX3x_INT_ATA (NR_IRQS_LEGACY + 15)
#define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18)
#define MX3x_INT_IIM (NR_IRQS_LEGACY + 19)
#define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22)
#define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23)
#define MX3x_INT_KPP (NR_IRQS_LEGACY + 24)
#define MX3x_INT_RTC (NR_IRQS_LEGACY + 25)
#define MX3x_INT_PWM (NR_IRQS_LEGACY + 26)
#define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27)
#define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28)
#define MX3x_INT_GPT (NR_IRQS_LEGACY + 29)
#define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
#define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32)
#define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33)
#define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34)
#define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39)
#define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
#define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
#define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45)
#define MX3x_INT_ECT (NR_IRQS_LEGACY + 48)
#define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
#define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
#define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51)
#define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52)
#define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55)
#define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56)
#define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
#define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
#define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
#define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
#define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
#define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63)
#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */

187
arch/arm/plat-mxc/include/mach/mx50.h
View File

@ -188,99 +188,100 @@
/*
* Interrupt numbers
*/
#define MX50_INT_MMC_SDHC1 1
#define MX50_INT_MMC_SDHC2 2
#define MX50_INT_MMC_SDHC3 3
#define MX50_INT_MMC_SDHC4 4
#define MX50_INT_DAP 5
#define MX50_INT_SDMA 6
#define MX50_INT_IOMUX 7
#define MX50_INT_UART4 13
#define MX50_INT_USB_H1 14
#define MX50_INT_USB_OTG 18
#define MX50_INT_DATABAHN 19
#define MX50_INT_ELCDIF 20
#define MX50_INT_EPXP 21
#define MX50_INT_SRTC_NTZ 24
#define MX50_INT_SRTC_TZ 25
#define MX50_INT_EPDC 27
#define MX50_INT_NIC 28
#define MX50_INT_SSI1 29
#define MX50_INT_SSI2 30
#define MX50_INT_UART1 31
#define MX50_INT_UART2 32
#define MX50_INT_UART3 33
#define MX50_INT_RESV34 34
#define MX50_INT_RESV35 35
#define MX50_INT_CSPI1 36
#define MX50_INT_CSPI2 37
#define MX50_INT_CSPI 38
#define MX50_INT_GPT 39
#define MX50_INT_EPIT1 40
#define MX50_INT_GPIO1_INT7 42
#define MX50_INT_GPIO1_INT6 43
#define MX50_INT_GPIO1_INT5 44
#define MX50_INT_GPIO1_INT4 45
#define MX50_INT_GPIO1_INT3 46
#define MX50_INT_GPIO1_INT2 47
#define MX50_INT_GPIO1_INT1 48
#define MX50_INT_GPIO1_INT0 49
#define MX50_INT_GPIO1_LOW 50
#define MX50_INT_GPIO1_HIGH 51
#define MX50_INT_GPIO2_LOW 52
#define MX50_INT_GPIO2_HIGH 53
#define MX50_INT_GPIO3_LOW 54
#define MX50_INT_GPIO3_HIGH 55
#define MX50_INT_GPIO4_LOW 56
#define MX50_INT_GPIO4_HIGH 57
#define MX50_INT_WDOG1 58
#define MX50_INT_KPP 60
#define MX50_INT_PWM1 61
#define MX50_INT_I2C1 62
#define MX50_INT_I2C2 63
#define MX50_INT_I2C3 64
#define MX50_INT_RESV65 65
#define MX50_INT_DCDC 66
#define MX50_INT_THERMAL_ALARM 67
#define MX50_INT_ANA3 68
#define MX50_INT_ANA4 69
#define MX50_INT_CCM1 71
#define MX50_INT_CCM2 72
#define MX50_INT_GPC1 73
#define MX50_INT_GPC2 74
#define MX50_INT_SRC 75
#define MX50_INT_NM 76
#define MX50_INT_PMU 77
#define MX50_INT_CTI_IRQ 78
#define MX50_INT_CTI1_TG0 79
#define MX50_INT_CTI1_TG1 80
#define MX50_INT_GPU2_IRQ 84
#define MX50_INT_GPU2_BUSY 85
#define MX50_INT_UART5 86
#define MX50_INT_FEC 87
#define MX50_INT_OWIRE 88
#define MX50_INT_CTI1_TG2 89
#define MX50_INT_SJC 90
#define MX50_INT_DCP_CHAN1_3 91
#define MX50_INT_DCP_CHAN0 92
#define MX50_INT_PWM2 94
#define MX50_INT_RNGB 97
#define MX50_INT_CTI1_TG3 98
#define MX50_INT_RAWNAND_BCH 100
#define MX50_INT_RAWNAND_GPMI 102
#define MX50_INT_GPIO5_LOW 103
#define MX50_INT_GPIO5_HIGH 104
#define MX50_INT_GPIO6_LOW 105
#define MX50_INT_GPIO6_HIGH 106
#define MX50_INT_MSHC 109
#define MX50_INT_APBHDMA_CHAN0 110
#define MX50_INT_APBHDMA_CHAN1 111
#define MX50_INT_APBHDMA_CHAN2 112
#define MX50_INT_APBHDMA_CHAN3 113
#define MX50_INT_APBHDMA_CHAN4 114
#define MX50_INT_APBHDMA_CHAN5 115
#define MX50_INT_APBHDMA_CHAN6 116
#define MX50_INT_APBHDMA_CHAN7 117
#include <asm/irq.h>
#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1)
#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2)
#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3)
#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4)
#define MX50_INT_DAP (NR_IRQS_LEGACY + 5)
#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6)
#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7)
#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13)
#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14)
#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18)
#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19)
#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20)
#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21)
#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27)
#define MX50_INT_NIC (NR_IRQS_LEGACY + 28)
#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29)
#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30)
#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31)
#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32)
#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33)
#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34)
#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35)
#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36)
#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37)
#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38)
#define MX50_INT_GPT (NR_IRQS_LEGACY + 39)
#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40)
#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58)
#define MX50_INT_KPP (NR_IRQS_LEGACY + 60)
#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61)
#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62)
#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63)
#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64)
#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65)
#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66)
#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67)
#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68)
#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69)
#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71)
#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72)
#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73)
#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74)
#define MX50_INT_SRC (NR_IRQS_LEGACY + 75)
#define MX50_INT_NM (NR_IRQS_LEGACY + 76)
#define MX50_INT_PMU (NR_IRQS_LEGACY + 77)
#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86)
#define MX50_INT_FEC (NR_IRQS_LEGACY + 87)
#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88)
#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
#define MX50_INT_SJC (NR_IRQS_LEGACY + 90)
#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91)
#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92)
#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94)
#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97)
#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100)
#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102)
#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109)
#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110)
#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111)
#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112)
#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113)
#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114)
#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115)
#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116)
#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117)
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern int mx50_revision(void);

209
arch/arm/plat-mxc/include/mach/mx51.h
View File

@ -232,110 +232,111 @@
/*
* Interrupt numbers
*/
#define MX51_INT_BASE 0
#define MX51_INT_RESV0 0
#define MX51_INT_ESDHC1 1
#define MX51_INT_ESDHC2 2
#define MX51_INT_ESDHC3 3
#define MX51_INT_ESDHC4 4
#define MX51_INT_RESV5 5
#define MX51_INT_SDMA 6
#define MX51_INT_IOMUX 7
#define MX51_INT_NFC 8
#define MX51_INT_VPU 9
#define MX51_INT_IPU_ERR 10
#define MX51_INT_IPU_SYN 11
#define MX51_INT_GPU 12
#define MX51_INT_RESV13 13
#define MX51_INT_USB_HS1 14
#define MX51_INT_EMI 15
#define MX51_INT_USB_HS2 16
#define MX51_INT_USB_HS3 17
#define MX51_INT_USB_OTG 18
#define MX51_INT_SAHARA_H0 19
#define MX51_INT_SAHARA_H1 20
#define MX51_INT_SCC_SMN 21
#define MX51_INT_SCC_STZ 22
#define MX51_INT_SCC_SCM 23
#define MX51_INT_SRTC_NTZ 24
#define MX51_INT_SRTC_TZ 25
#define MX51_INT_RTIC 26
#define MX51_INT_CSU 27
#define MX51_INT_SLIM_B 28
#define MX51_INT_SSI1 29
#define MX51_INT_SSI2 30
#define MX51_INT_UART1 31
#define MX51_INT_UART2 32
#define MX51_INT_UART3 33
#define MX51_INT_RESV34 34
#define MX51_INT_RESV35 35
#define MX51_INT_ECSPI1 36
#define MX51_INT_ECSPI2 37
#define MX51_INT_CSPI 38
#define MX51_INT_GPT 39
#define MX51_INT_EPIT1 40
#define MX51_INT_EPIT2 41
#define MX51_INT_GPIO1_INT7 42
#define MX51_INT_GPIO1_INT6 43
#define MX51_INT_GPIO1_INT5 44
#define MX51_INT_GPIO1_INT4 45
#define MX51_INT_GPIO1_INT3 46
#define MX51_INT_GPIO1_INT2 47
#define MX51_INT_GPIO1_INT1 48
#define MX51_INT_GPIO1_INT0 49
#define MX51_INT_GPIO1_LOW 50
#define MX51_INT_GPIO1_HIGH 51
#define MX51_INT_GPIO2_LOW 52
#define MX51_INT_GPIO2_HIGH 53
#define MX51_INT_GPIO3_LOW 54
#define MX51_INT_GPIO3_HIGH 55
#define MX51_INT_GPIO4_LOW 56
#define MX51_INT_GPIO4_HIGH 57
#define MX51_INT_WDOG1 58
#define MX51_INT_WDOG2 59
#define MX51_INT_KPP 60
#define MX51_INT_PWM1 61
#define MX51_INT_I2C1 62
#define MX51_INT_I2C2 63
#define MX51_INT_HS_I2C 64
#define MX51_INT_RESV65 65
#define MX51_INT_RESV66 66
#define MX51_INT_SIM_IPB 67
#define MX51_INT_SIM_DAT 68
#define MX51_INT_IIM 69
#define MX51_INT_ATA 70
#define MX51_INT_CCM1 71
#define MX51_INT_CCM2 72
#define MX51_INT_GPC1 73
#define MX51_INT_GPC2 74
#define MX51_INT_SRC 75
#define MX51_INT_NM 76
#define MX51_INT_PMU 77
#define MX51_INT_CTI_IRQ 78
#define MX51_INT_CTI1_TG0 79
#define MX51_INT_CTI1_TG1 80
#define MX51_INT_MCG_ERR 81
#define MX51_INT_MCG_TMR 82
#define MX51_INT_MCG_FUNC 83
#define MX51_INT_GPU2_IRQ 84
#define MX51_INT_GPU2_BUSY 85
#define MX51_INT_RESV86 86
#define MX51_INT_FEC 87
#define MX51_INT_OWIRE 88
#define MX51_INT_CTI1_TG2 89
#define MX51_INT_SJC 90
#define MX51_INT_SPDIF 91
#define MX51_INT_TVE 92
#define MX51_INT_FIRI 93
#define MX51_INT_PWM2 94
#define MX51_INT_SLIM_EXP 95
#define MX51_INT_SSI3 96
#define MX51_INT_EMI_BOOT 97
#define MX51_INT_CTI1_TG3 98
#define MX51_INT_SMC_RX 99
#define MX51_INT_VPU_IDLE 100
#define MX51_INT_EMI_NFC 101
#define MX51_INT_GPU_IDLE 102
#include <asm/irq.h>
#define MX51_INT_BASE (NR_IRQS_LEGACY + 0)
#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0)
#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5)
#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6)
#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7)
#define MX51_INT_NFC (NR_IRQS_LEGACY + 8)
#define MX51_INT_VPU (NR_IRQS_LEGACY + 9)
#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
#define MX51_INT_GPU (NR_IRQS_LEGACY + 12)
#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13)
#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14)
#define MX51_INT_EMI (NR_IRQS_LEGACY + 15)
#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16)
#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17)
#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18)
#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26)
#define MX51_INT_CSU (NR_IRQS_LEGACY + 27)
#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28)
#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29)
#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30)
#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31)
#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32)
#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33)
#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34)
#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35)
#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38)
#define MX51_INT_GPT (NR_IRQS_LEGACY + 39)
#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40)
#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41)
#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58)
#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59)
#define MX51_INT_KPP (NR_IRQS_LEGACY + 60)
#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61)
#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62)
#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63)
#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64)
#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65)
#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66)
#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67)
#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
#define MX51_INT_IIM (NR_IRQS_LEGACY + 69)
#define MX51_INT_ATA (NR_IRQS_LEGACY + 70)
#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71)
#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72)
#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73)
#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74)
#define MX51_INT_SRC (NR_IRQS_LEGACY + 75)
#define MX51_INT_NM (NR_IRQS_LEGACY + 76)
#define MX51_INT_PMU (NR_IRQS_LEGACY + 77)
#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81)
#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82)
#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83)
#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86)
#define MX51_INT_FEC (NR_IRQS_LEGACY + 87)
#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88)
#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
#define MX51_INT_SJC (NR_IRQS_LEGACY + 90)
#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91)
#define MX51_INT_TVE (NR_IRQS_LEGACY + 92)
#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93)
#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94)
#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96)
#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99)
#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern int mx51_revision(void);

217
arch/arm/plat-mxc/include/mach/mx53.h
View File

@ -229,113 +229,114 @@
/*
* Interrupt numbers
*/
#define MX53_INT_RESV0 0
#define MX53_INT_ESDHC1 1
#define MX53_INT_ESDHC2 2
#define MX53_INT_ESDHC3 3
#define MX53_INT_ESDHC4 4
#define MX53_INT_DAP 5
#define MX53_INT_SDMA 6
#define MX53_INT_IOMUX 7
#define MX53_INT_NFC 8
#define MX53_INT_VPU 9
#define MX53_INT_IPU_ERR 10
#define MX53_INT_IPU_SYN 11
#define MX53_INT_GPU 12
#define MX53_INT_UART4 13
#define MX53_INT_USB_H1 14
#define MX53_INT_EMI 15
#define MX53_INT_USB_H2 16
#define MX53_INT_USB_H3 17
#define MX53_INT_USB_OTG 18
#define MX53_INT_SAHARA_H0 19
#define MX53_INT_SAHARA_H1 20
#define MX53_INT_SCC_SMN 21
#define MX53_INT_SCC_STZ 22
#define MX53_INT_SCC_SCM 23
#define MX53_INT_SRTC_NTZ 24
#define MX53_INT_SRTC_TZ 25
#define MX53_INT_RTIC 26
#define MX53_INT_CSU 27
#define MX53_INT_SATA 28
#define MX53_INT_SSI1 29
#define MX53_INT_SSI2 30
#define MX53_INT_UART1 31
#define MX53_INT_UART2 32
#define MX53_INT_UART3 33
#define MX53_INT_RTC 34
#define MX53_INT_PTP 35
#define MX53_INT_ECSPI1 36
#define MX53_INT_ECSPI2 37
#define MX53_INT_CSPI 38
#define MX53_INT_GPT 39
#define MX53_INT_EPIT1 40
#define MX53_INT_EPIT2 41
#define MX53_INT_GPIO1_INT7 42
#define MX53_INT_GPIO1_INT6 43
#define MX53_INT_GPIO1_INT5 44
#define MX53_INT_GPIO1_INT4 45
#define MX53_INT_GPIO1_INT3 46
#define MX53_INT_GPIO1_INT2 47
#define MX53_INT_GPIO1_INT1 48
#define MX53_INT_GPIO1_INT0 49
#define MX53_INT_GPIO1_LOW 50
#define MX53_INT_GPIO1_HIGH 51
#define MX53_INT_GPIO2_LOW 52
#define MX53_INT_GPIO2_HIGH 53
#define MX53_INT_GPIO3_LOW 54
#define MX53_INT_GPIO3_HIGH 55
#define MX53_INT_GPIO4_LOW 56
#define MX53_INT_GPIO4_HIGH 57
#define MX53_INT_WDOG1 58
#define MX53_INT_WDOG2 59
#define MX53_INT_KPP 60
#define MX53_INT_PWM1 61
#define MX53_INT_I2C1 62
#define MX53_INT_I2C2 63
#define MX53_INT_I2C3 64
#define MX53_INT_MLB 65
#define MX53_INT_ASRC 66
#define MX53_INT_SPDIF 67
#define MX53_INT_SIM_DAT 68
#define MX53_INT_IIM 69
#define MX53_INT_ATA 70
#define MX53_INT_CCM1 71
#define MX53_INT_CCM2 72
#define MX53_INT_GPC1 73
#define MX53_INT_GPC2 74
#define MX53_INT_SRC 75
#define MX53_INT_NM 76
#define MX53_INT_PMU 77
#define MX53_INT_CTI_IRQ 78
#define MX53_INT_CTI1_TG0 79
#define MX53_INT_CTI1_TG1 80
#define MX53_INT_ESAI 81
#define MX53_INT_CAN1 82
#define MX53_INT_CAN2 83
#define MX53_INT_GPU2_IRQ 84
#define MX53_INT_GPU2_BUSY 85
#define MX53_INT_UART5 86
#define MX53_INT_FEC 87
#define MX53_INT_OWIRE 88
#define MX53_INT_CTI1_TG2 89
#define MX53_INT_SJC 90
#define MX53_INT_TVE 92
#define MX53_INT_FIRI 93
#define MX53_INT_PWM2 94
#define MX53_INT_SLIM_EXP 95
#define MX53_INT_SSI3 96
#define MX53_INT_EMI_BOOT 97
#define MX53_INT_CTI1_TG3 98
#define MX53_INT_SMC_RX 99
#define MX53_INT_VPU_IDLE 100
#define MX53_INT_EMI_NFC 101
#define MX53_INT_GPU_IDLE 102
#define MX53_INT_GPIO5_LOW 103
#define MX53_INT_GPIO5_HIGH 104
#define MX53_INT_GPIO6_LOW 105
#define MX53_INT_GPIO6_HIGH 106
#define MX53_INT_GPIO7_LOW 107
#define MX53_INT_GPIO7_HIGH 108
#include <asm/irq.h>
#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0)
#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
#define MX53_INT_DAP (NR_IRQS_LEGACY + 5)
#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6)
#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7)
#define MX53_INT_NFC (NR_IRQS_LEGACY + 8)
#define MX53_INT_VPU (NR_IRQS_LEGACY + 9)
#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
#define MX53_INT_GPU (NR_IRQS_LEGACY + 12)
#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13)
#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14)
#define MX53_INT_EMI (NR_IRQS_LEGACY + 15)
#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16)
#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17)
#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18)
#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26)
#define MX53_INT_CSU (NR_IRQS_LEGACY + 27)
#define MX53_INT_SATA (NR_IRQS_LEGACY + 28)
#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29)
#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30)
#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31)
#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32)
#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33)
#define MX53_INT_RTC (NR_IRQS_LEGACY + 34)
#define MX53_INT_PTP (NR_IRQS_LEGACY + 35)
#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38)
#define MX53_INT_GPT (NR_IRQS_LEGACY + 39)
#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40)
#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41)
#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58)
#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59)
#define MX53_INT_KPP (NR_IRQS_LEGACY + 60)
#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61)
#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62)
#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63)
#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64)
#define MX53_INT_MLB (NR_IRQS_LEGACY + 65)
#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66)
#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67)
#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
#define MX53_INT_IIM (NR_IRQS_LEGACY + 69)
#define MX53_INT_ATA (NR_IRQS_LEGACY + 70)
#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71)
#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72)
#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73)
#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74)
#define MX53_INT_SRC (NR_IRQS_LEGACY + 75)
#define MX53_INT_NM (NR_IRQS_LEGACY + 76)
#define MX53_INT_PMU (NR_IRQS_LEGACY + 77)
#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81)
#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82)
#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83)
#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86)
#define MX53_INT_FEC (NR_IRQS_LEGACY + 87)
#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88)
#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
#define MX53_INT_SJC (NR_IRQS_LEGACY + 90)
#define MX53_INT_TVE (NR_IRQS_LEGACY + 92)
#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93)
#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94)
#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96)
#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99)
#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107)
#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108)
#endif /* ifndef __MACH_MX53_H__ */

30
arch/arm/plat-mxc/tzic.c
View File

@ -15,6 +15,8 @@
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
@ -49,6 +51,7 @@
#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
static struct irq_domain *domain;
#define TZIC_NUM_IRQS 128
@ -77,15 +80,14 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
static void tzic_irq_suspend(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
int idx = gc->irq_base >> 5;
int idx = d->hwirq >> 5;
__raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
}
static void tzic_irq_resume(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
int idx = gc->irq_base >> 5;
int idx = d->hwirq >> 5;
__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
tzic_base + TZIC_WAKEUP0(idx));
@ -102,11 +104,10 @@ static struct mxc_extra_irq tzic_extra_irq = {
#endif
};
static __init void tzic_init_gc(unsigned int irq_start)
static __init void tzic_init_gc(int idx, unsigned int irq_start)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
int idx = irq_start >> 5;
gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
handle_level_irq);
@ -140,7 +141,8 @@ asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
while (stat) {
handled = 1;
irqofs = fls(stat) - 1;
handle_IRQ(irqofs + i * 32, regs);
handle_IRQ(irq_find_mapping(domain,
irqofs + i * 32), regs);
stat &= ~(1 << irqofs);
}
}
@ -154,6 +156,8 @@ asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
*/
void __init tzic_init_irq(void __iomem *irqbase)
{
struct device_node *np;
int irq_base;
int i;
tzic_base = irqbase;
@ -175,12 +179,20 @@ void __init tzic_init_irq(void __iomem *irqbase)
/* all IRQ no FIQ Warning :: No selection */
for (i = 0; i < TZIC_NUM_IRQS; i += 32)
tzic_init_gc(i);
irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
WARN_ON(irq_base < 0);
np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
&irq_domain_simple_ops, NULL);
WARN_ON(!domain);
for (i = 0; i < 4; i++, irq_base += 32)
tzic_init_gc(i, irq_base);
#ifdef CONFIG_FIQ
/* Initialize FIQ */
init_FIQ();
init_FIQ(FIQ_START);
#endif
pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");

2
arch/arm/plat-s3c24xx/irq.c
View File

@ -533,7 +533,7 @@ void __init s3c24xx_init_irq(void)
int i;
#ifdef CONFIG_FIQ
init_FIQ();
init_FIQ(FIQ_START);
#endif
irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");

8
drivers/dma/ipu/ipu_idmac.c
View File

@ -1663,7 +1663,6 @@ static void __exit ipu_idmac_exit(struct ipu *ipu)
static int __init ipu_probe(struct platform_device *pdev)
{
struct ipu_platform_data *pdata = pdev->dev.platform_data;
struct resource *mem_ipu, *mem_ic;
int ret;
@ -1671,7 +1670,7 @@ static int __init ipu_probe(struct platform_device *pdev)
mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mem_ic = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!pdata || !mem_ipu || !mem_ic)
if (!mem_ipu || !mem_ic)
return -EINVAL;
ipu_data.dev = &pdev->dev;
@ -1688,10 +1687,9 @@ static int __init ipu_probe(struct platform_device *pdev)
goto err_noirq;
ipu_data.irq_err = ret;
ipu_data.irq_base = pdata->irq_base;
dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n",
ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base);
dev_dbg(&pdev->dev, "fn irq %u, err irq %u\n",
ipu_data.irq_fn, ipu_data.irq_err);
/* Remap IPU common registers */
ipu_data.reg_ipu = ioremap(mem_ipu->start, resource_size(mem_ipu));

14
drivers/dma/ipu/ipu_irq.c
View File

@ -14,6 +14,7 @@
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/module.h>
#include <mach/ipu.h>
@ -354,10 +355,12 @@ static struct irq_chip ipu_irq_chip = {
/* Install the IRQ handler */
int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
{
struct ipu_platform_data *pdata = dev->dev.platform_data;
unsigned int irq, irq_base, i;
unsigned int irq, i;
int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
numa_node_id());
irq_base = pdata->irq_base;
if (irq_base < 0)
return irq_base;
for (i = 0; i < IPU_IRQ_NR_BANKS; i++)
irq_bank[i].ipu = ipu;
@ -387,15 +390,16 @@ int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
irq_set_handler_data(ipu->irq_err, ipu);
irq_set_chained_handler(ipu->irq_err, ipu_irq_err);
ipu->irq_base = irq_base;
return 0;
}
void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev)
{
struct ipu_platform_data *pdata = dev->dev.platform_data;
unsigned int irq, irq_base;
irq_base = pdata->irq_base;
irq_base = ipu->irq_base;
irq_set_chained_handler(ipu->irq_fn, NULL);
irq_set_handler_data(ipu->irq_fn, NULL);

56
drivers/gpio/gpio-mxc.c
View File

@ -23,6 +23,7 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@ -33,8 +34,6 @@
#include <asm-generic/bug.h>
#include <asm/mach/irq.h>
#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
enum mxc_gpio_hwtype {
IMX1_GPIO, /* runs on i.mx1 */
IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
@ -61,7 +60,7 @@ struct mxc_gpio_port {
void __iomem *base;
int irq;
int irq_high;
int virtual_irq_start;
struct irq_domain *domain;
struct bgpio_chip bgc;
u32 both_edges;
};
@ -144,14 +143,15 @@ static LIST_HEAD(mxc_gpio_ports);
static int gpio_set_irq_type(struct irq_data *d, u32 type)
{
u32 gpio = irq_to_gpio(d->irq);
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct mxc_gpio_port *port = gc->private;
u32 bit, val;
u32 gpio_idx = d->hwirq;
u32 gpio = port->bgc.gc.base + gpio_idx;
int edge;
void __iomem *reg = port->base;
port->both_edges &= ~(1 << (gpio & 31));
port->both_edges &= ~(1 << gpio_idx);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
edge = GPIO_INT_RISE_EDGE;
@ -168,7 +168,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type)
edge = GPIO_INT_HIGH_LEV;
pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
}
port->both_edges |= 1 << (gpio & 31);
port->both_edges |= 1 << gpio_idx;
break;
case IRQ_TYPE_LEVEL_LOW:
edge = GPIO_INT_LOW_LEV;
@ -180,11 +180,11 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type)
return -EINVAL;
}
reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
bit = gpio & 0xf;
reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* ICR1 or ICR2 */
bit = gpio_idx & 0xf;
val = readl(reg) & ~(0x3 << (bit << 1));
writel(val | (edge << (bit << 1)), reg);
writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
writel(1 << gpio_idx, port->base + GPIO_ISR);
return 0;
}
@ -217,15 +217,13 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
/* handle 32 interrupts in one status register */
static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
{
u32 gpio_irq_no_base = port->virtual_irq_start;
while (irq_stat != 0) {
int irqoffset = fls(irq_stat) - 1;
if (port->both_edges & (1 << irqoffset))
mxc_flip_edge(port, irqoffset);
generic_handle_irq(gpio_irq_no_base + irqoffset);
generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
irq_stat &= ~(1 << irqoffset);
}
@ -276,10 +274,9 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
*/
static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
{
u32 gpio = irq_to_gpio(d->irq);
u32 gpio_idx = gpio & 0x1F;
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct mxc_gpio_port *port = gc->private;
u32 gpio_idx = d->hwirq;
if (enable) {
if (port->irq_high && (gpio_idx >= 16))
@ -296,12 +293,12 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
return 0;
}
static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
port->base, handle_level_irq);
gc->private = port;
@ -352,7 +349,7 @@ static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
struct mxc_gpio_port *port =
container_of(bgc, struct mxc_gpio_port, bgc);
return port->virtual_irq_start + offset;
return irq_find_mapping(port->domain, offset);
}
static int __devinit mxc_gpio_probe(struct platform_device *pdev)
@ -360,6 +357,7 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev)
struct device_node *np = pdev->dev.of_node;
struct mxc_gpio_port *port;
struct resource *iores;
int irq_base;
int err;
mxc_gpio_get_hw(pdev);
@ -432,20 +430,30 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev)
if (err)
goto out_bgpio_remove;
/*
* In dt case, we use gpio number range dynamically
* allocated by gpio core.
*/
port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
pdev->id * 32);
irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
if (irq_base < 0) {
err = irq_base;
goto out_gpiochip_remove;
}
port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
&irq_domain_simple_ops, NULL);
if (!port->domain) {
err = -ENODEV;
goto out_irqdesc_free;
}
/* gpio-mxc can be a generic irq chip */
mxc_gpio_init_gc(port);
mxc_gpio_init_gc(port, irq_base);
list_add_tail(&port->node, &mxc_gpio_ports);
return 0;
out_irqdesc_free:
irq_free_descs(irq_base, 32);
out_gpiochip_remove:
WARN_ON(gpiochip_remove(&port->bgc.gc) < 0);
out_bgpio_remove:
bgpio_remove(&port->bgc);
out_iounmap:

1
drivers/i2c/busses/i2c-imx.c
View File

@ -53,7 +53,6 @@
#include <linux/of_i2c.h>
#include <linux/pinctrl/consumer.h>
#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/i2c.h>

1
drivers/media/video/mx1_camera.c
View File

@ -43,6 +43,7 @@
#include <asm/fiq.h>
#include <mach/dma-mx1-mx2.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/mx1_camera.h>
/*

6
drivers/tty/serial/imx.c
View File

@ -169,7 +169,6 @@
#define SERIAL_IMX_MAJOR 207
#define MINOR_START 16
#define DEV_NAME "ttymxc"
#define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
/*
* This determines how often we check the modem status signals
@ -741,10 +740,7 @@ static int imx_startup(struct uart_port *port)
/* do not use RTS IRQ on IrDA */
if (!USE_IRDA(sport)) {
retval = request_irq(sport->rtsirq, imx_rtsint,
(sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
IRQF_TRIGGER_FALLING |
IRQF_TRIGGER_RISING,
retval = request_irq(sport->rtsirq, imx_rtsint, 0,
DRIVER_NAME, sport);
if (retval)
goto error_out3;

1
sound/soc/fsl/imx-pcm-fiq.c
View File

@ -29,6 +29,7 @@
#include <asm/fiq.h>
#include <mach/irqs.h>
#include <mach/ssi.h>
#include "imx-ssi.h"