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clk: vt8500: Fix error in PLL calculations on non-exact match. 

When a PLL frequency calculation is performed and a non-exact match
is found the wrong multiplier and divisors are returned.

Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Tony Prisk 2012-12-27 13:14:29 +13:00 committed by Mike Turquette
parent 3fe296cf5a
commit 35a5db55ab
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/clk-vt8500.c
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@ -361,9 +361,9 @@ static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
/* if we got here, it wasn't an exact match */
pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
rate - best_err);
*multiplier = mul;
*divisor1 = div1;
*divisor2 = div2;
*multiplier = best_mul;
*divisor1 = best_div1;
*divisor2 = best_div2;
}
static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,