ARM: dts: mvebu: armada-395-gp: add support for the Armada 395 GP Board
This commit adds description for the following features for this board: - Serial port - PCIe interfaces - USB2.0 - USB3.0 - SDIO - 1024 MiB NAND-FLASH - SATA - I2C buses Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit is contained in:
Grzegorz Jaszczyk
Gregory CLEMENT
parent
0c2123a69e
commit
3566451235
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@ -15,6 +15,10 @@ Required root node property:
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compatible: must contain "marvell,armada395"
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Example:
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compatible = "marvell,a395-gp", "marvell,armada395", "marvell,armada390";
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Boards using the Marvell Armada 398 SoC shall have the following
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property before the common "marvell,armada390" one:
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@ -0,0 +1,163 @@
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/*
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* Device Tree file for Marvell Armada 395 GP board
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*
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* Copyright (C) 2016 Marvell
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*
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* Grzegorz Jaszczyk <jaz@semihalf.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "armada-395.dtsi"
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/ {
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model = "Marvell Armada 395 GP Board";
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compatible = "marvell,a395-gp", "marvell,armada395",
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"marvell,armada390";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; /* 1 GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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internal-regs {
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i2c@11000 {
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status = "okay";
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clock-frequency = <100000>;
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eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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};
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};
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serial@12000 {
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/*
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* Exported on the micro USB connector CON17
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* through an FTDI
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*/
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status = "okay";
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};
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/* CON1 */
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usb@58000 {
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status = "okay";
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};
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/* CON2 */
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sata@a8000 {
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status = "okay";
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};
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flash@d0000 {
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status = "okay";
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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num-cs = <1>;
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x00000000 0x00600000>;
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read-only;
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};
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partition@800000 {
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label = "uImage";
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reg = <0x00600000 0x00400000>;
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read-only;
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};
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partition@1000000 {
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label = "Root";
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reg = <0x00a00000 0x3f600000>;
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};
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};
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};
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/* CON18 */
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sdhci@d8000 {
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clock-frequency = <200000000>;
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broken-cd;
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wp-inverted;
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bus-width = <8>;
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status = "okay";
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no-1-8-v;
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};
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/* CON4 */
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usb3@f0000 {
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status = "okay";
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* The two PCIe units are accessible through
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* mini PCIe slot on the board.
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*/
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/* CON7 */
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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/* CON8 */
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pcie@4,0 {
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/* Port 3, Lane 0 */
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status = "okay";
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};
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};
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};
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};
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