x86: enable PAT for amd k8 and fam10h
make known_pat_cpu to think amd k8 and fam10h is ok too. also make tom2 below to be WRBACK Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -37,6 +37,7 @@ static struct fixed_range_block fixed_range_blocks[] = {
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static unsigned long smp_changes_mask;
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static struct mtrr_state mtrr_state = {};
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static int mtrr_state_set;
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static u64 tom2;
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#undef MODULE_PARAM_PREFIX
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#define MODULE_PARAM_PREFIX "mtrr."
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@ -138,6 +139,11 @@ u8 mtrr_type_lookup(u64 start, u64 end)
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}
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}
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if (tom2) {
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if (start >= (1ULL<<32) && (end < tom2))
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return MTRR_TYPE_WRBACK;
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}
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if (prev_match != 0xFF)
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return prev_match;
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@ -206,6 +212,15 @@ void __init get_mtrr_state(void)
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mtrr_state.def_type = (lo & 0xff);
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mtrr_state.enabled = (lo & 0xc00) >> 10;
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if (amd_special_default_mtrr()) {
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unsigned lo, hi;
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/* TOP_MEM2 */
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rdmsr(MSR_K8_TOP_MEM2, lo, hi);
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tom2 = hi;
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tom2 <<= 32;
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tom2 |= lo;
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tom2 &= 0xffffff8000000ULL;
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}
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if (mtrr_show) {
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int high_width;
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@ -236,6 +251,8 @@ void __init get_mtrr_state(void)
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else
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printk(KERN_INFO "MTRR %u disabled\n", i);
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}
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if (tom2)
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printk(KERN_INFO "TOM2: %016lx aka %ldM\n", tom2, tom2>>20);
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}
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mtrr_state_set = 1;
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@ -627,7 +627,7 @@ early_param("disable_mtrr_trim", disable_mtrr_trim_setup);
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#define Tom2Enabled (1U << 21)
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#define Tom2ForceMemTypeWB (1U << 22)
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static __init int amd_special_default_mtrr(void)
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int __init amd_special_default_mtrr(void)
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{
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u32 l, h;
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@ -47,6 +47,12 @@ static int pat_known_cpu(void)
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return 1;
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}
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}
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
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boot_cpu_data.x86 >= 0xf && boot_cpu_data.x86 <= 0x11) {
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if (cpu_has_pat) {
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return 1;
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}
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}
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pat_wc_enabled = 0;
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printk(KERN_INFO "CPU and/or kernel does not support PAT.\n");
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@ -99,6 +99,7 @@ extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi);
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extern void mtrr_ap_init(void);
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extern void mtrr_bp_init(void);
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extern int mtrr_trim_uncached_memory(unsigned long end_pfn);
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extern int amd_special_default_mtrr(void);
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# else
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static inline u8 mtrr_type_lookup(u64 addr, u64 end)
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{
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