The i.MX device tree changes for 4.4:
- Add IOMUXC LPSR (Low Power State Retention) device for i.MX7D.
- Add a few low power mode related devices and touch controller for
i.MX6UL.
- Add a number of devices for i.MX7D SDB board support, USB, Dual FEC,
and eMMC5.0.
- i.MX6 Boundary Devices updates: relicense under GPLv2/X11, add Okaya
LCD, touch and wifi support, add new boards Nitrogen6_Lite and
Nitrogen6_Max.
- Enable touch screen and NAND Flash controller for a few Vybrid
devices.
- Some random and small updates on LS1021A and MXS support.
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Merge tag 'imx-dt-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
The i.MX device tree changes for 4.4:
- Add IOMUXC LPSR (Low Power State Retention) device for i.MX7D.
- Add a few low power mode related devices and touch controller for
i.MX6UL.
- Add a number of devices for i.MX7D SDB board support, USB, Dual FEC,
and eMMC5.0.
- i.MX6 Boundary Devices updates: relicense under GPLv2/X11, add Okaya
LCD, touch and wifi support, add new boards Nitrogen6_Lite and
Nitrogen6_Max.
- Enable touch screen and NAND Flash controller for a few Vybrid
devices.
- Some random and small updates on LS1021A and MXS support.
* tag 'imx-dt-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (53 commits)
ARM: dts: ls1021a: Add quirk for Erratum A009116
ARM: imx6sx-sdb: Fix typo in regulator enable GPIO property
ARM: dts: imx6: phyFLEX: fix typo in "pinctrl-names"
ARM: dts: imx6: change the core clock of spdif
ARM: dts: vf-colibri: enable NAND flash controller
ARM: dts: vf610twr: add NAND flash controller peripherial
ARM: dts: imx: add Boundary Devices Nitrogen6_Lite board
ARM: dts: imx: add Boundary Devices Nitrogen6_Max board
ARM: dts: imx6dl-nitrogen6x: change manufacturer to Boundary Devices
ARM: dts: imx6q-nitrogen6x: change manufacturer to Boundary Devices
of: Add Boundary Devices Inc. vendor prefix
ARM: dts: imx6qdl-sabrelite: relicense under GPLv2/X11
ARM: dts: imx6qdl-nitrogen6x: relicense under GPLv2/X11
ARM: dts: imx6qdl-nitrogen6x: add wifi wl1271 support
ARM: dts: imx6dql-nitrogen6x: add touchscreen support
ARM: dts: imx6qdl-sabrelite: add Okaya LCD panel
ARM: dts: imx6qdl-nitrogen6x: add Okaya LCD panel
ARM: dts: vf500-colibri: Add device tree node for touchscreen support
ARM: dts: i.MX35: fix cpu compatible value
ARM: dts: i.MX31: fix cpu compatible value
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
355d1ef1ad
|
|
@ -34,6 +34,7 @@ avago Avago Technologies
|
|||
avic Shanghai AVIC Optoelectronics Co., Ltd.
|
||||
axis Axis Communications AB
|
||||
bosch Bosch Sensortec GmbH
|
||||
boundary Boundary Devices Inc.
|
||||
brcm Broadcom Corporation
|
||||
buffalo Buffalo, Inc.
|
||||
calxeda Calxeda
|
||||
|
|
|
|||
|
|
@ -292,6 +292,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
|||
imx6dl-gw551x.dtb \
|
||||
imx6dl-gw552x.dtb \
|
||||
imx6dl-hummingboard.dtb \
|
||||
imx6dl-nit6xlite.dtb \
|
||||
imx6dl-nitrogen6x.dtb \
|
||||
imx6dl-phytec-pbab01.dtb \
|
||||
imx6dl-rex-basic.dtb \
|
||||
|
|
@ -321,6 +322,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
|||
imx6q-gw552x.dtb \
|
||||
imx6q-hummingboard.dtb \
|
||||
imx6q-nitrogen6x.dtb \
|
||||
imx6q-nitrogen6_max.dtb \
|
||||
imx6q-phytec-pbab01.dtb \
|
||||
imx6q-rex-pro.dtb \
|
||||
imx6q-sabreauto.dtb \
|
||||
|
|
|
|||
|
|
@ -383,9 +383,11 @@
|
|||
};
|
||||
|
||||
ocotp@8002c000 {
|
||||
compatible = "fsl,ocotp";
|
||||
compatible = "fsl,imx23-ocotp", "fsl,ocotp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x8002c000 0x2000>;
|
||||
status = "disabled";
|
||||
clocks = <&clks 15>;
|
||||
};
|
||||
|
||||
axi-ahb@8002e000 {
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@
|
|||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25vf016b";
|
||||
compatible = "sst,sst25vf016b", "jedec,spi-nor";
|
||||
spi-max-frequency = <40000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p80";
|
||||
compatible = "m25p80", "jedec,spi-nor";
|
||||
spi-max-frequency = <40000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -936,9 +936,11 @@
|
|||
};
|
||||
|
||||
ocotp: ocotp@8002c000 {
|
||||
compatible = "fsl,ocotp";
|
||||
compatible = "fsl,imx28-ocotp", "fsl,ocotp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x8002c000 0x2000>;
|
||||
status = "disabled";
|
||||
clocks = <&clks 25>;
|
||||
};
|
||||
|
||||
axi-ahb@8002e000 {
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm1136";
|
||||
compatible = "arm,arm1136jf-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm1136";
|
||||
compatible = "arm,arm1136jf-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@
|
|||
flash: m25p32@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p32", "m25p80";
|
||||
compatible = "m25p32", "jedec,spi-nor";
|
||||
spi-max-frequency = <25000000>;
|
||||
reg = <1>;
|
||||
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@
|
|||
flash: m25p32@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p32", "st,m25p";
|
||||
compatible = "st,m25p32", "st,m25p", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <1>;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright 2015 Boundary Devices, Inc.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-nit6xlite.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Boundary Devices i.MX6 Solo Nitrogen6_Lite Board";
|
||||
compatible = "boundary,imx6dl-nit6xlite", "fsl,imx6dl";
|
||||
};
|
||||
|
|
@ -3,12 +3,42 @@
|
|||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -16,6 +46,6 @@
|
|||
#include "imx6qdl-nitrogen6x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 DualLite Nitrogen6x Board";
|
||||
compatible = "fsl,imx6dl-nitrogen6x", "fsl,imx6dl";
|
||||
model = "Boundary Devices i.MX6 DualLite Nitrogen6x Board";
|
||||
compatible = "boundary,imx6dl-nitrogen6x", "fsl,imx6dl";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
|
||||
&ecspi3 {
|
||||
flash: m25p80@0 {
|
||||
compatible = "sst,sst25vf016b";
|
||||
compatible = "sst,sst25vf016b", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,12 +2,42 @@
|
|||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
|
|||
|
|
@ -109,7 +109,7 @@
|
|||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "m25p80";
|
||||
compatible = "m25p80", "jedec,spi-nor";
|
||||
spi-max-frequency = <40000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -145,7 +145,7 @@
|
|||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "sst,w25q256";
|
||||
compatible = "sst,w25q256", "jedec,spi-nor";
|
||||
spi-max-frequency = <30000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright 2015 Boundary Devices, Inc.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-nitrogen6_max.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Boundary Devices i.MX6 Quad Nitrogen6_MAX Board";
|
||||
compatible = "boundary,imx6q-nitrogen6_max", "fsl,imx6q";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -3,12 +3,42 @@
|
|||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -16,8 +46,8 @@
|
|||
#include "imx6qdl-nitrogen6x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 Quad Nitrogen6x Board";
|
||||
compatible = "fsl,imx6q-nitrogen6x", "fsl,imx6q";
|
||||
model = "Boundary Devices i.MX6 Quad Nitrogen6x Board";
|
||||
compatible = "boundary,imx6q-nitrogen6x", "fsl,imx6q";
|
||||
};
|
||||
|
||||
&sata {
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
|
||||
&ecspi3 {
|
||||
flash: m25p80@0 {
|
||||
compatible = "sst,sst25vf032b";
|
||||
compatible = "sst,sst25vf032b", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,12 +2,42 @@
|
|||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
|
|||
|
|
@ -109,7 +109,7 @@
|
|||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q128a11";
|
||||
compatible = "micron,n25q128a11", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -141,7 +141,7 @@
|
|||
flash: m25p80@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q128a11";
|
||||
compatible = "micron,n25q128a11", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25vf040b", "m25p80";
|
||||
compatible = "sst,sst25vf040b", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,630 @@
|
|||
/*
|
||||
* Copyright 2015 Boundary Devices, Inc.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x20000000>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_2p5v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "2P5V";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_wlan_vmmc: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wlan_vmmc>;
|
||||
regulator-name = "reg_wlan_vmmc";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
gpio = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <70000>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
bt_rfkill {
|
||||
compatible = "rfkill-gpio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_bt_rfkill>;
|
||||
gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
|
||||
name = "bt_rfkill";
|
||||
type = <2>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_keys>;
|
||||
|
||||
home {
|
||||
label = "Home";
|
||||
gpios = <&gpio7 13 IRQ_TYPE_LEVEL_LOW>;
|
||||
linux,code = <102>;
|
||||
};
|
||||
|
||||
back {
|
||||
label = "Back";
|
||||
gpios = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>;
|
||||
linux,code = <158>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_leds>;
|
||||
|
||||
j14-pin1 {
|
||||
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
||||
retain-state-suspended;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
j14-pin3 {
|
||||
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
retain-state-suspended;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
j14-pins8-9 {
|
||||
gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
|
||||
retain-state-suspended;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
j46-pin2 {
|
||||
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
|
||||
retain-state-suspended;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
j46-pin3 {
|
||||
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
|
||||
retain-state-suspended;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
backlight_lcd {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <7>;
|
||||
power-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
backlight_lvds0: backlight_lvds0 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm4 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <7>;
|
||||
power-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
panel_lvds0 {
|
||||
compatible = "hannstar,hsd100pxn1";
|
||||
backlight = <&backlight_lvds0>;
|
||||
|
||||
port {
|
||||
panel_in_lvds0: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6dl-nit6xlite-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx6dl-nit6xlite-sgtl5000";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
|
||||
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "microchip,sst25vf016b";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
|
||||
txen-skew-ps = <0>;
|
||||
txc-skew-ps = <3000>;
|
||||
rxdv-skew-ps = <0>;
|
||||
rxc-skew-ps = <3000>;
|
||||
rxd0-skew-ps = <0>;
|
||||
rxd1-skew-ps = <0>;
|
||||
rxd2-skew-ps = <0>;
|
||||
rxd3-skew-ps = <0>;
|
||||
txd0-skew-ps = <0>;
|
||||
txd1-skew-ps = <0>;
|
||||
txd2-skew-ps = <0>;
|
||||
txd3-skew-ps = <0>;
|
||||
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sgtl5000>;
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
touchscreen@04 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
touchscreen@38 {
|
||||
compatible = "edt,edt-ft5x06";
|
||||
reg = <0x38>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
rtc@6f {
|
||||
compatible = "isil,isl1208";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rtc>;
|
||||
reg = <0x6f>;
|
||||
interrupts-extended = <&gpio2 26 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_j10>;
|
||||
pinctrl-1 = <&pinctrl_j28>;
|
||||
|
||||
imx6dl-nit6xlite {
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
|
||||
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_bt_rfkill: bt_rfkillgrp {
|
||||
fsl,pins = <
|
||||
/* BT wake */
|
||||
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
|
||||
/* BT reset */
|
||||
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0
|
||||
/* BT reg en */
|
||||
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
|
||||
/* BT host wake irq */
|
||||
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
|
||||
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
/* Phy reset */
|
||||
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_keys: gpio_keysgrp {
|
||||
fsl,pins = <
|
||||
/* Home Button: J14 pin 5 */
|
||||
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
|
||||
/* Back Button: J14 pin 7 */
|
||||
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
|
||||
/* Touch IRQ: J7 pin 4 */
|
||||
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
|
||||
/* tcs2004 IRQ */
|
||||
MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
|
||||
/* tsc2004 reset */
|
||||
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_j10: j10grp {
|
||||
fsl,pins = <
|
||||
/* Broadcom WiFi module pins */
|
||||
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
|
||||
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
|
||||
MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_j28: j28grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_leds: ledsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0
|
||||
MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0
|
||||
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0
|
||||
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0
|
||||
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4: pwm4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wlan_vmmc: wlan_vmmcgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_rtc: rtcgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sgtl5000: sgtl5000grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
|
||||
/* power enable, high active */
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in_lvds0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_wlan_vmmc>;
|
||||
vqmmc-1-8-v;
|
||||
ocr-limit = <0x180>; /* 1.65v - 2.1v */
|
||||
cap-power-off-card;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,873 @@
|
|||
/*
|
||||
* Copyright 2015 Boundary Devices, Inc.
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0xF0000000>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_1p8v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "1P8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_2p5v: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "2P5V";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_h1_vbus: regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1>;
|
||||
regulator-name = "usb_h1_vbus";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_wlan_vmmc: regulator@5 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wlan_vmmc>;
|
||||
regulator-name = "reg_wlan_vmmc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <70000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_can_xcvr: regulator@6 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <6>;
|
||||
regulator-name = "CAN XCVR";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can_xcvr>;
|
||||
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_keys>;
|
||||
|
||||
power {
|
||||
label = "Power Button";
|
||||
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
menu {
|
||||
label = "Menu";
|
||||
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_MENU>;
|
||||
};
|
||||
|
||||
home {
|
||||
label = "Home";
|
||||
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_HOME>;
|
||||
};
|
||||
|
||||
back {
|
||||
label = "Back";
|
||||
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_BACK>;
|
||||
};
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
};
|
||||
|
||||
i2cmux@2 {
|
||||
compatible = "i2c-mux-gpio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2mux>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH
|
||||
&gpio4 15 GPIO_ACTIVE_HIGH>;
|
||||
i2c-parent = <&i2c2>;
|
||||
idle-state = <0>;
|
||||
|
||||
i2c2@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c2@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2cmux@3 {
|
||||
compatible = "i2c-mux-gpio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3mux>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
|
||||
i2c-parent = <&i2c3>;
|
||||
idle-state = <0>;
|
||||
|
||||
i2c3@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
speaker-enable {
|
||||
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
|
||||
retain-state-suspended;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
ttymxc4-rs232 {
|
||||
gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
|
||||
retain-state-suspended;
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
backlight_lcd: backlight_lcd {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <7>;
|
||||
power-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
backlight_lvds0: backlight_lvds0 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm4 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <7>;
|
||||
power-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
backlight_lvds1: backlight_lvds1 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <7>;
|
||||
power-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
lcd_display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interface-pix-fmt = "bgr666";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_j15>;
|
||||
status = "okay";
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
lcd_display_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
lcd_display_out: endpoint {
|
||||
remote-endpoint = <&lcd_panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel_lcd {
|
||||
compatible = "okaya,rs800480t-7x0gp";
|
||||
backlight = <&backlight_lcd>;
|
||||
|
||||
port {
|
||||
lcd_panel_in: endpoint {
|
||||
remote-endpoint = <&lcd_display_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel_lvds0 {
|
||||
compatible = "hannstar,hsd100pxn1";
|
||||
backlight = <&backlight_lvds0>;
|
||||
|
||||
port {
|
||||
panel_in_lvds0: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel_lvds1 {
|
||||
compatible = "hannstar,hsd100pxn1";
|
||||
backlight = <&backlight_lvds1>;
|
||||
|
||||
port {
|
||||
panel_in_lvds1: endpoint {
|
||||
remote-endpoint = <&lvds1_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6q-nitrogen6_max-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx6q-nitrogen6_max-sgtl5000";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sgtl5000>;
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1>;
|
||||
xceiver-supply = <®_can_xcvr>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
|
||||
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "microchip,sst25vf016b";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
|
||||
txen-skew-ps = <0>;
|
||||
txc-skew-ps = <3000>;
|
||||
rxdv-skew-ps = <0>;
|
||||
rxc-skew-ps = <3000>;
|
||||
rxd0-skew-ps = <0>;
|
||||
rxd1-skew-ps = <0>;
|
||||
rxd2-skew-ps = <0>;
|
||||
rxd3-skew-ps = <0>;
|
||||
txd0-skew-ps = <0>;
|
||||
txd1-skew-ps = <0>;
|
||||
txd2-skew-ps = <0>;
|
||||
txd3-skew-ps = <0>;
|
||||
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
|
||||
rtc: rtc@68 {
|
||||
compatible = "st,rv4162";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rv4162>;
|
||||
reg = <0x68>;
|
||||
interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
touchscreen@04 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
touchscreen@38 {
|
||||
compatible = "edt,edt-ft5x06";
|
||||
reg = <0x38>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6q-nitrogen6_max {
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
|
||||
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can1: can1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can_xcvr: can-xcvrgrp {
|
||||
fsl,pins = <
|
||||
/* Flexcan XCVR enable */
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
|
||||
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
/* Phy reset */
|
||||
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_keys: gpio_keysgrp {
|
||||
fsl,pins = <
|
||||
/* Power Button */
|
||||
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
|
||||
/* Menu Button */
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
|
||||
/* Home Button */
|
||||
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
|
||||
/* Back Button */
|
||||
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
|
||||
/* Volume Up Button */
|
||||
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
|
||||
/* Volume Down Button */
|
||||
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2mux: i2c2muxgrp {
|
||||
fsl,pins = <
|
||||
/* ov5642 camera i2c enable */
|
||||
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0
|
||||
/* ov5640_mipi camera i2c enable */
|
||||
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3mux: i2c3muxgrp {
|
||||
fsl,pins = <
|
||||
/* PCIe I2C enable */
|
||||
MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_j15: j15grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
|
||||
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
|
||||
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
|
||||
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
||||
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
||||
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
|
||||
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
|
||||
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
|
||||
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
|
||||
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
|
||||
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
|
||||
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie: pciegrp {
|
||||
fsl,pins = <
|
||||
/* PCIe reset */
|
||||
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4: pwm4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_rv4162: rv4162grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sgtl5000: sgtl5000grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart5: uart5grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1
|
||||
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1
|
||||
/* RS485 RX Enable: pull up */
|
||||
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1
|
||||
/* RS485 DEN: pull down */
|
||||
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1
|
||||
/* RS485/!RS232 Select: pull down (rs232) */
|
||||
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1
|
||||
/* ON: pull down */
|
||||
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
|
||||
/* power enable, high active */
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0
|
||||
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
|
||||
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
|
||||
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
|
||||
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wlan_vmmc: wlan_vmmcgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
|
||||
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
|
||||
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0
|
||||
MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&lcd_display_in>;
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in_lvds0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds-channel@1 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
|
||||
lvds1_out: endpoint {
|
||||
remote-endpoint = <&panel_in_lvds1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_h1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
vmmc-supply = <®_wlan_vmmc>;
|
||||
cap-power-off-card;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
wlcore: wlcore@2 {
|
||||
compatible = "ti,wl1271";
|
||||
reg = <2>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ref-clock-frequency = <38400000>;
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
vmmc-supply = <®_1p8v>;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -3,12 +3,42 @@
|
|||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
|
@ -65,6 +95,19 @@
|
|||
pinctrl-0 = <&pinctrl_can_xcvr>;
|
||||
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
reg_wlan_vmmc: regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wlan_vmmc>;
|
||||
regulator-name = "reg_wlan_vmmc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <70000>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
|
|
@ -124,7 +167,7 @@
|
|||
mux-ext-port = <3>;
|
||||
};
|
||||
|
||||
backlight_lcd {
|
||||
backlight_lcd: backlight_lcd {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
|
|
@ -142,6 +185,43 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
lcd_display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interface-pix-fmt = "bgr666";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_j15>;
|
||||
status = "okay";
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
lcd_display_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
lcd_display_out: endpoint {
|
||||
remote-endpoint = <&lcd_panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lcd_panel {
|
||||
compatible = "okaya,rs800480t-7x0gp";
|
||||
backlight = <&backlight_lcd>;
|
||||
|
||||
port {
|
||||
lcd_panel_in: endpoint {
|
||||
remote-endpoint = <&lcd_display_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "hannstar,hsd100pxn1";
|
||||
backlight = <&backlight_lvds>;
|
||||
|
|
@ -182,7 +262,7 @@
|
|||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "sst,sst25vf016b";
|
||||
compatible = "sst,sst25vf016b", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
@ -247,6 +327,21 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
touchscreen@04 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
touchscreen@38 {
|
||||
compatible = "edt,edt-ft5x06";
|
||||
reg = <0x38>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
|
|
@ -258,6 +353,7 @@
|
|||
fsl,pins = <
|
||||
/* SGTL5000 sys_mclk */
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
|
||||
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -354,6 +450,39 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_j15: j15grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
|
||||
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
|
||||
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
|
||||
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
||||
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
||||
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
|
||||
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
|
||||
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
|
||||
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
|
||||
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
|
||||
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
|
||||
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
|
||||
|
|
@ -395,6 +524,18 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
|
||||
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
|
|
@ -418,9 +559,22 @@
|
|||
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wlan_vmmc: wlan_vmmcgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
|
||||
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
|
||||
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0
|
||||
MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&lcd_display_in>;
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -489,6 +643,27 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
vmmc-supply = <®_wlan_vmmc>;
|
||||
cap-power-off-card;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
wlcore: wlcore@2 {
|
||||
compatible = "ti,wl1271";
|
||||
reg = <2>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ref-clock-frequency = <38400000>;
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Phytec phyFLEX-i.MX6 Ouad";
|
||||
model = "Phytec phyFLEX-i.MX6 Quad";
|
||||
compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
|
||||
|
||||
memory {
|
||||
|
|
@ -80,7 +80,7 @@
|
|||
cs-gpios = <&gpio4 24 0>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "m25p80";
|
||||
compatible = "m25p80", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
@ -373,7 +373,7 @@
|
|||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-name = "default";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpio = <&gpio4 17 0>;
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@
|
|||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p32";
|
||||
compatible = "st,m25p32", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,12 +2,42 @@
|
|||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
|
@ -123,7 +153,7 @@
|
|||
mux-ext-port = <4>;
|
||||
};
|
||||
|
||||
backlight_lcd {
|
||||
backlight_lcd: backlight_lcd {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
|
|
@ -141,6 +171,43 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
lcd_display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interface-pix-fmt = "bgr666";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_j15>;
|
||||
status = "okay";
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
lcd_display_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
lcd_display_out: endpoint {
|
||||
remote-endpoint = <&lcd_panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lcd_panel {
|
||||
compatible = "okaya,rs800480t-7x0gp";
|
||||
backlight = <&backlight_lcd>;
|
||||
|
||||
port {
|
||||
lcd_panel_in: endpoint {
|
||||
remote-endpoint = <&lcd_display_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "hannstar,hsd100pxn1";
|
||||
backlight = <&backlight_lvds>;
|
||||
|
|
@ -181,7 +248,7 @@
|
|||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "sst,sst25vf016b";
|
||||
compatible = "sst,sst25vf016b", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
@ -348,6 +415,39 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_j15: j15grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
|
||||
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
|
||||
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
|
||||
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
||||
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
||||
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
|
||||
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
|
||||
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
|
||||
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
|
||||
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
|
||||
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
|
||||
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
|
||||
|
|
@ -416,6 +516,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&lcd_display_in>;
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -158,7 +158,7 @@
|
|||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p32";
|
||||
compatible = "st,m25p32", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -218,16 +218,16 @@
|
|||
dmas = <&sdma 14 18 0>,
|
||||
<&sdma 15 18 0>;
|
||||
dma-names = "rx", "tx";
|
||||
clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
|
||||
<&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
|
||||
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
|
||||
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
|
||||
<&clks IMX6QDL_CLK_DUMMY>;
|
||||
clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
|
||||
<&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
|
||||
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
|
||||
<&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
|
||||
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
|
||||
clock-names = "core", "rxtx0",
|
||||
"rxtx1", "rxtx2",
|
||||
"rxtx3", "rxtx4",
|
||||
"rxtx5", "rxtx6",
|
||||
"rxtx7";
|
||||
"rxtx7", "dma";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -126,7 +126,7 @@
|
|||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p32";
|
||||
compatible = "st,m25p32", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -135,8 +135,24 @@
|
|||
ranges;
|
||||
|
||||
spdif: spdif@02004000 {
|
||||
compatible = "fsl,imx6sl-spdif",
|
||||
"fsl,imx35-spdif";
|
||||
reg = <0x02004000 0x4000>;
|
||||
interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 14 18 0>,
|
||||
<&sdma 15 18 0>;
|
||||
dma-names = "rx", "tx";
|
||||
clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
|
||||
<&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
|
||||
<&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
|
||||
<&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
|
||||
<&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
|
||||
clock-names = "core", "rxtx0",
|
||||
"rxtx1", "rxtx2",
|
||||
"rxtx3", "rxtx4",
|
||||
"rxtx5", "rxtx6",
|
||||
"rxtx7", "dma";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi1: ecspi@02008000 {
|
||||
|
|
@ -670,8 +686,11 @@
|
|||
};
|
||||
|
||||
dcp: dcp@020fc000 {
|
||||
compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
|
||||
reg = <0x020fc000 0x4000>;
|
||||
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -129,7 +129,7 @@
|
|||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25fl128s";
|
||||
compatible = "spansion,s25fl128s", "jedec,spi-nor";
|
||||
spi-max-frequency = <66000000>;
|
||||
};
|
||||
|
||||
|
|
@ -137,7 +137,7 @@
|
|||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25fl128s";
|
||||
compatible = "spansion,s25fl128s", "jedec,spi-nor";
|
||||
spi-max-frequency = <66000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@
|
|||
flash0: n25q256a@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q256a";
|
||||
compatible = "micron,n25q256a", "jedec,spi-nor";
|
||||
spi-max-frequency = <29000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
|
@ -138,7 +138,7 @@
|
|||
flash1: n25q256a@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q256a";
|
||||
compatible = "micron,n25q256a", "jedec,spi-nor";
|
||||
spi-max-frequency = <29000000>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@
|
|||
regulator-name = "peri_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
|
||||
gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -211,7 +211,7 @@
|
|||
dmas = <&sdma 14 18 0>,
|
||||
<&sdma 15 18 0>;
|
||||
dma-names = "rx", "tx";
|
||||
clocks = <&clks IMX6SX_CLK_SPDIF>,
|
||||
clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
|
||||
<&clks IMX6SX_CLK_OSC>,
|
||||
<&clks IMX6SX_CLK_SPDIF>,
|
||||
<&clks 0>, <&clks 0>, <&clks 0>,
|
||||
|
|
|
|||
|
|
@ -87,6 +87,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
&snvs_poweroff {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tsc>;
|
||||
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
measure-delay-time = <0xffff>;
|
||||
pre-charge-time = <0xfff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
|
|
@ -277,6 +290,15 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_tsc: tscgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
|
||||
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
|
||||
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
|
||||
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
|
||||
|
|
|
|||
|
|
@ -135,6 +135,11 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ocram: sram@00900000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00900000 0x20000>;
|
||||
};
|
||||
|
||||
aips1: aips-bus@02000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -424,6 +429,14 @@
|
|||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
snvs_poweroff: snvs-poweroff {
|
||||
compatible = "syscon-poweroff";
|
||||
regmap = <&snvs>;
|
||||
offset = <0x38>;
|
||||
mask = <0x60>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
snvs_pwrkey: snvs-powerkey {
|
||||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&snvs>;
|
||||
|
|
@ -571,6 +584,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
tsc: tsc@02040000 {
|
||||
compatible = "fsl,imx6ul-tsc";
|
||||
reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_IPG>,
|
||||
<&clks IMX6UL_CLK_ADC2>;
|
||||
clock-names = "tsc", "adc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc1: usdhc@02190000 {
|
||||
compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
|
||||
reg = <0x02190000 0x4000>;
|
||||
|
|
@ -625,6 +649,11 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
mmdc: mmdc@021b0000 {
|
||||
compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
|
||||
reg = <0x021b0000 0x4000>;
|
||||
};
|
||||
|
||||
qspi: qspi@021e0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -15,6 +15,122 @@
|
|||
* <mux_reg conf_reg input_reg mux_mode input_val>
|
||||
*/
|
||||
|
||||
#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
|
||||
#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
|
||||
#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
|
||||
#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
|
||||
#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
|
||||
#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
|
||||
#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
|
||||
#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
|
||||
#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
|
||||
#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
|
||||
#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4
|
||||
#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
|
||||
#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
|
||||
#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5
|
||||
#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
|
||||
#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
|
||||
#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
|
||||
#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4
|
||||
#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
|
||||
#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
|
||||
#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
|
||||
#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5
|
||||
#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
|
||||
#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
|
||||
#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0
|
||||
#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0
|
||||
#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0
|
||||
#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0
|
||||
#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1
|
||||
#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0
|
||||
#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0
|
||||
#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0
|
||||
#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0
|
||||
#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0
|
||||
#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0
|
||||
#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1
|
||||
#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0
|
||||
#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0
|
||||
#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0
|
||||
#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0
|
||||
#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0
|
||||
#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0
|
||||
#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1
|
||||
#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0
|
||||
#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0
|
||||
#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0
|
||||
#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0
|
||||
#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0
|
||||
#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0
|
||||
#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0
|
||||
#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0
|
||||
#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0
|
||||
#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0
|
||||
#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0
|
||||
#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0
|
||||
|
|
@ -453,7 +569,7 @@
|
|||
#define MX7D_PAD_LCD_DATA23__EIM_ADDR26 0x0124 0x0394 0x0000 0x4 0x0
|
||||
#define MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x0124 0x0394 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_LCD_DATA23__I2C4_SDA 0x0124 0x0394 0x05F0 0x6 0x1
|
||||
#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x06F4 0x0 0x0
|
||||
#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0128 0x0398 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x0128 0x0398 0x05D4 0x1 0x0
|
||||
#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0
|
||||
|
|
@ -469,7 +585,7 @@
|
|||
#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x012C 0x039C 0x0000 0x4 0x0
|
||||
#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x012C 0x039C 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC 0x012C 0x039C 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2
|
||||
#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0
|
||||
#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x0000 0x2 0x0
|
||||
|
|
@ -501,7 +617,7 @@
|
|||
#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT 0x013C 0x03AC 0x0000 0x4 0x0
|
||||
#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x013C 0x03AC 0x0000 0x5 0x0
|
||||
#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL 0x013C 0x03AC 0x0000 0x6 0x0
|
||||
#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0700 0x0 0x2
|
||||
#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x0140 0x03B0 0x0000 0x0 0x0
|
||||
#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x0140 0x03B0 0x0728 0x1 0x0
|
||||
#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0
|
||||
|
|
|
|||
|
|
@ -101,6 +101,45 @@
|
|||
arm-supply = <&sw1a_reg>;
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet1>;
|
||||
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
|
||||
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
|
||||
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
|
||||
assigned-clock-rates = <0>, <100000000>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet2>;
|
||||
assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
|
||||
<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
|
||||
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
|
||||
assigned-clock-rates = <0>, <100000000>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <ðphy1>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
|
|
@ -231,6 +270,17 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
vbus-supply = <®_usb_otg1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
vbus-supply = <®_usb_otg2_vbus>;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
|
|
@ -241,11 +291,60 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
bus-width = <8>;
|
||||
fsl,tuning-step = <2>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx7d-sdb {
|
||||
pinctrl_enet1: enet1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
|
||||
MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
|
||||
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
|
||||
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
|
||||
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
|
||||
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
|
||||
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
|
||||
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
|
||||
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
|
||||
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
|
||||
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
|
||||
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
|
||||
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
|
||||
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet2: enet2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
|
||||
MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
|
||||
MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
|
||||
MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
|
||||
MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
|
||||
MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
|
||||
MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
|
||||
MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
|
||||
MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
|
||||
MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
|
||||
MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
|
||||
MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
|
||||
|
|
@ -281,7 +380,6 @@
|
|||
>;
|
||||
};
|
||||
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
|
||||
|
|
|
|||
|
|
@ -446,6 +446,12 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc_lpsr: iomuxc-lpsr@302c0000 {
|
||||
compatible = "fsl,imx7d-iomuxc-lpsr";
|
||||
reg = <0x302c0000 0x10000>;
|
||||
fsl,input-sel = <&iomuxc>;
|
||||
};
|
||||
|
||||
gpt1: gpt@302d0000 {
|
||||
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
||||
reg = <0x302d0000 0x10000>;
|
||||
|
|
@ -570,6 +576,58 @@
|
|||
};
|
||||
};
|
||||
|
||||
aips2: aips-bus@30400000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30400000 0x400000>;
|
||||
ranges;
|
||||
|
||||
pwm1: pwm@30660000 {
|
||||
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30660000 0x10000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
|
||||
<&clks IMX7D_PWM1_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@30670000 {
|
||||
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30670000 0x10000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
|
||||
<&clks IMX7D_PWM2_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@30680000 {
|
||||
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30680000 0x10000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
|
||||
<&clks IMX7D_PWM3_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm4: pwm@30690000 {
|
||||
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30690000 0x10000>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
|
||||
<&clks IMX7D_PWM4_ROOT_CLK>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aips3: aips-bus@30800000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -694,6 +752,77 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg1: usb@30b10000 {
|
||||
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
|
||||
reg = <0x30b10000 0x200>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_USB_CTRL_CLK>;
|
||||
fsl,usbphy = <&usbphynop1>;
|
||||
fsl,usbmisc = <&usbmisc1 0>;
|
||||
phy-clkgate-delay-us = <400>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg2: usb@30b20000 {
|
||||
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
|
||||
reg = <0x30b20000 0x200>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_USB_CTRL_CLK>;
|
||||
fsl,usbphy = <&usbphynop2>;
|
||||
fsl,usbmisc = <&usbmisc2 0>;
|
||||
phy-clkgate-delay-us = <400>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh: usb@30b30000 {
|
||||
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
|
||||
reg = <0x30b30000 0x200>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_USB_CTRL_CLK>;
|
||||
fsl,usbphy = <&usbphynop3>;
|
||||
fsl,usbmisc = <&usbmisc3 0>;
|
||||
phy_type = "hsic";
|
||||
dr_mode = "host";
|
||||
phy-clkgate-delay-us = <400>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc1: usbmisc@30b10200 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
|
||||
reg = <0x30b10200 0x200>;
|
||||
};
|
||||
|
||||
usbmisc2: usbmisc@30b20200 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
|
||||
reg = <0x30b20200 0x200>;
|
||||
};
|
||||
|
||||
usbmisc3: usbmisc@30b30200 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
|
||||
reg = <0x30b30200 0x200>;
|
||||
};
|
||||
|
||||
usbphynop1: usbphynop1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX7D_USB_PHY1_CLK>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usbphynop2: usbphynop2 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX7D_USB_PHY2_CLK>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usbphynop3: usbphynop3 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usdhc1: usdhc@30b40000 {
|
||||
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
|
|
@ -729,6 +858,42 @@
|
|||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec1: ethernet@30be0000 {
|
||||
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x30be0000 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
|
||||
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
|
||||
<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
|
||||
<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
|
||||
<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
fsl,num-tx-queues=<3>;
|
||||
fsl,num-rx-queues=<3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec2: ethernet@30bf0000 {
|
||||
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x30bf0000 0x10000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
|
||||
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
|
||||
<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
|
||||
<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
|
||||
<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
fsl,num-tx-queues=<3>;
|
||||
fsl,num-rx-queues=<3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -144,6 +144,19 @@
|
|||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
ina220@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
ina220@41 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@
|
|||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
crypto = &crypto;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
|
|
@ -148,6 +149,45 @@
|
|||
big-endian;
|
||||
};
|
||||
|
||||
crypto: crypto@1700000 {
|
||||
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
|
||||
fsl,sec-era = <7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0x1700000 0x0 0x100000>;
|
||||
ranges = <0x0 0x0 0x1700000 0x100000>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x10000 0x10000>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@20000 {
|
||||
compatible = "fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x20000 0x10000>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@30000 {
|
||||
compatible = "fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@40000 {
|
||||
compatible = "fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x40000 0x10000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
clockgen: clocking@1ee1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -405,6 +445,7 @@
|
|||
model = "eTSEC";
|
||||
fsl,magic-packet;
|
||||
ranges;
|
||||
dma-coherent;
|
||||
|
||||
queue-group@2d10000 {
|
||||
#address-cells = <2>;
|
||||
|
|
@ -433,6 +474,7 @@
|
|||
interrupt-parent = <&gic>;
|
||||
model = "eTSEC";
|
||||
ranges;
|
||||
dma-coherent;
|
||||
|
||||
queue-group@2d50000 {
|
||||
#address-cells = <2>;
|
||||
|
|
@ -461,6 +503,7 @@
|
|||
interrupt-parent = <&gic>;
|
||||
model = "eTSEC";
|
||||
ranges;
|
||||
dma-coherent;
|
||||
|
||||
queue-group@2d90000 {
|
||||
#address-cells = <2>;
|
||||
|
|
@ -494,6 +537,7 @@
|
|||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -52,6 +52,26 @@
|
|||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
};
|
||||
|
||||
&nfc {
|
||||
assigned-clocks = <&clks VF610_CLK_NFC>;
|
||||
assigned-clock-rates = <33000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nfc>;
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
compatible = "fsl,vf610-nfc-nandcs";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-ecc-strength = <32>;
|
||||
nand-ecc-step-size = <2048>;
|
||||
nand-on-flash-bbt;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm0>;
|
||||
|
|
@ -156,6 +176,25 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_nfc: nfcgrp {
|
||||
fsl,pins = <
|
||||
VF610_PAD_PTD23__NF_IO7 0x28df
|
||||
VF610_PAD_PTD22__NF_IO6 0x28df
|
||||
VF610_PAD_PTD21__NF_IO5 0x28df
|
||||
VF610_PAD_PTD20__NF_IO4 0x28df
|
||||
VF610_PAD_PTD19__NF_IO3 0x28df
|
||||
VF610_PAD_PTD18__NF_IO2 0x28df
|
||||
VF610_PAD_PTD17__NF_IO1 0x28df
|
||||
VF610_PAD_PTD16__NF_IO0 0x28df
|
||||
VF610_PAD_PTB24__NF_WE_B 0x28c2
|
||||
VF610_PAD_PTB25__NF_CE0_B 0x28c2
|
||||
VF610_PAD_PTB27__NF_RE_B 0x28c2
|
||||
VF610_PAD_PTC26__NF_RB_B 0x283d
|
||||
VF610_PAD_PTC27__NF_ALE 0x28c2
|
||||
VF610_PAD_PTC28__NF_CLE 0x28c2
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm0: pwm0grp {
|
||||
fsl,pins = <
|
||||
VF610_PAD_PTB0__FTM0_CH0 0x1182
|
||||
|
|
|
|||
|
|
@ -15,3 +15,8 @@
|
|||
model = "Toradex Colibri VF50 on Colibri Evaluation Board";
|
||||
compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500";
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
vf50-ts-min-pressure = <200>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,4 +17,51 @@
|
|||
memory {
|
||||
reg = <0x80000000 0x8000000>;
|
||||
};
|
||||
|
||||
touchscreen: vf50-touchscreen {
|
||||
compatible = "toradex,vf50-touchscreen";
|
||||
io-channels = <&adc1 0>,<&adc0 0>,
|
||||
<&adc0 1>,<&adc1 2>;
|
||||
xp-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
|
||||
xm-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
|
||||
yp-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
|
||||
ym-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "idle","default","gpios";
|
||||
pinctrl-0 = <&pinctrl_touchctrl_idle>;
|
||||
pinctrl-1 = <&pinctrl_touchctrl_default>;
|
||||
pinctrl-2 = <&pinctrl_touchctrl_gpios>;
|
||||
vf50-ts-min-pressure = <200>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
vf610-colibri {
|
||||
pinctrl_touchctrl_idle: touchctrl_idle {
|
||||
fsl,pins = <
|
||||
VF610_PAD_PTA18__GPIO_8 0x006d
|
||||
VF610_PAD_PTA19__GPIO_9 0x006c
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_touchctrl_default: touchctrl_default {
|
||||
fsl,pins = <
|
||||
VF610_PAD_PTA18__ADC0_SE0 0x0040
|
||||
VF610_PAD_PTA19__ADC0_SE1 0x0040
|
||||
VF610_PAD_PTA16__ADC1_SE0 0x0040
|
||||
VF610_PAD_PTB2__ADC1_SE2 0x0040
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_touchctrl_gpios: touchctrl_gpios {
|
||||
fsl,pins = <
|
||||
VF610_PAD_PTA23__GPIO_13 0x22e9
|
||||
VF610_PAD_PTB23__GPIO_93 0x22e9
|
||||
VF610_PAD_PTA22__GPIO_12 0x22e9
|
||||
VF610_PAD_PTA11__GPIO_4 0x22e9
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -237,6 +237,33 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_nfc: nfcgrp {
|
||||
fsl,pins = <
|
||||
VF610_PAD_PTD31__NF_IO15 0x28df
|
||||
VF610_PAD_PTD30__NF_IO14 0x28df
|
||||
VF610_PAD_PTD29__NF_IO13 0x28df
|
||||
VF610_PAD_PTD28__NF_IO12 0x28df
|
||||
VF610_PAD_PTD27__NF_IO11 0x28df
|
||||
VF610_PAD_PTD26__NF_IO10 0x28df
|
||||
VF610_PAD_PTD25__NF_IO9 0x28df
|
||||
VF610_PAD_PTD24__NF_IO8 0x28df
|
||||
VF610_PAD_PTD23__NF_IO7 0x28df
|
||||
VF610_PAD_PTD22__NF_IO6 0x28df
|
||||
VF610_PAD_PTD21__NF_IO5 0x28df
|
||||
VF610_PAD_PTD20__NF_IO4 0x28df
|
||||
VF610_PAD_PTD19__NF_IO3 0x28df
|
||||
VF610_PAD_PTD18__NF_IO2 0x28df
|
||||
VF610_PAD_PTD17__NF_IO1 0x28df
|
||||
VF610_PAD_PTD16__NF_IO0 0x28df
|
||||
VF610_PAD_PTB24__NF_WE_B 0x28c2
|
||||
VF610_PAD_PTB25__NF_CE0_B 0x28c2
|
||||
VF610_PAD_PTB27__NF_RE_B 0x28c2
|
||||
VF610_PAD_PTC26__NF_RB_B 0x283d
|
||||
VF610_PAD_PTC27__NF_ALE 0x28c2
|
||||
VF610_PAD_PTC28__NF_CLE 0x28c2
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm0: pwm0grp {
|
||||
fsl,pins = <
|
||||
VF610_PAD_PTB0__FTM0_CH0 0x1582
|
||||
|
|
@ -274,6 +301,26 @@
|
|||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
assigned-clocks = <&clks VF610_CLK_NFC>;
|
||||
assigned-clock-rates = <33000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nfc>;
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
compatible = "fsl,vf610-nfc-nandcs";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
nand-bus-width = <16>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-ecc-strength = <24>;
|
||||
nand-ecc-step-size = <2048>;
|
||||
nand-on-flash-bbt;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm0>;
|
||||
|
|
|
|||
|
|
@ -564,6 +564,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
nfc: nand@400e0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,vf610-nfc";
|
||||
reg = <0x400e0000 0x4000>;
|
||||
interrupts = <83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks VF610_CLK_NFC>;
|
||||
clock-names = "nfc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@400e6000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -86,6 +86,16 @@ enum mx25_clks {
|
|||
|
||||
static struct clk *clk[clk_max];
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
&clk[uart_ipg_per],
|
||||
&clk[uart1_ipg],
|
||||
&clk[uart2_ipg],
|
||||
&clk[uart3_ipg],
|
||||
&clk[uart4_ipg],
|
||||
&clk[uart5_ipg],
|
||||
NULL
|
||||
};
|
||||
|
||||
static int __init __mx25_clocks_init(unsigned long osc_rate,
|
||||
void __iomem *ccm_base)
|
||||
{
|
||||
|
|
@ -233,6 +243,8 @@ static int __init __mx25_clocks_init(unsigned long osc_rate,
|
|||
*/
|
||||
clk_set_parent(clk[cko_sel], clk[ipg]);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -47,6 +47,17 @@ static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
|
|||
static struct clk *clk[IMX27_CLK_MAX];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
&clk[IMX27_CLK_PER1_GATE],
|
||||
&clk[IMX27_CLK_UART1_IPG_GATE],
|
||||
&clk[IMX27_CLK_UART2_IPG_GATE],
|
||||
&clk[IMX27_CLK_UART3_IPG_GATE],
|
||||
&clk[IMX27_CLK_UART4_IPG_GATE],
|
||||
&clk[IMX27_CLK_UART5_IPG_GATE],
|
||||
&clk[IMX27_CLK_UART6_IPG_GATE],
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init _mx27_clocks_init(unsigned long fref)
|
||||
{
|
||||
BUG_ON(!ccm);
|
||||
|
|
@ -163,6 +174,8 @@ static void __init _mx27_clocks_init(unsigned long fref)
|
|||
|
||||
clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
imx_print_silicon_rev("i.MX27", mx27_revision());
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -62,7 +62,17 @@ enum mx31_clks {
|
|||
static struct clk *clk[clk_max];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
int __init mx31_clocks_init(unsigned long fref)
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
&clk[ipg],
|
||||
&clk[uart1_gate],
|
||||
&clk[uart2_gate],
|
||||
&clk[uart3_gate],
|
||||
&clk[uart4_gate],
|
||||
&clk[uart5_gate],
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init _mx31_clocks_init(unsigned long fref)
|
||||
{
|
||||
void __iomem *base;
|
||||
struct device_node *np;
|
||||
|
|
@ -132,6 +142,12 @@ int __init mx31_clocks_init(unsigned long fref)
|
|||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_set_parent(clk[csi], clk[upll]);
|
||||
clk_prepare_enable(clk[emi_gate]);
|
||||
clk_prepare_enable(clk[iim_gate]);
|
||||
mx31_revision();
|
||||
clk_disable_unprepare(clk[iim_gate]);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
|
||||
|
||||
if (np) {
|
||||
|
|
@ -139,6 +155,13 @@ int __init mx31_clocks_init(unsigned long fref)
|
|||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
}
|
||||
|
||||
int __init mx31_clocks_init(void)
|
||||
{
|
||||
u32 fref = 26000000; /* default */
|
||||
|
||||
_mx31_clocks_init(fref);
|
||||
|
||||
clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
|
||||
|
|
@ -194,12 +217,8 @@ int __init mx31_clocks_init(unsigned long fref)
|
|||
clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
|
||||
clk_register_clkdev(clk[iim_gate], "iim", NULL);
|
||||
|
||||
clk_set_parent(clk[csi], clk[upll]);
|
||||
clk_prepare_enable(clk[emi_gate]);
|
||||
clk_prepare_enable(clk[iim_gate]);
|
||||
mx31_revision();
|
||||
clk_disable_unprepare(clk[iim_gate]);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31);
|
||||
|
||||
return 0;
|
||||
|
|
@ -218,5 +237,7 @@ int __init mx31_clocks_init_dt(void)
|
|||
break;
|
||||
}
|
||||
|
||||
return mx31_clocks_init(fref);
|
||||
_mx31_clocks_init(fref);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -84,7 +84,15 @@ enum mx35_clks {
|
|||
|
||||
static struct clk *clk[clk_max];
|
||||
|
||||
int __init mx35_clocks_init(void)
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
&clk[ipg],
|
||||
&clk[uart1_gate],
|
||||
&clk[uart2_gate],
|
||||
&clk[uart3_gate],
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init _mx35_clocks_init(void)
|
||||
{
|
||||
void __iomem *base;
|
||||
u32 pdr0, consumer_sel, hsp_sel;
|
||||
|
|
@ -220,6 +228,32 @@ int __init mx35_clocks_init(void)
|
|||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_prepare_enable(clk[spba_gate]);
|
||||
clk_prepare_enable(clk[gpio1_gate]);
|
||||
clk_prepare_enable(clk[gpio2_gate]);
|
||||
clk_prepare_enable(clk[gpio3_gate]);
|
||||
clk_prepare_enable(clk[iim_gate]);
|
||||
clk_prepare_enable(clk[emi_gate]);
|
||||
clk_prepare_enable(clk[max_gate]);
|
||||
clk_prepare_enable(clk[iomuxc_gate]);
|
||||
|
||||
/*
|
||||
* SCC is needed to boot via mmc after a watchdog reset. The clock code
|
||||
* before conversion to common clk also enabled UART1 (which isn't
|
||||
* handled here and not needed for mmc) and IIM (which is enabled
|
||||
* unconditionally above).
|
||||
*/
|
||||
clk_prepare_enable(clk[scc_gate]);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
imx_print_silicon_rev("i.MX35", mx35_revision());
|
||||
}
|
||||
|
||||
int __init mx35_clocks_init(void)
|
||||
{
|
||||
_mx35_clocks_init();
|
||||
|
||||
clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
|
||||
clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
|
||||
clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
|
||||
|
|
@ -279,25 +313,6 @@ int __init mx35_clocks_init(void)
|
|||
clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
|
||||
clk_register_clkdev(clk[admux_gate], "audmux", NULL);
|
||||
|
||||
clk_prepare_enable(clk[spba_gate]);
|
||||
clk_prepare_enable(clk[gpio1_gate]);
|
||||
clk_prepare_enable(clk[gpio2_gate]);
|
||||
clk_prepare_enable(clk[gpio3_gate]);
|
||||
clk_prepare_enable(clk[iim_gate]);
|
||||
clk_prepare_enable(clk[emi_gate]);
|
||||
clk_prepare_enable(clk[max_gate]);
|
||||
clk_prepare_enable(clk[iomuxc_gate]);
|
||||
|
||||
/*
|
||||
* SCC is needed to boot via mmc after a watchdog reset. The clock code
|
||||
* before conversion to common clk also enabled UART1 (which isn't
|
||||
* handled here and not needed for mmc) and IIM (which is enabled
|
||||
* unconditionally above).
|
||||
*/
|
||||
clk_prepare_enable(clk[scc_gate]);
|
||||
|
||||
imx_print_silicon_rev("i.MX35", mx35_revision());
|
||||
|
||||
mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31);
|
||||
|
||||
return 0;
|
||||
|
|
@ -305,10 +320,10 @@ int __init mx35_clocks_init(void)
|
|||
|
||||
static void __init mx35_clocks_init_dt(struct device_node *ccm_node)
|
||||
{
|
||||
_mx35_clocks_init();
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
mx35_clocks_init();
|
||||
}
|
||||
CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);
|
||||
|
|
|
|||
|
|
@ -130,6 +130,20 @@ static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
|
|||
static struct clk *clk[IMX5_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
&clk[IMX5_CLK_UART1_IPG_GATE],
|
||||
&clk[IMX5_CLK_UART1_PER_GATE],
|
||||
&clk[IMX5_CLK_UART2_IPG_GATE],
|
||||
&clk[IMX5_CLK_UART2_PER_GATE],
|
||||
&clk[IMX5_CLK_UART3_IPG_GATE],
|
||||
&clk[IMX5_CLK_UART3_PER_GATE],
|
||||
&clk[IMX5_CLK_UART4_IPG_GATE],
|
||||
&clk[IMX5_CLK_UART4_PER_GATE],
|
||||
&clk[IMX5_CLK_UART5_IPG_GATE],
|
||||
&clk[IMX5_CLK_UART5_PER_GATE],
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init mx5_clocks_common_init(void __iomem *ccm_base)
|
||||
{
|
||||
clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
|
|
@ -310,6 +324,8 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
|
|||
clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
|
||||
clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
|
||||
clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
}
|
||||
|
||||
static void __init mx50_clocks_init(struct device_node *np)
|
||||
|
|
|
|||
|
|
@ -119,6 +119,7 @@ static unsigned int share_count_ssi1;
|
|||
static unsigned int share_count_ssi2;
|
||||
static unsigned int share_count_ssi3;
|
||||
static unsigned int share_count_mipi_core_cfg;
|
||||
static unsigned int share_count_spdif;
|
||||
|
||||
static inline int clk_on_imx6q(void)
|
||||
{
|
||||
|
|
@ -130,6 +131,12 @@ static inline int clk_on_imx6dl(void)
|
|||
return of_machine_is_compatible("fsl,imx6dl");
|
||||
}
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
&clk[IMX6QDL_CLK_UART_IPG],
|
||||
&clk[IMX6QDL_CLK_UART_SERIAL],
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
|
@ -456,7 +463,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4);
|
||||
clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
|
||||
clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
|
||||
clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif);
|
||||
clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
|
||||
clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
|
||||
clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
|
||||
clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
|
||||
|
|
@ -541,5 +549,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
/* All existing boards with PCIe use LVDS1 */
|
||||
if (IS_ENABLED(CONFIG_PCI_IMX6))
|
||||
clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
}
|
||||
CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
|
||||
|
|
|
|||
|
|
@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = {
|
|||
static unsigned int share_count_ssi1;
|
||||
static unsigned int share_count_ssi2;
|
||||
static unsigned int share_count_ssi3;
|
||||
static unsigned int share_count_spdif;
|
||||
|
||||
static struct clk *clks[IMX6SL_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
|
@ -184,6 +185,12 @@ void imx6sl_set_wait_clk(bool enter)
|
|||
imx6sl_enable_pll_arm(false);
|
||||
}
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
&clks[IMX6SL_CLK_UART],
|
||||
&clks[IMX6SL_CLK_UART_SERIAL],
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
|
@ -391,7 +398,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
|
||||
clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
|
||||
clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
|
||||
clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif);
|
||||
clks[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
|
||||
clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
|
||||
clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
|
||||
clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
|
||||
|
|
@ -439,5 +447,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],
|
||||
clks[IMX6SL_CLK_PLL2_PFD2]);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
}
|
||||
CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
|
||||
|
|
|
|||
|
|
@ -135,6 +135,12 @@ static u32 share_count_ssi1;
|
|||
static u32 share_count_ssi2;
|
||||
static u32 share_count_ssi3;
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
&clks[IMX6SX_CLK_UART_IPG],
|
||||
&clks[IMX6SX_CLK_UART_SERIAL],
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
|
@ -454,6 +460,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SX_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
|
||||
clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
|
||||
clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
|
||||
|
|
@ -557,5 +564,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
|
||||
clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
}
|
||||
CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
|
||||
|
|
|
|||
|
|
@ -407,6 +407,24 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
|
|||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
/*
|
||||
* Lower the AHB clock rate before changing the parent clock source,
|
||||
* as AHB clock rate can NOT be higher than 133MHz, but its parent
|
||||
* will be switched from 396MHz PFD to 528MHz PLL in order to increase
|
||||
* AXI clock rate, so we need to lower AHB rate first to make sure at
|
||||
* any time, AHB rate is <= 133MHz.
|
||||
*/
|
||||
clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
|
||||
|
||||
/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
|
||||
clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
|
||||
clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);
|
||||
clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);
|
||||
clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);
|
||||
|
||||
/* Make sure AHB rate is 132MHz */
|
||||
clk_set_rate(clks[IMX6UL_CLK_AHB], 132000000);
|
||||
|
||||
/* set perclk to from OSC */
|
||||
clk_set_parent(clks[IMX6UL_CLK_PERCLK_SEL], clks[IMX6UL_CLK_OSC]);
|
||||
|
||||
|
|
|
|||
|
|
@ -363,6 +363,17 @@ static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_
|
|||
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
&clks[IMX7D_UART1_ROOT_CLK],
|
||||
&clks[IMX7D_UART2_ROOT_CLK],
|
||||
&clks[IMX7D_UART3_ROOT_CLK],
|
||||
&clks[IMX7D_UART4_ROOT_CLK],
|
||||
&clks[IMX7D_UART5_ROOT_CLK],
|
||||
&clks[IMX7D_UART6_ROOT_CLK],
|
||||
&clks[IMX7D_UART7_ROOT_CLK],
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
|
@ -818,6 +829,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate2("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
|
||||
clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate2("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
|
||||
clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate2("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
|
||||
clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate2("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
|
||||
|
||||
clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
|
||||
|
||||
|
|
@ -856,5 +868,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
|||
/* set uart module clock's parent clock source that must be great then 80MHz */
|
||||
clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
}
|
||||
CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);
|
||||
|
|
|
|||
|
|
@ -387,6 +387,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));
|
||||
clk[VF610_CLK_DAP] = imx_clk_gate("dap", "platform_bus", CCM_CCSR, 24);
|
||||
clk[VF610_CLK_OCOTP] = imx_clk_gate("ocotp", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(5));
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
|
|
|
|||
|
|
@ -73,3 +73,41 @@ void imx_cscmr1_fixup(u32 *val)
|
|||
*val ^= CSCMR1_FIXUP;
|
||||
return;
|
||||
}
|
||||
|
||||
static int imx_keep_uart_clocks __initdata;
|
||||
static struct clk ** const *imx_uart_clocks __initdata;
|
||||
|
||||
static int __init imx_keep_uart_clocks_param(char *str)
|
||||
{
|
||||
imx_keep_uart_clocks = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
__setup_param("earlycon", imx_keep_uart_earlycon,
|
||||
imx_keep_uart_clocks_param, 0);
|
||||
__setup_param("earlyprintk", imx_keep_uart_earlyprintk,
|
||||
imx_keep_uart_clocks_param, 0);
|
||||
|
||||
void __init imx_register_uart_clocks(struct clk ** const clks[])
|
||||
{
|
||||
if (imx_keep_uart_clocks) {
|
||||
int i;
|
||||
|
||||
imx_uart_clocks = clks;
|
||||
for (i = 0; imx_uart_clocks[i]; i++)
|
||||
clk_prepare_enable(*imx_uart_clocks[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static int __init imx_clk_disable_uart(void)
|
||||
{
|
||||
if (imx_keep_uart_clocks && imx_uart_clocks) {
|
||||
int i;
|
||||
|
||||
for (i = 0; imx_uart_clocks[i]; i++)
|
||||
clk_disable_unprepare(*imx_uart_clocks[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
late_initcall_sync(imx_clk_disable_uart);
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
extern spinlock_t imx_ccm_lock;
|
||||
|
||||
void imx_check_clocks(struct clk *clks[], unsigned int count);
|
||||
void imx_register_uart_clocks(struct clk ** const clks[]);
|
||||
|
||||
extern void imx_cscmr1_fixup(u32 *val);
|
||||
|
||||
|
|
|
|||
|
|
@ -254,6 +254,7 @@
|
|||
#define IMX6QDL_CLK_CAAM_MEM 241
|
||||
#define IMX6QDL_CLK_CAAM_ACLK 242
|
||||
#define IMX6QDL_CLK_CAAM_IPG 243
|
||||
#define IMX6QDL_CLK_END 244
|
||||
#define IMX6QDL_CLK_SPDIF_GCLK 244
|
||||
#define IMX6QDL_CLK_END 245
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
|
||||
|
|
|
|||
|
|
@ -174,6 +174,7 @@
|
|||
#define IMX6SL_CLK_SSI1_IPG 161
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#define IMX6SL_CLK_SSI2_IPG 162
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||||
#define IMX6SL_CLK_SSI3_IPG 163
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#define IMX6SL_CLK_END 164
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#define IMX6SL_CLK_SPDIF_GCLK 164
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#define IMX6SL_CLK_END 165
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||||
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#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
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||||
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@ -274,6 +274,7 @@
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|||
#define IMX6SX_PLL5_BYPASS 261
|
||||
#define IMX6SX_PLL6_BYPASS 262
|
||||
#define IMX6SX_PLL7_BYPASS 263
|
||||
#define IMX6SX_CLK_CLK_END 264
|
||||
#define IMX6SX_CLK_SPDIF_GCLK 264
|
||||
#define IMX6SX_CLK_CLK_END 265
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
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||||
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|||
|
|
@ -446,5 +446,6 @@
|
|||
#define IMX7D_MU_ROOT_CLK 433
|
||||
#define IMX7D_SEMA4_HS_ROOT_CLK 434
|
||||
#define IMX7D_PLL_DRAM_TEST_DIV 435
|
||||
#define IMX7D_CLK_END 436
|
||||
#define IMX7D_ADC_ROOT_CLK 436
|
||||
#define IMX7D_CLK_END 437
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
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||||
|
|
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|||
|
|
@ -194,6 +194,7 @@
|
|||
#define VF610_PLL7_BYPASS 181
|
||||
#define VF610_CLK_SNVS 182
|
||||
#define VF610_CLK_DAP 183
|
||||
#define VF610_CLK_END 184
|
||||
#define VF610_CLK_OCOTP 184
|
||||
#define VF610_CLK_END 185
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_VF610_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue