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clk/zynq/pll: Use #defines for fbdiv min/max values 

Use more descriptive #defines for the minimum and maximum PLL
feedback divider.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Soren Brinkmann 2013-07-19 10:16:45 -07:00 committed by Michal Simek
parent 14924ba288
commit 353dc6c47d
1 changed files with 7 additions and 4 deletions
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11
drivers/clk/zynq/pll.c
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@ -50,6 +50,9 @@ struct zynq_pll {
#define PLLCTRL_RESET_MASK 1
#define PLLCTRL_RESET_SHIFT 0
#define PLL_FBDIV_MIN 13
#define PLL_FBDIV_MAX 66
/**
* zynq_pll_round_rate() - Round a clock frequency
* @hw: Handle between common and hardware-specific interfaces
@ -63,10 +66,10 @@ static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
u32 fbdiv;
fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
if (fbdiv < 13)
fbdiv = 13;
else if (fbdiv > 66)
fbdiv = 66;
if (fbdiv < PLL_FBDIV_MIN)
fbdiv = PLL_FBDIV_MIN;
else if (fbdiv > PLL_FBDIV_MAX)
fbdiv = PLL_FBDIV_MAX;
return *prate * fbdiv;
}