clk: exynos5250: add clock ID for div_pcm0

There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0.  Add a clock ID for it so that
we can reference it in device trees.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This commit is contained in:
Andrew Bresticker 2013-09-25 14:12:49 -07:00 committed by Tomasz Figa
parent 547f33509c
commit 35399dda01
3 changed files with 3 additions and 1 deletions

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@ -62,6 +62,7 @@ clock which they consume.
div_i2s1 157 div_i2s1 157
div_i2s2 158 div_i2s2 158
sclk_hdmiphy 159 sclk_hdmiphy 159
div_pcm0 160
[Peripheral Clock Gates] [Peripheral Clock Gates]

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@ -329,7 +329,7 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4), DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4), DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
DIV(0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),

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@ -55,6 +55,7 @@
#define CLK_DIV_I2S1 157 #define CLK_DIV_I2S1 157
#define CLK_DIV_I2S2 158 #define CLK_DIV_I2S2 158
#define CLK_SCLK_HDMIPHY 159 #define CLK_SCLK_HDMIPHY 159
#define CLK_DIV_PCM0 160
/* gate clocks */ /* gate clocks */
#define CLK_GSCL0 256 #define CLK_GSCL0 256