powerpc/85xx: introduce support for the Freescale / iVeia P1022RDK
The Freescale / iVeia P1022RDK reference board is a small-factor board with a Freescale P1022 SOC. It includes: 1) 512 MB 64-bit DDR3-800 (max) memory 2) 8MB SPI serial flash memory for boot loader 3) Bootable 4-bit SD/MMC port 4) Two 10/100/1000 Ethernet connectors 5) One SATA port 6) Two USB ports 7) One PCIe x4 slot 8) DVI video connector 9) Audio input and output jacks, powered by a Wolfson WM8960 codec. Unlike the P1022DS, the P1022RDK does not have any localbus devices, presumably because of the localbus / DIU multiplexing restriction of the P1022 SOC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Timur Tabi
Kumar Gala
parent
4c30c143f0
commit
34f84b5b5b
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@ -0,0 +1,188 @@
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/*
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* P1022 RDK 32-bit Physical Address Map Device Tree Source
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*
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* Copyright 2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/include/ "fsl/p1022si-pre.dtsi"
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/ {
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model = "fsl,P1022RDK";
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compatible = "fsl,P1022RDK";
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memory {
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device_type = "memory";
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};
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board_lbc: lbc: localbus@ffe05000 {
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/* The P1022 RDK does not have any localbus devices */
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status = "disabled";
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};
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board_soc: soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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i2c@3100 {
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wm8960:codec@1a {
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compatible = "wlf,wm8960";
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reg = <0x1a>;
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/* MCLK source is a stand-alone oscillator */
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clock-frequency = <12288000>;
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};
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rtc@68 {
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compatible = "stm,m41t62";
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reg = <0x68>;
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};
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adt7461@4c{
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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zl6100@21{
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compatible = "isil,zl6100";
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reg = <0x21>;
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};
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zl6100@24{
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compatible = "isil,zl6100";
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reg = <0x24>;
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};
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zl6100@26{
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compatible = "isil,zl6100";
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reg = <0x26>;
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};
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zl6100@29{
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compatible = "isil,zl6100";
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reg = <0x29>;
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};
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};
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spi@7000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,m25p80";
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reg = <0>;
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spi-max-frequency = <1000000>;
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partition@0 {
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label = "full-spi-flash";
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reg = <0x00000000 0x00100000>;
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};
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};
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};
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ssi@15000 {
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fsl,mode = "i2s-slave";
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codec-handle = <&wm8960>;
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};
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usb@22000 {
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phy_type = "ulpi";
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};
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usb@23000 {
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phy_type = "ulpi";
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};
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mdio@24000 {
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phy0: ethernet-phy@0 {
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interrupts = <3 1 0 0>;
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reg = <0x1>;
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};
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phy1: ethernet-phy@1 {
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interrupts = <9 1 0 0>;
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reg = <0x2>;
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};
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};
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mdio@25000 {
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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ethernet@b0000 {
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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ethernet@b1000 {
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phy-handle = <&phy1>;
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tbi-handle = <&tbi0>;
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phy-connection-type = "sgmii";
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};
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};
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pci0: pcie@ffe09000 {
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ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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reg = <0x0 0xffe09000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xe0000000
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0x2000000 0x0 0xe0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@ffe0a000 {
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ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
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reg = <0 0xffe0a000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xe0000000
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0x2000000 0x0 0xe0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci2: pcie@ffe0b000 {
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ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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reg = <0 0xffe0b000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xe0000000
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0x2000000 0x0 0xe0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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};
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/include/ "fsl/p1022si-post.dtsi"
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@ -30,6 +30,7 @@ CONFIG_MPC85xx_DS=y
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CONFIG_MPC85xx_RDB=y
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CONFIG_P1010_RDB=y
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CONFIG_P1022_DS=y
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CONFIG_P1022_RDK=y
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CONFIG_P1023_RDS=y
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CONFIG_SOCRATES=y
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CONFIG_KSI8560=y
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@ -32,6 +32,7 @@ CONFIG_MPC85xx_DS=y
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CONFIG_MPC85xx_RDB=y
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CONFIG_P1010_RDB=y
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CONFIG_P1022_DS=y
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CONFIG_P1022_RDK=y
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CONFIG_P1023_RDS=y
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CONFIG_SOCRATES=y
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CONFIG_KSI8560=y
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@ -104,6 +104,13 @@ config P1022_DS
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help
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This option enables support for the Freescale P1022DS reference board.
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config P1022_RDK
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bool "Freescale / iVeia P1022 RDK"
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select DEFAULT_UIMAGE
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help
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This option enables support for the Freescale / iVeia P1022RDK
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reference board.
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config P1023_RDS
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bool "Freescale P1023 RDS"
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select DEFAULT_UIMAGE
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@ -15,6 +15,7 @@ obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
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obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
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obj-$(CONFIG_P1010_RDB) += p1010rdb.o
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obj-$(CONFIG_P1022_DS) += p1022_ds.o
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obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
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obj-$(CONFIG_P1023_RDS) += p1023_rds.o
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obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o
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obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
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@ -0,0 +1,195 @@
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/*
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* P1022 RDK board specific routines
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*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* Author: Timur Tabi <timur@freescale.com>
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*
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* Based on p1022_ds.c
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/pci.h>
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#include <linux/of_platform.h>
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#include <linux/memblock.h>
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#include <asm/div64.h>
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#include <asm/mpic.h>
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#include <asm/swiotlb.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <asm/udbg.h>
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#include <asm/fsl_guts.h>
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#include "smp.h"
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#include "mpc85xx.h"
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
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#define CLKDVDR_PXCKEN 0x80000000
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#define CLKDVDR_PXCKINV 0x10000000
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#define CLKDVDR_PXCKDLY 0x06000000
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#define CLKDVDR_PXCLK_MASK 0x00FF0000
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/**
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* p1022rdk_set_monitor_port: switch the output to a different monitor port
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*/
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static void p1022rdk_set_monitor_port(enum fsl_diu_monitor_port port)
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{
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if (port != FSL_DIU_PORT_DVI) {
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pr_err("p1022rdk: unsupported monitor port %i\n", port);
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return;
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}
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}
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/**
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* p1022rdk_set_pixel_clock: program the DIU's clock
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*
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* @pixclock: the wavelength, in picoseconds, of the clock
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*/
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void p1022rdk_set_pixel_clock(unsigned int pixclock)
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{
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struct device_node *guts_np = NULL;
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struct ccsr_guts __iomem *guts;
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unsigned long freq;
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u64 temp;
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u32 pxclk;
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/* Map the global utilities registers. */
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guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
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if (!guts_np) {
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pr_err("p1022rdk: missing global utilties device node\n");
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return;
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}
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guts = of_iomap(guts_np, 0);
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of_node_put(guts_np);
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if (!guts) {
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pr_err("p1022rdk: could not map global utilties device\n");
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return;
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}
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/* Convert pixclock from a wavelength to a frequency */
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temp = 1000000000000ULL;
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do_div(temp, pixclock);
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freq = temp;
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/*
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* 'pxclk' is the ratio of the platform clock to the pixel clock.
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* This number is programmed into the CLKDVDR register, and the valid
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* range of values is 2-255.
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*/
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pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
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pxclk = clamp_t(u32, pxclk, 2, 255);
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/* Disable the pixel clock, and set it to non-inverted and no delay */
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clrbits32(&guts->clkdvdr,
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CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
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/* Enable the clock and set the pxclk */
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setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
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iounmap(guts);
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}
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/**
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* p1022rdk_valid_monitor_port: set the monitor port for sysfs
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*/
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enum fsl_diu_monitor_port
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p1022rdk_valid_monitor_port(enum fsl_diu_monitor_port port)
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{
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return FSL_DIU_PORT_DVI;
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}
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#endif
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void __init p1022_rdk_pic_init(void)
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{
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struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
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MPIC_SINGLE_DEST_CPU,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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}
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/*
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* Setup the architecture
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*/
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static void __init p1022_rdk_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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#endif
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dma_addr_t max = 0xffffffff;
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if (ppc_md.progress)
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ppc_md.progress("p1022_rdk_setup_arch()", 0);
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#ifdef CONFIG_PCI
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for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
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struct resource rsrc;
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struct pci_controller *hose;
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of_address_to_resource(np, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == 0x8000)
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fsl_add_bridge(np, 1);
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else
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fsl_add_bridge(np, 0);
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hose = pci_find_hose_for_OF_device(np);
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max = min(max, hose->dma_window_base_cur +
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hose->dma_window_size);
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}
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#endif
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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diu_ops.set_monitor_port = p1022rdk_set_monitor_port;
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diu_ops.set_pixel_clock = p1022rdk_set_pixel_clock;
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diu_ops.valid_monitor_port = p1022rdk_valid_monitor_port;
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#endif
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mpc85xx_smp_init();
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#ifdef CONFIG_SWIOTLB
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if ((memblock_end_of_DRAM() - 1) > max) {
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ppc_swiotlb_enable = 1;
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set_pci_dma_ops(&swiotlb_dma_ops);
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ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
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}
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#endif
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pr_info("Freescale / iVeia P1022 RDK reference board\n");
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}
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machine_device_initcall(p1022_rdk, mpc85xx_common_publish_devices);
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machine_arch_initcall(p1022_rdk, swiotlb_setup_bus_notifier);
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init p1022_rdk_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "fsl,p1022rdk");
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}
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define_machine(p1022_rdk) {
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.name = "P1022 RDK",
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.probe = p1022_rdk_probe,
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.setup_arch = p1022_rdk_setup_arch,
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.init_IRQ = p1022_rdk_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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