dt-bindings: pinctrl: Add DT bindings for Renesas RZ/V2M pinctrl
Add device tree binding documentation and header file for Renesas RZ/V2M pinctrl. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220624084833.22605-2-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Phil Edworthy
Geert Uytterhoeven
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/V2M combined Pin and GPIO controller
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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- Phil Edworthy <phil.edworthy@renesas.com>
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description:
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The Renesas RZ/V2M SoC features a combined Pin and GPIO controller.
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Pin multiplexing and GPIO configuration is performed on a per-pin basis.
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Each port features up to 16 pins, each of them configurable for GPIO function
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(port mode) or in alternate function mode.
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Up to 8 different alternate function modes exist for each single pin.
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properties:
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compatible:
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const: renesas,r9a09g011-pinctrl # RZ/V2M
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reg:
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maxItems: 1
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gpio-controller: true
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'#gpio-cells':
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const: 2
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description:
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The first cell contains the global GPIO port index, constructed using the
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RZV2M_GPIO() helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h> and the
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second cell represents consumer flag as mentioned in ../gpio/gpio.txt
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E.g. "RZV2M_GPIO(8, 1)" for P8_1.
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gpio-ranges:
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maxItems: 1
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interrupts:
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description: INEXINT[0..38] corresponding to individual pin inputs.
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maxItems: 39
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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additionalProperties:
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anyOf:
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- type: object
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allOf:
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- $ref: pincfg-node.yaml#
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- $ref: pinmux-node.yaml#
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description:
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Pin controller client devices use pin configuration subnodes (children
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and grandchildren) for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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phandle: true
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pinmux:
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description:
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Values are constructed from GPIO port number, pin number, and
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alternate function configuration number using the RZV2M_PORT_PINMUX()
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helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h>.
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pins: true
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bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength-microamp:
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# Superset of supported values
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enum: [ 1600, 1800, 2000, 3200, 3800, 4000, 6400, 7800, 8000,
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9000, 9600, 11000, 12000, 13000, 18000 ]
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slew-rate:
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description: 0 is slow slew rate, 1 is fast slew rate
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enum: [ 0, 1 ]
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gpio-hog: true
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gpios: true
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output-high: true
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output-low: true
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line-name: true
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- type: object
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properties:
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phandle: true
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additionalProperties:
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$ref: "#/additionalProperties/anyOf/0"
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allOf:
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- $ref: "pinctrl.yaml#"
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required:
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- compatible
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- reg
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- gpio-controller
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- '#gpio-cells'
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- gpio-ranges
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- interrupts
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- clocks
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- power-domains
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- resets
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examples:
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- |
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#include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
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#include <dt-bindings/clock/r9a09g011-cpg.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl: pinctrl@b6250000 {
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compatible = "renesas,r9a09g011-pinctrl";
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reg = <0xb6250000 0x800>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 352>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
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resets = <&cpg R9A09G011_PFC_PRESETN>;
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power-domains = <&cpg>;
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i2c2_pins: i2c2 {
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pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */
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<RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */
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};
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};
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@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* This header provides constants for Renesas RZ/V2M pinctrl bindings.
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*
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*/
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#ifndef __DT_BINDINGS_RZV2M_PINCTRL_H
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#define __DT_BINDINGS_RZV2M_PINCTRL_H
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#define RZV2M_PINS_PER_PORT 16
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/*
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* Create the pin index from its bank and position numbers and store in
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* the upper 16 bits the alternate function identifier
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*/
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#define RZV2M_PORT_PINMUX(b, p, f) ((b) * RZV2M_PINS_PER_PORT + (p) | ((f) << 16))
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/* Convert a port and pin label to its global pin index */
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#define RZV2M_GPIO(port, pin) ((port) * RZV2M_PINS_PER_PORT + (pin))
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#endif /* __DT_BINDINGS_RZV2M_PINCTRL_H */
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