clk: st: Adds Flexgen clock binding
A Flexgen structure is composed by: - a clock cross bar (represented by a mux element) - a pre and final dividers (represented by a divider and gate elements) Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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Gabriel FERNANDEZ
Mike Turquette
parent
79bb8aa16f
commit
3414666d34
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@ -32,6 +32,10 @@ address is common of all subnode.
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vcc_node {
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...
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};
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flexgen_node {
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...
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};
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...
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};
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@ -45,6 +49,7 @@ Each subnode should use the binding discribe in [2]..[7]
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[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
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[6] Documentation/devicetree/bindings/clock/st,vcc.txt
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[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
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[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
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Required properties:
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@ -0,0 +1,119 @@
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Binding for a type of flexgen structure found on certain
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STMicroelectronics consumer electronics SoC devices
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This structure includes:
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- a clock cross bar (represented by a mux element)
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- a pre and final dividers (represented by a divider and gate elements)
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Flexgen structure is a part of Clockgen[1].
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Please find an example below:
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Clockgen block diagram
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-------------------------------------------------------------------
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| Flexgen stucture |
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| --------------------------------------------- |
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| | ------- -------- -------- | |
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clk_sysin | | | | | | | | |
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---|-----------------|-->| | | | | | | |
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| | | | | | | | | | |
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| | ------- | | | |Pre | |Final | | |
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| | |PLL0 | | | | |Dividers| |Dividers| | |
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| |->| | | | | | x32 | | x32 | | |
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| | | odf_0|----|-->| | | | | | | |
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| | | | | | | | | | | | |
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| | | | | | | | | | | | |
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| | | | | | | | | | | | |
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| | | | | | | | | | | | |
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| | ------- | | | | | | | | |
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| | | | | | | | | | |
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| | ------- | | Clock | | | | | | |
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| | |PLL1 | | | | | | | | | |
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| |->| | | | Cross | | | | | | |
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| | | odf_0|----|-->| | | | | | CLK_DIV[31:0]
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| | | | | | Bar |====>| |====>| |===|=========>
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| | | | | | | | | | | | |
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| | | | | | | | | | | | |
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| | | | | | | | | | | | |
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| | ------- | | | | | | | | |
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| | | | | | | | | | |
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| | ------- | | | | | | | | |
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| | |QUADFS | | | | | | | | | |
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| |->| ch0|----|-->| | | | | | | |
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| | | | | | | | | | | |
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| | ch1|----|-->| | | | | | | |
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| | | | | | | | | | | |
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| | ch2|----|-->| | | DIV | | DIV | | |
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| | | | | | | 1 to | | 1 to | | |
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| | ch3|----|-->| | | 1024 | | 64 | | |
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| ------- | | | | | | | | |
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| | ------- -------- -------- | |
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| -------------------------------------------- |
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-------------------------------------------------------------------
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This binding uses the common clock binding[2].
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[1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
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[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be:
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"st,flexgen"
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- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
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outputs).
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- clocks : must be set to the parent's phandle. it's could be output clocks of
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a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
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- clock-output-names : List of strings used to name the clock outputs.
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Example:
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clk_s_c0_flexgen: clk-s-c0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen";
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clocks = <&clk_s_c0_pll0 0>,
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<&clk_s_c0_pll1 0>,
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<&clk_s_c0_quadfs 0>,
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<&clk_s_c0_quadfs 1>,
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<&clk_s_c0_quadfs 2>,
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<&clk_s_c0_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-icn-gpu",
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"clk-fdma",
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"clk-nand",
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"clk-hva",
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"clk-proc-stfe",
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"clk-proc-tp",
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"clk-rx-icn-dmu",
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"clk-rx-icn-hva",
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"clk-icn-cpu",
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"clk-tx-icn-dmu",
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"clk-mmc-0",
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"clk-mmc-1",
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"clk-jpegdec",
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"clk-ext2fa9",
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"clk-ic-bdisp-0",
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"clk-ic-bdisp-1",
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"clk-pp-dmu",
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"clk-vid-dmu",
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"clk-dss-lpc",
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"clk-st231-aud-0",
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"clk-st231-gp-1",
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"clk-st231-dmu",
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"clk-icn-lmi",
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"clk-tx-icn-disp-1",
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"clk-icn-sbc",
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"clk-stfe-frc2",
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"clk-eth-phy",
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"clk-eth-ref-phyclk",
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"clk-flash-promip",
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"clk-main-disp",
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"clk-aux-disp",
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"clk-compo-dvp";
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};
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