x86: coding style fixes to arch/x86/kernel/cpu/common.c
Before: total: 55 errors, 6 warnings, 727 lines checked After: total: 0 errors, 3 warnings, 734 lines checked No code changed: arch/x86/kernel/cpu/common.o: text data bss dec hex filename 3500 4611 44 8155 1fdb common.o.before 3500 4611 44 8155 1fdb common.o.after md5: e37091f11fbeb682c0db152ac3022a38 common.o.before.asm e37091f11fbeb682c0db152ac3022a38 common.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Paolo Ciarrocchi
Ingo Molnar
parent
db96598494
commit
34048c9e92
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@ -62,9 +62,9 @@ __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
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static int cachesize_override __cpuinitdata = -1;
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static int disable_x86_serial_nr __cpuinitdata = 1;
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struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
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struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
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static void __cpuinit default_init(struct cpuinfo_x86 * c)
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static void __cpuinit default_init(struct cpuinfo_x86 *c)
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{
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/* Not much we can do here... */
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/* Check if at least it has cpuid */
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@ -81,11 +81,11 @@ static struct cpu_dev __cpuinitdata default_cpu = {
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.c_init = default_init,
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.c_vendor = "Unknown",
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};
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static struct cpu_dev * this_cpu __cpuinitdata = &default_cpu;
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static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
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static int __init cachesize_setup(char *str)
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{
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get_option (&str, &cachesize_override);
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get_option(&str, &cachesize_override);
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return 1;
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}
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__setup("cachesize=", cachesize_setup);
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@ -107,12 +107,12 @@ int __cpuinit get_model_name(struct cpuinfo_x86 *c)
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/* Intel chips right-justify this string for some dumb reason;
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undo that brain damage */
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p = q = &c->x86_model_id[0];
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while ( *p == ' ' )
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while (*p == ' ')
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p++;
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if ( p != q ) {
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while ( *p )
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if (p != q) {
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while (*p)
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*q++ = *p++;
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while ( q <= &c->x86_model_id[48] )
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while (q <= &c->x86_model_id[48])
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*q++ = '\0'; /* Zero-pad the rest */
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}
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@ -130,7 +130,7 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
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printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
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edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
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c->x86_cache_size=(ecx>>24)+(edx>>24);
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c->x86_cache_size = (ecx>>24)+(edx>>24);
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}
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if (n < 0x80000006) /* Some chips just has a large L1. */
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@ -138,16 +138,16 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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ecx = cpuid_ecx(0x80000006);
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l2size = ecx >> 16;
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/* do processor-specific cache resizing */
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if (this_cpu->c_size_cache)
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l2size = this_cpu->c_size_cache(c,l2size);
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l2size = this_cpu->c_size_cache(c, l2size);
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/* Allow user to override all this if necessary. */
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if (cachesize_override != -1)
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l2size = cachesize_override;
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if ( l2size == 0 )
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if (l2size == 0)
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return; /* Again, no L2 cache is possible */
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c->x86_cache_size = l2size;
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@ -156,16 +156,19 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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l2size, ecx & 0xFF);
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}
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/* Naming convention should be: <Name> [(<Codename>)] */
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/* This table only is used unless init_<vendor>() below doesn't set it; */
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/* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
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/*
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* Naming convention should be: <Name> [(<Codename>)]
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* This table only is used unless init_<vendor>() below doesn't set it;
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* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
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*
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*/
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/* Look up CPU names by table lookup. */
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static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
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{
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struct cpu_model_info *info;
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if ( c->x86_model >= 16 )
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if (c->x86_model >= 16)
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return NULL; /* Range check */
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if (!this_cpu)
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@ -190,9 +193,9 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
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for (i = 0; i < X86_VENDOR_NUM; i++) {
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if (cpu_devs[i]) {
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if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
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(cpu_devs[i]->c_ident[1] &&
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!strcmp(v,cpu_devs[i]->c_ident[1]))) {
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if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
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(cpu_devs[i]->c_ident[1] &&
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!strcmp(v, cpu_devs[i]->c_ident[1]))) {
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c->x86_vendor = i;
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if (!early)
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this_cpu = cpu_devs[i];
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@ -210,7 +213,7 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
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}
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static int __init x86_fxsr_setup(char * s)
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static int __init x86_fxsr_setup(char *s)
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{
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setup_clear_cpu_cap(X86_FEATURE_FXSR);
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setup_clear_cpu_cap(X86_FEATURE_XMM);
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@ -219,7 +222,7 @@ static int __init x86_fxsr_setup(char * s)
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__setup("nofxsr", x86_fxsr_setup);
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static int __init x86_sep_setup(char * s)
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static int __init x86_sep_setup(char *s)
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{
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setup_clear_cpu_cap(X86_FEATURE_SEP);
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return 1;
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@ -308,12 +311,15 @@ static void __cpuinit early_get_cap(struct cpuinfo_x86 *c)
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}
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/* Do minimum CPU detection early.
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Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
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The others are not touched to avoid unwanted side effects.
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WARNING: this function is only called on the BP. Don't add code here
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that is supposed to run on all CPUs. */
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/*
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* Do minimum CPU detection early.
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* Fields really needed: vendor, cpuid_level, family, model, mask,
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* cache alignment.
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* The others are not touched to avoid unwanted side effects.
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*
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* WARNING: this function is only called on the BP. Don't add code here
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* that is supposed to run on all CPUs.
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*/
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static void __init early_cpu_detect(void)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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@ -335,7 +341,7 @@ static void __init early_cpu_detect(void)
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early_get_cap(c);
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}
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static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
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static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
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{
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u32 tfms, xlvl;
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unsigned int ebx;
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@ -346,13 +352,12 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
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(unsigned int *)&c->x86_vendor_id[0],
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(unsigned int *)&c->x86_vendor_id[8],
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(unsigned int *)&c->x86_vendor_id[4]);
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get_cpu_vendor(c, 0);
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/* Initialize the standard set of capabilities */
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/* Note that the vendor-specific code below might override */
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/* Intel-defined flags: level 0x00000001 */
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if ( c->cpuid_level >= 0x00000001 ) {
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if (c->cpuid_level >= 0x00000001) {
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u32 capability, excap;
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cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
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c->x86_capability[0] = capability;
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@ -378,12 +383,12 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
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/* AMD-defined flags: level 0x80000001 */
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xlvl = cpuid_eax(0x80000000);
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if ( (xlvl & 0xffff0000) == 0x80000000 ) {
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if ( xlvl >= 0x80000001 ) {
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if ((xlvl & 0xffff0000) == 0x80000000) {
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if (xlvl >= 0x80000001) {
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c->x86_capability[1] = cpuid_edx(0x80000001);
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c->x86_capability[6] = cpuid_ecx(0x80000001);
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}
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if ( xlvl >= 0x80000004 )
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if (xlvl >= 0x80000004)
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get_model_name(c); /* Default name */
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}
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@ -397,12 +402,12 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
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static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
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{
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if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
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if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
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/* Disable processor serial number */
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unsigned long lo,hi;
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rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
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unsigned long lo, hi;
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rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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lo |= 0x200000;
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wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
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wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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printk(KERN_NOTICE "CPU serial number disabled.\n");
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clear_bit(X86_FEATURE_PN, c->x86_capability);
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@ -439,9 +444,11 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
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memset(&c->x86_capability, 0, sizeof c->x86_capability);
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if (!have_cpuid_p()) {
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/* First of all, decide if this is a 486 or higher */
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/* It's a 486 if we can modify the AC flag */
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if ( flag_is_changeable_p(X86_EFLAGS_AC) )
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/*
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* First of all, decide if this is a 486 or higher
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* It's a 486 if we can modify the AC flag
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*/
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if (flag_is_changeable_p(X86_EFLAGS_AC))
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c->x86 = 4;
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else
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c->x86 = 3;
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@ -474,10 +481,10 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
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*/
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/* If the model name is still unset, do table lookup. */
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if ( !c->x86_model_id[0] ) {
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if (!c->x86_model_id[0]) {
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char *p;
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p = table_lookup_model(c);
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if ( p )
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if (p)
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strcpy(c->x86_model_id, p);
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else
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/* Last resort... */
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@ -491,9 +498,9 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
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* common between the CPUs. The first time this routine gets
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* executed, c == &boot_cpu_data.
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*/
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if ( c != &boot_cpu_data ) {
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if (c != &boot_cpu_data) {
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/* AND the already accumulated flags with these */
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for ( i = 0 ; i < NCAPINTS ; i++ )
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for (i = 0 ; i < NCAPINTS ; i++)
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boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
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}
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@ -537,7 +544,7 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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if (smp_num_siblings == 1) {
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printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
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} else if (smp_num_siblings > 1 ) {
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} else if (smp_num_siblings > 1) {
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if (smp_num_siblings > NR_CPUS) {
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printk(KERN_WARNING "CPU: Unsupported number of the "
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@ -592,7 +599,7 @@ void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
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else
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printk("%s", c->x86_model_id);
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if (c->x86_mask || c->cpuid_level >= 0)
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if (c->x86_mask || c->cpuid_level >= 0)
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printk(" stepping %02x\n", c->x86_mask);
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else
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printk("\n");
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@ -653,7 +660,7 @@ void __cpuinit cpu_init(void)
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{
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int cpu = smp_processor_id();
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struct task_struct *curr = current;
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struct tss_struct * t = &per_cpu(init_tss, cpu);
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struct tss_struct *t = &per_cpu(init_tss, cpu);
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struct thread_struct *thread = &curr->thread;
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if (cpu_test_and_set(cpu, cpu_initialized)) {
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@ -679,7 +686,7 @@ void __cpuinit cpu_init(void)
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enter_lazy_tlb(&init_mm, curr);
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load_sp0(t, thread);
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set_tss_desc(cpu,t);
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set_tss_desc(cpu, t);
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load_TR_desc();
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load_LDT(&init_mm.context);
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