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drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines 

This is required for DP HBR2 test pattern

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland 2016-11-28 17:00:20 -05:00 committed by Alex Deucher
parent 8c27f5c1fd
commit 33503e9e5a
8 changed files with 50 additions and 0 deletions
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8
drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h
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@ -4552,6 +4552,14 @@
#define mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5
#define mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5
#define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5
#define mmDP_DPHY_SCRAM_CNTL 0x4ab6
#define mmDP0_DP_DPHY_SCRAM_CNTL 0x4ab6
#define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6
#define mmDP2_DP_DPHY_SCRAM_CNTL 0x4cb6
#define mmDP3_DP_DPHY_SCRAM_CNTL 0x4db6
#define mmDP4_DP_DPHY_SCRAM_CNTL 0x4eb6
#define mmDP5_DP_DPHY_SCRAM_CNTL 0x4fb6
#define mmDP6_DP_DPHY_SCRAM_CNTL 0x54b6
#define mmDP_DPHY_CRC_EN 0x4ab7
#define mmDP0_DP_DPHY_CRC_EN 0x4ab7
#define mmDP1_DP_DPHY_CRC_EN 0x4bb7

4
drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h
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@ -8690,6 +8690,10 @@
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x10
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x3ff00
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1
#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10

9
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
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@ -4544,6 +4544,15 @@
#define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5
#define mmDP7_DP_DPHY_PRBS_CNTL 0x56b5
#define mmDP8_DP_DPHY_PRBS_CNTL 0x57b5
#define mmDP_DPHY_SCRAM_CNTL 0x4ab6
#define mmDP0_DP_DPHY_SCRAM_CNTL 0x4ab6
#define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6
#define mmDP2_DP_DPHY_SCRAM_CNTL 0x4cb6
#define mmDP3_DP_DPHY_SCRAM_CNTL 0x4db6
#define mmDP4_DP_DPHY_SCRAM_CNTL 0x4eb6
#define mmDP5_DP_DPHY_SCRAM_CNTL 0x4fb6
#define mmDP6_DP_DPHY_SCRAM_CNTL 0x54b6
#define mmDP8_DP_DPHY_SCRAM_CNTL 0x56b6
#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc

4
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
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@ -8366,6 +8366,10 @@
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x10
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x3ff00
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x3ff
#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x8000

9
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h
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@ -5776,6 +5776,15 @@
#define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5
#define mmDP7_DP_DPHY_PRBS_CNTL 0x56b5
#define mmDP8_DP_DPHY_PRBS_CNTL 0x57b5
#define mmDP_DPHY_SCRAM_CNTL 0x4ab6
#define mmDP0_DP_DPHY_SCRAM_CNTL 0x4ab6
#define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6
#define mmDP2_DP_DPHY_SCRAM_CNTL 0x4cb6
#define mmDP3_DP_DPHY_SCRAM_CNTL 0x4db6
#define mmDP4_DP_DPHY_SCRAM_CNTL 0x4eb6
#define mmDP5_DP_DPHY_SCRAM_CNTL 0x4fb6
#define mmDP6_DP_DPHY_SCRAM_CNTL 0x54b6
#define mmDP8_DP_DPHY_SCRAM_CNTL 0x56b6
#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc

4
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h
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@ -9628,6 +9628,10 @@
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x10
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x3ff00
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x3ff
#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x8000

8
drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h
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@ -3920,6 +3920,14 @@
#define mmDP4_DP_DPHY_PRBS_CNTL 0x48d4
#define mmDP5_DP_DPHY_PRBS_CNTL 0x4bd4
#define mmDP6_DP_DPHY_PRBS_CNTL 0x4ed4
#define mmDP_DPHY_SCRAM_CNTL 0x1cd5
#define mmDP0_DP_DPHY_SCRAM_CNTL 0x1cd5
#define mmDP1_DP_DPHY_SCRAM_CNTL 0x1fd5
#define mmDP2_DP_DPHY_SCRAM_CNTL 0x42d5
#define mmDP3_DP_DPHY_SCRAM_CNTL 0x45d5
#define mmDP4_DP_DPHY_SCRAM_CNTL 0x48d5
#define mmDP5_DP_DPHY_SCRAM_CNTL 0x4bd5
#define mmDP6_DP_DPHY_SCRAM_CNTL 0x4ed5
#define mmDP_DPHY_CRC_EN 0x1cd6
#define mmDP0_DP_DPHY_CRC_EN 0x1cd6
#define mmDP1_DP_DPHY_CRC_EN 0x1fd6

4
drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h
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@ -9214,6 +9214,10 @@
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00
#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x10
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x3ff00
#define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1
#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10