pwm: mtk-disp: Fix overflow in period and duty calculation
Current calculation for period and high_width may have 64-bit overflow. state->period and rate are u64. rate * state->period will overflow. clk_div = div_u64(rate * state->period, NSEC_PER_SEC) period = div64_u64(rate * state->period, div); high_width = div64_u64(rate * state->duty_cycle, div); This patch is to resolve it by using mul_u64_u64_div_u64(). Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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@ -119,7 +119,7 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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* high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
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*/
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rate = clk_get_rate(mdp->clk_main);
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clk_div = div_u64(rate * state->period, NSEC_PER_SEC) >>
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clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
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PWM_PERIOD_BIT_WIDTH;
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if (clk_div > PWM_CLKDIV_MAX) {
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if (!mdp->enabled) {
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@ -130,11 +130,11 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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}
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div = NSEC_PER_SEC * (clk_div + 1);
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period = div64_u64(rate * state->period, div);
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period = mul_u64_u64_div_u64(state->period, rate, div);
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if (period > 0)
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period--;
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high_width = div64_u64(rate * state->duty_cycle, div);
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high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div);
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value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
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mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
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