tools/headers: Pick up latest kernel ABIs
Sync KVM ABI additions and x86 CPU features additions - neither of which has any impact on the tooling build. Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Jiri Olsa <jolsa@redhat.com> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -91,6 +91,7 @@ struct kvm_regs {
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#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
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#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
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#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
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#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
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#define KVM_VGIC_ITS_ADDR_TYPE 4
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#define KVM_VGIC_ITS_ADDR_TYPE 4
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#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5
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#define KVM_VGIC_V3_DIST_SIZE SZ_64K
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#define KVM_VGIC_V3_DIST_SIZE SZ_64K
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#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
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#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
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@ -91,6 +91,7 @@ struct kvm_regs {
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#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
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#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
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#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
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#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
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#define KVM_VGIC_ITS_ADDR_TYPE 4
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#define KVM_VGIC_ITS_ADDR_TYPE 4
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#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5
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#define KVM_VGIC_V3_DIST_SIZE SZ_64K
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#define KVM_VGIC_V3_DIST_SIZE SZ_64K
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#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
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#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
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@ -633,6 +633,7 @@ struct kvm_ppc_cpu_char {
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#define KVM_REG_PPC_PSSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
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#define KVM_REG_PPC_PSSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
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#define KVM_REG_PPC_DEC_EXPIRY (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe)
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#define KVM_REG_PPC_DEC_EXPIRY (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe)
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#define KVM_REG_PPC_ONLINE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf)
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/* Transactional Memory checkpointed state:
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/* Transactional Memory checkpointed state:
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* This is all GPRs, all VSX regs and a subset of SPRs
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* This is all GPRs, all VSX regs and a subset of SPRs
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@ -282,7 +282,9 @@
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#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
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#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
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#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
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#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
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#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */
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#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
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#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
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#define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
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/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
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/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
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#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
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#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
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@ -948,6 +948,7 @@ struct kvm_ppc_resize_hpt {
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#define KVM_CAP_S390_BPB 152
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#define KVM_CAP_S390_BPB 152
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#define KVM_CAP_GET_MSR_FEATURES 153
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#define KVM_CAP_GET_MSR_FEATURES 153
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#define KVM_CAP_HYPERV_EVENTFD 154
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#define KVM_CAP_HYPERV_EVENTFD 154
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#define KVM_CAP_HYPERV_TLBFLUSH 155
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#ifdef KVM_CAP_IRQ_ROUTING
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#ifdef KVM_CAP_IRQ_ROUTING
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