ARM: shmobile: r8a7779: split r8a7779_init_irq_extpin() for DT
r8a7779 INTC needs IRL pin mode settings to determine behavior of IRQ0 - IRQ3, and r8a7779_init_irq_extpin() is controlling it via irlm parameter. But this function registers renesas_intc_irqpin driver if irlm was set, and this value depends on platform. This is not good for DT. This patch splits r8a7779_init_irq_extpin() function into "mode settings" and "funtion register" parts Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -33,6 +33,7 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
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extern void r8a7779_init_delay(void);
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extern void r8a7779_init_irq_extpin(int irlm);
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extern void r8a7779_init_irq_extpin_dt(int irlm);
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extern void r8a7779_init_irq_dt(void);
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extern void r8a7779_map_io(void);
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extern void r8a7779_earlytimer_init(void);
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@ -98,7 +98,7 @@ static struct resource irqpin0_resources[] __initdata = {
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DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
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};
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void __init r8a7779_init_irq_extpin(int irlm)
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void __init r8a7779_init_irq_extpin_dt(int irlm)
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{
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void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
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u32 tmp;
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@ -116,7 +116,11 @@ void __init r8a7779_init_irq_extpin(int irlm)
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tmp |= (1 << 21); /* LVLMODE = 1 */
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iowrite32(tmp, icr0);
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iounmap(icr0);
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}
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void __init r8a7779_init_irq_extpin(int irlm)
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{
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r8a7779_init_irq_extpin_dt(irlm);
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if (irlm)
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platform_device_register_resndata(
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&platform_bus, "renesas_intc_irqpin", -1,
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