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drm fixes for -rc1: 

nouveau:
 - bugfixes + TU116 enabling (minor iteration):w
 
 amdgpu:
 - large pile of fixes for new hw support this release (navi, vega20)
 - audio hotplug fix
 - bunch of corner cases and small fixes all over for amdgpu/kfd
 
 komeda:
 - back out some new properties (from this merge window) that needs
   more pondering.
 
 bochs: fb pitch setup
 
 ... plus a new panel quirk
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Merge tag 'drm-next-2019-07-19' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Daniel Vetter:
 "Dave is back in shape, but now family got it so I'm doing the pull.
  Two things worthy of note:

   - nouveau feature pull was way too late, Dave&me decided to not take
     that, so Ben spun up a pull with just the fixes.

   - after some chatting with the arm display maintainers we decided to
     change a bit how that's maintained, for more oversight/review and
     cross vendor collab.

  More details below:

  nouveau:
   - bugfixes
   - TU116 enabling (minor iteration) :w

  amdgpu:
   - large pile of fixes for new hw support this release (navi, vega20)
   - audio hotplug fix
   - bunch of corner cases and small fixes all over for amdgpu/kfd

  komeda:
   - back out some new properties (from this merge window) that needs
     more pondering.

  bochs:
   - fb pitch setup

  core:
   - a new panel quirk
   - misc fixes"

* tag 'drm-next-2019-07-19' of git://anongit.freedesktop.org/drm/drm: (73 commits)
  drm/nouveau/secboot/gp102-: remove WAR for SEC2 RTOS start bug
  drm/nouveau/flcn/gp102-: improve implementation of bind_context() on SEC2/GSP
  drm/nouveau: fix memory leak in nouveau_conn_reset()
  drm/nouveau/dmem: missing mutex_lock in error path
  drm/nouveau/hwmon: return EINVAL if the GPU is powered down for sensors reads
  drm/nouveau: fix bogus GPL-2 license header
  drm/nouveau: fix bogus GPL-2 license header
  drm/nouveau/i2c: Enable i2c pads & busses during preinit
  drm/nouveau/disp/tu102-: wire up scdc parameter setter
  drm/nouveau/core: recognise TU116 chipset
  drm/nouveau/kms: disallow dual-link harder if hdmi connection detected
  drm/nouveau/disp/nv50-: fix center/aspect-corrected scaling
  drm/nouveau/disp/nv50-: force scaler for any non-default LVDS/eDP modes
  drm/nouveau/mcp89/mmu: Use mcp77_mmu_new instead of g84_mmu_new on MCP89.
  drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq
  drm/amdgpu/pm: remove check for pp funcs in freq sysfs handlers
  drm/amd/display: Force uclk to max for every state
  drm/amdkfd: Remove GWS from process during uninit
  drm/amd/amdgpu: Fix offset for vmid selection in debugfs interface
  drm/amd/powerplay: update vega20 driver if to fit latest SMU firmware
  ...
This commit is contained in:
Linus Torvalds 2019-07-19 12:29:43 -07:00
parent dd4542d282 8ee7956256
commit 31cc088a4f
412 changed files with 1253 additions and 904 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
MAINTAINERS
View File

@ -1236,7 +1236,7 @@ M: James (Qian) Wang <james.qian.wang@arm.com>
M: Liviu Dudau <liviu.dudau@arm.com> M: Liviu Dudau <liviu.dudau@arm.com>
L: Mali DP Maintainers <malidp@foss.arm.com> L: Mali DP Maintainers <malidp@foss.arm.com>
S: Supported S: Supported
T: git git://linux-arm.org/linux-ld.git for-upstream/mali-dp T: git git://anongit.freedesktop.org/drm/drm-misc
F: drivers/gpu/drm/arm/display/include/ F: drivers/gpu/drm/arm/display/include/
F: drivers/gpu/drm/arm/display/komeda/ F: drivers/gpu/drm/arm/display/komeda/
F: Documentation/devicetree/bindings/display/arm,komeda.txt F: Documentation/devicetree/bindings/display/arm,komeda.txt
@ -1247,7 +1247,7 @@ M: Liviu Dudau <liviu.dudau@arm.com>
M: Brian Starkey <brian.starkey@arm.com> M: Brian Starkey <brian.starkey@arm.com>
L: Mali DP Maintainers <malidp@foss.arm.com> L: Mali DP Maintainers <malidp@foss.arm.com>
S: Supported S: Supported
T: git git://linux-arm.org/linux-ld.git for-upstream/mali-dp T: git git://anongit.freedesktop.org/drm/drm-misc
F: drivers/gpu/drm/arm/ F: drivers/gpu/drm/arm/
F: Documentation/devicetree/bindings/display/arm,malidp.txt F: Documentation/devicetree/bindings/display/arm,malidp.txt
F: Documentation/gpu/afbc.rst F: Documentation/gpu/afbc.rst

1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@ -164,6 +164,7 @@ extern int amdgpu_async_gfx_ring;
extern int amdgpu_mcbp; extern int amdgpu_mcbp;
extern int amdgpu_discovery; extern int amdgpu_discovery;
extern int amdgpu_mes; extern int amdgpu_mes;
extern int amdgpu_noretry;
#ifdef CONFIG_DRM_AMDGPU_SI #ifdef CONFIG_DRM_AMDGPU_SI
extern int amdgpu_si_support; extern int amdgpu_si_support;

9
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
View File

@ -106,10 +106,10 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
ssize_t result = 0; ssize_t result = 0;
int r; int r;
bool pm_pg_lock, use_bank, use_ring; bool pm_pg_lock, use_bank, use_ring;
unsigned instance_bank, sh_bank, se_bank, me, pipe, queue; unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
pm_pg_lock = use_bank = use_ring = false; pm_pg_lock = use_bank = use_ring = false;
instance_bank = sh_bank = se_bank = me = pipe = queue = 0; instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
if (size & 0x3 || *pos & 0x3 || if (size & 0x3 || *pos & 0x3 ||
((*pos & (1ULL << 62)) && (*pos & (1ULL << 61)))) ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
@ -135,6 +135,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
me = (*pos & GENMASK_ULL(33, 24)) >> 24; me = (*pos & GENMASK_ULL(33, 24)) >> 24;
pipe = (*pos & GENMASK_ULL(43, 34)) >> 34; pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
queue = (*pos & GENMASK_ULL(53, 44)) >> 44; queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
use_ring = 1; use_ring = 1;
} else { } else {
@ -152,7 +153,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
sh_bank, instance_bank); sh_bank, instance_bank);
} else if (use_ring) { } else if (use_ring) {
mutex_lock(&adev->srbm_mutex); mutex_lock(&adev->srbm_mutex);
amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue); amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
} }
if (pm_pg_lock) if (pm_pg_lock)
@ -185,7 +186,7 @@ end:
amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
mutex_unlock(&adev->grbm_idx_mutex); mutex_unlock(&adev->grbm_idx_mutex);
} else if (use_ring) { } else if (use_ring) {
amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0); amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex); mutex_unlock(&adev->srbm_mutex);
} }

1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -2537,6 +2537,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
hash_init(adev->mn_hash); hash_init(adev->mn_hash);
mutex_init(&adev->lock_reset); mutex_init(&adev->lock_reset);
mutex_init(&adev->virt.dpm_mutex); mutex_init(&adev->virt.dpm_mutex);
mutex_init(&adev->psp.mutex);
r = amdgpu_device_check_arguments(adev); r = amdgpu_device_check_arguments(adev);
if (r) if (r)

2
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
View File

@ -123,7 +123,7 @@ static int hw_id_map[MAX_HWIP] = {
[UVD_HWIP] = UVD_HWID, [UVD_HWIP] = UVD_HWID,
[VCE_HWIP] = VCE_HWID, [VCE_HWIP] = VCE_HWID,
[DF_HWIP] = DF_HWID, [DF_HWIP] = DF_HWID,
[DCE_HWIP] = DCEAZ_HWID, [DCE_HWIP] = DMU_HWID,
[OSSSYS_HWIP] = OSSSYS_HWID, [OSSSYS_HWIP] = OSSSYS_HWID,
[SMUIO_HWIP] = SMUIO_HWID, [SMUIO_HWIP] = SMUIO_HWID,
[PWR_HWIP] = PWR_HWID, [PWR_HWIP] = PWR_HWID,

19
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View File

@ -140,8 +140,9 @@ uint amdgpu_smu_memory_pool_size = 0;
uint amdgpu_dc_feature_mask = 0; uint amdgpu_dc_feature_mask = 0;
int amdgpu_async_gfx_ring = 1; int amdgpu_async_gfx_ring = 1;
int amdgpu_mcbp = 0; int amdgpu_mcbp = 0;
int amdgpu_discovery = 0; int amdgpu_discovery = -1;
int amdgpu_mes = 0; int amdgpu_mes = 0;
int amdgpu_noretry;
struct amdgpu_mgpu_info mgpu_info = { struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@ -593,6 +594,7 @@ module_param_named(mcbp, amdgpu_mcbp, int, 0444);
/** /**
* DOC: discovery (int) * DOC: discovery (int)
* Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
* (-1 = auto (default), 0 = disabled, 1 = enabled)
*/ */
MODULE_PARM_DESC(discovery, MODULE_PARM_DESC(discovery,
"Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
@ -607,6 +609,10 @@ MODULE_PARM_DESC(mes,
"Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
module_param_named(mes, amdgpu_mes, int, 0444); module_param_named(mes, amdgpu_mes, int, 0444);
MODULE_PARM_DESC(noretry,
"Disable retry faults (0 = retry enabled (default), 1 = retry disabled)");
module_param_named(noretry, amdgpu_noretry, int, 0644);
#ifdef CONFIG_HSA_AMD #ifdef CONFIG_HSA_AMD
/** /**
* DOC: sched_policy (int) * DOC: sched_policy (int)
@ -682,17 +688,6 @@ module_param(ignore_crat, int, 0444);
MODULE_PARM_DESC(ignore_crat, MODULE_PARM_DESC(ignore_crat,
"Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
/**
* DOC: noretry (int)
* This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry.
* Setting 1 disables retry.
* Retry is needed for recoverable page faults.
*/
int noretry;
module_param(noretry, int, 0644);
MODULE_PARM_DESC(noretry,
"Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)");
/** /**
* DOC: halt_if_hws_hang (int) * DOC: halt_if_hws_hang (int)
* Halt if HWS hang is detected. Default value, 0, disables the halt on hang. * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.

4
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
View File

@ -195,7 +195,7 @@ struct amdgpu_gfx_funcs {
uint32_t wave, uint32_t start, uint32_t size, uint32_t wave, uint32_t start, uint32_t size,
uint32_t *dst); uint32_t *dst);
void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
u32 queue); u32 queue, u32 vmid);
}; };
struct amdgpu_ngg_buf { struct amdgpu_ngg_buf {
@ -327,7 +327,7 @@ struct amdgpu_gfx {
#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q)) #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
/** /**
* amdgpu_gfx_create_bitmask - create a bitmask * amdgpu_gfx_create_bitmask - create a bitmask

13
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
View File

@ -2077,11 +2077,6 @@ static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL; return -EINVAL;
/* sanity check PP is enabled */
if (!(adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->read_sensor))
return -EINVAL;
/* get the sclk */ /* get the sclk */
r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
(void *)&sclk, &size); (void *)&sclk, &size);
@ -2112,11 +2107,6 @@ static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL; return -EINVAL;
/* sanity check PP is enabled */
if (!(adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->read_sensor))
return -EINVAL;
/* get the sclk */ /* get the sclk */
r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
(void *)&mclk, &size); (void *)&mclk, &size);
@ -2996,13 +2986,10 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
} }
if (is_support_sw_smu(adev)) { if (is_support_sw_smu(adev)) {
struct smu_context *smu = &adev->smu;
struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm; struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
mutex_lock(&(smu->mutex));
smu_handle_task(&adev->smu, smu_handle_task(&adev->smu,
smu_dpm->dpm_level, smu_dpm->dpm_level,
AMD_PP_TASK_DISPLAY_CONFIG_CHANGE); AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
mutex_unlock(&(smu->mutex));
} else { } else {
if (adev->powerplay.pp_funcs->dispatch_tasks) { if (adev->powerplay.pp_funcs->dispatch_tasks) {
if (!amdgpu_device_has_dc_support(adev)) { if (!amdgpu_device_has_dc_support(adev)) {

25
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View File

@ -130,6 +130,8 @@ psp_cmd_submit_buf(struct psp_context *psp,
int index; int index;
int timeout = 2000; int timeout = 2000;
mutex_lock(&psp->mutex);
memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
@ -139,6 +141,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
fence_mc_addr, index); fence_mc_addr, index);
if (ret) { if (ret) {
atomic_dec(&psp->fence_value); atomic_dec(&psp->fence_value);
mutex_unlock(&psp->mutex);
return ret; return ret;
} }
@ -161,8 +164,10 @@ psp_cmd_submit_buf(struct psp_context *psp,
ucode->ucode_id); ucode->ucode_id);
DRM_WARN("psp command failed and response status is (%d)\n", DRM_WARN("psp command failed and response status is (%d)\n",
psp->cmd_buf_mem->resp.status); psp->cmd_buf_mem->resp.status);
if (!timeout) if (!timeout) {
mutex_unlock(&psp->mutex);
return -EINVAL; return -EINVAL;
}
} }
/* get xGMI session id from response buffer */ /* get xGMI session id from response buffer */
@ -172,6 +177,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
} }
mutex_unlock(&psp->mutex);
return ret; return ret;
} }
@ -763,6 +769,15 @@ static int psp_hw_start(struct psp_context *psp)
int ret; int ret;
if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
if (psp->kdb_bin_size &&
(psp->funcs->bootloader_load_kdb != NULL)) {
ret = psp_bootloader_load_kdb(psp);
if (ret) {
DRM_ERROR("PSP load kdb failed!\n");
return ret;
}
}
ret = psp_bootloader_load_sysdrv(psp); ret = psp_bootloader_load_sysdrv(psp);
if (ret) { if (ret) {
DRM_ERROR("PSP load sysdrv failed!\n"); DRM_ERROR("PSP load sysdrv failed!\n");
@ -1188,10 +1203,16 @@ failed:
int psp_gpu_reset(struct amdgpu_device *adev) int psp_gpu_reset(struct amdgpu_device *adev)
{ {
int ret;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
return 0; return 0;
return psp_mode1_reset(&adev->psp); mutex_lock(&adev->psp.mutex);
ret = psp_mode1_reset(&adev->psp);
mutex_unlock(&adev->psp.mutex);
return ret;
} }
int psp_rlc_autoload_start(struct psp_context *psp) int psp_rlc_autoload_start(struct psp_context *psp)

12
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
View File

@ -42,6 +42,12 @@ struct psp_context;
struct psp_xgmi_node_info; struct psp_xgmi_node_info;
struct psp_xgmi_topology_info; struct psp_xgmi_topology_info;
enum psp_bootloader_cmd {
PSP_BL__LOAD_SYSDRV = 0x10000,
PSP_BL__LOAD_SOSDRV = 0x20000,
PSP_BL__LOAD_KEY_DATABASE = 0x80000,
};
enum psp_ring_type enum psp_ring_type
{ {
PSP_RING_TYPE__INVALID = 0, PSP_RING_TYPE__INVALID = 0,
@ -73,6 +79,7 @@ enum psp_reg_prog_id {
struct psp_funcs struct psp_funcs
{ {
int (*init_microcode)(struct psp_context *psp); int (*init_microcode)(struct psp_context *psp);
int (*bootloader_load_kdb)(struct psp_context *psp);
int (*bootloader_load_sysdrv)(struct psp_context *psp); int (*bootloader_load_sysdrv)(struct psp_context *psp);
int (*bootloader_load_sos)(struct psp_context *psp); int (*bootloader_load_sos)(struct psp_context *psp);
int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
@ -156,9 +163,11 @@ struct psp_context
uint32_t sys_bin_size; uint32_t sys_bin_size;
uint32_t sos_bin_size; uint32_t sos_bin_size;
uint32_t toc_bin_size; uint32_t toc_bin_size;
uint32_t kdb_bin_size;
uint8_t *sys_start_addr; uint8_t *sys_start_addr;
uint8_t *sos_start_addr; uint8_t *sos_start_addr;
uint8_t *toc_start_addr; uint8_t *toc_start_addr;
uint8_t *kdb_start_addr;
/* tmr buffer */ /* tmr buffer */
struct amdgpu_bo *tmr_bo; struct amdgpu_bo *tmr_bo;
@ -201,6 +210,7 @@ struct psp_context
uint8_t *ta_ras_start_addr; uint8_t *ta_ras_start_addr;
struct psp_xgmi_context xgmi_context; struct psp_xgmi_context xgmi_context;
struct psp_ras_context ras; struct psp_ras_context ras;
struct mutex mutex;
}; };
struct amdgpu_psp_funcs { struct amdgpu_psp_funcs {
@ -219,6 +229,8 @@ struct amdgpu_psp_funcs {
(psp)->funcs->compare_sram_data((psp), (ucode), (type)) (psp)->funcs->compare_sram_data((psp), (ucode), (type))
#define psp_init_microcode(psp) \ #define psp_init_microcode(psp) \
((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
#define psp_bootloader_load_kdb(psp) \
((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
#define psp_bootloader_load_sysdrv(psp) \ #define psp_bootloader_load_sysdrv(psp) \
((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
#define psp_bootloader_load_sos(psp) \ #define psp_bootloader_load_sos(psp) \

51
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
View File

@ -391,6 +391,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm, src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
src->mem); src->mem);
src_node_size = (src_mm->size << PAGE_SHIFT); src_node_size = (src_mm->size << PAGE_SHIFT);
src_page_offset = 0;
} else { } else {
src_node_start += cur_size; src_node_start += cur_size;
src_page_offset = src_node_start & (PAGE_SIZE - 1); src_page_offset = src_node_start & (PAGE_SIZE - 1);
@ -400,6 +401,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm, dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
dst->mem); dst->mem);
dst_node_size = (dst_mm->size << PAGE_SHIFT); dst_node_size = (dst_mm->size << PAGE_SHIFT);
dst_page_offset = 0;
} else { } else {
dst_node_start += cur_size; dst_node_start += cur_size;
dst_page_offset = dst_node_start & (PAGE_SIZE - 1); dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
@ -487,6 +489,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
if (unlikely(r)) { if (unlikely(r)) {
pr_err("Failed to find GTT space for blit from VRAM\n");
return r; return r;
} }
@ -545,6 +548,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
if (unlikely(r)) { if (unlikely(r)) {
pr_err("Failed to find GTT space for blit to VRAM\n");
return r; return r;
} }
@ -564,6 +568,30 @@ out_cleanup:
return r; return r;
} }
/**
* amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
*
* Called by amdgpu_bo_move()
*/
static bool amdgpu_mem_visible(struct amdgpu_device *adev,
struct ttm_mem_reg *mem)
{
struct drm_mm_node *nodes = mem->mm_node;
if (mem->mem_type == TTM_PL_SYSTEM ||
mem->mem_type == TTM_PL_TT)
return true;
if (mem->mem_type != TTM_PL_VRAM)
return false;
/* ttm_mem_reg_ioremap only supports contiguous memory */
if (nodes->size != mem->num_pages)
return false;
return ((nodes->start + nodes->size) << PAGE_SHIFT)
<= adev->gmc.visible_vram_size;
}
/** /**
* amdgpu_bo_move - Move a buffer object to a new memory location * amdgpu_bo_move - Move a buffer object to a new memory location
* *
@ -608,8 +636,10 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
return 0; return 0;
} }
if (!adev->mman.buffer_funcs_enabled) if (!adev->mman.buffer_funcs_enabled) {
r = -ENODEV;
goto memcpy; goto memcpy;
}
if (old_mem->mem_type == TTM_PL_VRAM && if (old_mem->mem_type == TTM_PL_VRAM &&
new_mem->mem_type == TTM_PL_SYSTEM) { new_mem->mem_type == TTM_PL_SYSTEM) {
@ -624,10 +654,16 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
if (r) { if (r) {
memcpy: memcpy:
r = ttm_bo_move_memcpy(bo, ctx, new_mem); /* Check that all memory is CPU accessible */
if (r) { if (!amdgpu_mem_visible(adev, old_mem) ||
!amdgpu_mem_visible(adev, new_mem)) {
pr_err("Move buffer fallback to memcpy unavailable\n");
return r; return r;
} }
r = ttm_bo_move_memcpy(bo, ctx, new_mem);
if (r)
return r;
} }
if (bo->type == ttm_bo_type_device && if (bo->type == ttm_bo_type_device &&
@ -2059,9 +2095,9 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
mm_node = bo->tbo.mem.mm_node; mm_node = bo->tbo.mem.mm_node;
num_loops = 0; num_loops = 0;
while (num_pages) { while (num_pages) {
uint32_t byte_count = mm_node->size << PAGE_SHIFT; uint64_t byte_count = mm_node->size << PAGE_SHIFT;
num_loops += DIV_ROUND_UP(byte_count, max_bytes); num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
num_pages -= mm_node->size; num_pages -= mm_node->size;
++mm_node; ++mm_node;
} }
@ -2087,12 +2123,13 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
mm_node = bo->tbo.mem.mm_node; mm_node = bo->tbo.mem.mm_node;
while (num_pages) { while (num_pages) {
uint32_t byte_count = mm_node->size << PAGE_SHIFT; uint64_t byte_count = mm_node->size << PAGE_SHIFT;
uint64_t dst_addr; uint64_t dst_addr;
dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem); dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
while (byte_count) { while (byte_count) {
uint32_t cur_size_in_bytes = min(byte_count, max_bytes); uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
max_bytes);
amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
dst_addr, cur_size_in_bytes); dst_addr, cur_size_in_bytes);

6
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
View File

@ -262,6 +262,12 @@ void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes)); le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes));
DRM_DEBUG("toc_size_bytes: %u\n", DRM_DEBUG("toc_size_bytes: %u\n",
le32_to_cpu(psp_hdr_v1_1->toc_size_bytes)); le32_to_cpu(psp_hdr_v1_1->toc_size_bytes));
DRM_DEBUG("kdb_header_version: %u\n",
le32_to_cpu(psp_hdr_v1_1->kdb_header_version));
DRM_DEBUG("kdb_offset_bytes: %u\n",
le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes));
DRM_DEBUG("kdb_size_bytes: %u\n",
le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes));
} }
} else { } else {
DRM_ERROR("Unknown PSP ucode version: %u.%u\n", DRM_ERROR("Unknown PSP ucode version: %u.%u\n",

3
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
View File

@ -85,6 +85,9 @@ struct psp_firmware_header_v1_1 {
uint32_t toc_header_version; uint32_t toc_header_version;
uint32_t toc_offset_bytes; uint32_t toc_offset_bytes;
uint32_t toc_size_bytes; uint32_t toc_size_bytes;
uint32_t kdb_header_version;
uint32_t kdb_offset_bytes;
uint32_t kdb_size_bytes;
}; };
/* version_major=1, version_minor=0 */ /* version_major=1, version_minor=0 */

3
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
View File

@ -390,7 +390,8 @@ static uint32_t parse_clk(char *buf, bool min)
if (!ptr) if (!ptr)
break; break;
ptr+=2; ptr+=2;
clk = simple_strtoul(ptr, NULL, 10); if (kstrtou32(ptr, 10, &clk))
return 0;
} while (!min); } while (!min);
return clk * 100; return clk * 100;

34
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
View File

@ -109,6 +109,13 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
/* Pending on emulation bring up */ /* Pending on emulation bring up */
}; };
#define DEFAULT_SH_MEM_CONFIG \
((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
(SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
(SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
@ -995,6 +1002,12 @@ static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
start + SQIND_WAVE_VGPRS_OFFSET, size, dst); start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
} }
static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 q, u32 vm)
{
nv_grbm_select(adev, me, pipe, q, vm);
}
static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
@ -1002,6 +1015,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
.read_wave_data = &gfx_v10_0_read_wave_data, .read_wave_data = &gfx_v10_0_read_wave_data,
.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
}; };
static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
@ -1408,7 +1422,6 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
{ {
int i; int i;
uint32_t sh_mem_config;
uint32_t sh_mem_bases; uint32_t sh_mem_bases;
/* /*
@ -1419,15 +1432,11 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
*/ */
sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
mutex_lock(&adev->srbm_mutex); mutex_lock(&adev->srbm_mutex);
for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
nv_grbm_select(adev, 0, 0, 0, i); nv_grbm_select(adev, 0, 0, 0, i);
/* CP and shaders */ /* CP and shaders */
WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
} }
nv_grbm_select(adev, 0, 0, 0, 0); nv_grbm_select(adev, 0, 0, 0, 0);
@ -1520,17 +1529,8 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) { for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
nv_grbm_select(adev, 0, 0, 0, i); nv_grbm_select(adev, 0, 0, 0, i);
/* CP and shaders */ /* CP and shaders */
if (i == 0) { WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, if (i != 0) {
SH_MEM_ALIGNMENT_MODE_UNALIGNED);
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_MODE, 0);
WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
} else {
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
SH_MEM_ALIGNMENT_MODE_UNALIGNED);
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_MODE, 0);
WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
(adev->gmc.private_aperture_start >> 48)); (adev->gmc.private_aperture_start >> 48));
tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

2
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
View File

@ -3043,7 +3043,7 @@ static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
} }
static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 q) u32 me, u32 pipe, u32 q, u32 vm)
{ {
DRM_INFO("Not implemented\n"); DRM_INFO("Not implemented\n");
} }

4
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
View File

@ -4169,9 +4169,9 @@ static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
} }
static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev, static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 q) u32 me, u32 pipe, u32 q, u32 vm)
{ {
cik_srbm_select(adev, me, pipe, q, 0); cik_srbm_select(adev, me, pipe, q, vm);
} }
static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {

4
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
View File

@ -3436,9 +3436,9 @@ static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
} }
static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev, static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 q) u32 me, u32 pipe, u32 q, u32 vm)
{ {
vi_srbm_select(adev, me, pipe, q, 0); vi_srbm_select(adev, me, pipe, q, vm);
} }
static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev) static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)

8
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@ -1313,9 +1313,9 @@ static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
} }
static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 q) u32 me, u32 pipe, u32 q, u32 vm)
{ {
soc15_grbm_select(adev, me, pipe, q, 0); soc15_grbm_select(adev, me, pipe, q, vm);
} }
static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
@ -1942,11 +1942,15 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
if (i == 0) { if (i == 0) {
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
SH_MEM_ALIGNMENT_MODE_UNALIGNED); SH_MEM_ALIGNMENT_MODE_UNALIGNED);
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
!!amdgpu_noretry);
WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0);
} else { } else {
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
SH_MEM_ALIGNMENT_MODE_UNALIGNED); SH_MEM_ALIGNMENT_MODE_UNALIGNED);
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
!!amdgpu_noretry);
WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
(adev->gmc.private_aperture_start >> 48)); (adev->gmc.private_aperture_start >> 48));

3
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
View File

@ -236,7 +236,8 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
block_size); block_size);
/* Send no-retry XNACK on fault to suppress VM fault storm. */ /* Send no-retry XNACK on fault to suppress VM fault storm. */
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 1); RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
!amdgpu_noretry);
WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp); WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);

3
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
View File

@ -215,7 +215,8 @@ static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
adev->vm_manager.block_size - 9); adev->vm_manager.block_size - 9);
/* Send no-retry XNACK on fault to suppress VM fault storm. */ /* Send no-retry XNACK on fault to suppress VM fault storm. */
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
!amdgpu_noretry);
WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp); WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp);
WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);

3
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
View File

@ -265,7 +265,8 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
block_size); block_size);
/* Send no-retry XNACK on fault to suppress VM fault storm. */ /* Send no-retry XNACK on fault to suppress VM fault storm. */
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 1); RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
!amdgpu_noretry);
WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp); WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);

3
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
View File

@ -205,7 +205,8 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
adev->vm_manager.block_size - 9); adev->vm_manager.block_size - 9);
/* Send no-retry XNACK on fault to suppress VM fault storm. */ /* Send no-retry XNACK on fault to suppress VM fault storm. */
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
!amdgpu_noretry);
WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp); WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp);
WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);

2
drivers/gpu/drm/amd/amdgpu/nv.c
View File

@ -392,8 +392,6 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_device_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#else
# warning "Enable CONFIG_DRM_AMD_DC for display support on navi."
#endif #endif
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);

52
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
View File

@ -103,6 +103,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
} }
break; break;
default: default:
@ -177,6 +180,48 @@ out:
return err; return err;
} }
static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
{
int ret;
uint32_t psp_gfxdrv_command_reg = 0;
struct amdgpu_device *adev = psp->adev;
uint32_t sol_reg;
/* Check tOS sign of life register to confirm sys driver and sOS
* are already been loaded.
*/
sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
if (sol_reg) {
psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
return 0;
}
/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
0x80000000, 0x80000000, false);
if (ret)
return ret;
memset(psp->fw_pri_buf, 0, PSP_1_MEG);
/* Copy PSP KDB binary to memory */
memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
/* Provide the sys driver to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20));
psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg);
/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1*/
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
0x80000000, 0x80000000, false);
return ret;
}
static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
{ {
int ret; int ret;
@ -190,7 +235,7 @@ static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
if (sol_reg) { if (sol_reg) {
psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
printk("sos fw version = 0x%x.\n", psp->sos_fw_version); dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
return 0; return 0;
} }
@ -208,7 +253,7 @@ static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
/* Provide the sys driver to bootloader */ /* Provide the sys driver to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20)); (uint32_t)(psp->fw_pri_mc_addr >> 20));
psp_gfxdrv_command_reg = 1 << 16; psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg); psp_gfxdrv_command_reg);
@ -249,7 +294,7 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
/* Provide the PSP secure OS to bootloader */ /* Provide the PSP secure OS to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20)); (uint32_t)(psp->fw_pri_mc_addr >> 20));
psp_gfxdrv_command_reg = 2 << 16; psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg); psp_gfxdrv_command_reg);
@ -822,6 +867,7 @@ static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
static const struct psp_funcs psp_v11_0_funcs = { static const struct psp_funcs psp_v11_0_funcs = {
.init_microcode = psp_v11_0_init_microcode, .init_microcode = psp_v11_0_init_microcode,
.bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
.bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
.bootloader_load_sos = psp_v11_0_bootloader_load_sos, .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
.ring_init = psp_v11_0_ring_init, .ring_init = psp_v11_0_ring_init,

4
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
View File

@ -155,7 +155,7 @@ static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
/* Provide the sys driver to bootloader */ /* Provide the sys driver to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20)); (uint32_t)(psp->fw_pri_mc_addr >> 20));
psp_gfxdrv_command_reg = 1 << 16; psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg); psp_gfxdrv_command_reg);
@ -218,7 +218,7 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
/* Provide the PSP secure OS to bootloader */ /* Provide the PSP secure OS to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20)); (uint32_t)(psp->fw_pri_mc_addr >> 20));
psp_gfxdrv_command_reg = 2 << 16; psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg); psp_gfxdrv_command_reg);

14
drivers/gpu/drm/amd/amdgpu/soc15.c
View File

@ -649,8 +649,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_device_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#else
# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif #endif
if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
@ -671,8 +669,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_device_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#else
# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif #endif
amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
break; break;
@ -717,9 +713,15 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
return; return;
/* Set the 2 events that we wish to watch, defined above */ /* Set the 2 events that we wish to watch, defined above */
/* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ /* Reg 40 is # received msgs */
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); /* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */
if (adev->asic_type == CHIP_VEGA20)
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
EVENT1_SEL, 108);
else
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
EVENT1_SEL, 104);
/* Write to enable desired perf counters */ /* Write to enable desired perf counters */
WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);

1
drivers/gpu/drm/amd/amdgpu/vi.c
View File

@ -59,7 +59,6 @@
#include "vid.h" #include "vid.h"
#include "vi.h" #include "vi.h"
#include "vi_dpm.h"
#include "gmc_v8_0.h" #include "gmc_v8_0.h"
#include "gmc_v7_0.h" #include "gmc_v7_0.h"
#include "gfx_v8_0.h" #include "gfx_v8_0.h"

32
drivers/gpu/drm/amd/amdgpu/vi_dpm.h
View File

@ -1,32 +0,0 @@
/*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __VI_DPM_H__
#define __VI_DPM_H__
extern const struct amd_ip_funcs cz_dpm_ip_funcs;
int cz_smu_init(struct amdgpu_device *adev);
int cz_smu_start(struct amdgpu_device *adev);
int cz_smu_fini(struct amdgpu_device *adev);
#endif

16
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
View File

@ -1157,12 +1157,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
q->properties.type)]; q->properties.type)];
/*
* Eviction state logic: mark all queues as evicted, even ones
* not currently active. Restoring inactive queues later only
* updates the is_evicted flag but is a no-op otherwise.
*/
q->properties.is_evicted = !!qpd->evicted;
if (q->properties.type == KFD_QUEUE_TYPE_SDMA || if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
dqm->asic_ops.init_sdma_vm(dqm, q, qpd); dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
@ -1173,9 +1168,16 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
retval = -ENOMEM; retval = -ENOMEM;
goto out_deallocate_doorbell; goto out_deallocate_doorbell;
} }
dqm_lock(dqm);
/*
* Eviction state logic: mark all queues as evicted, even ones
* not currently active. Restoring inactive queues later only
* updates the is_evicted flag but is a no-op otherwise.
*/
q->properties.is_evicted = !!qpd->evicted;
mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
&q->gart_mqd_addr, &q->properties); &q->gart_mqd_addr, &q->properties);
dqm_lock(dqm);
list_add(&q->list, &qpd->queues_list); list_add(&q->list, &qpd->queues_list);
qpd->queue_count++; qpd->queue_count++;

2
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
View File

@ -61,7 +61,7 @@ static int update_qpd_v9(struct device_queue_manager *dqm,
qpd->sh_mem_config = qpd->sh_mem_config =
SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
if (noretry && if (amdgpu_noretry &&
!dqm->dev->device_info->needs_iommu_device) !dqm->dev->device_info->needs_iommu_device)
qpd->sh_mem_config |= qpd->sh_mem_config |=
1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;

2
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
View File

@ -157,7 +157,7 @@ extern int ignore_crat;
/* /*
* Set sh_mem_config.retry_disable on Vega10 * Set sh_mem_config.retry_disable on Vega10
*/ */
extern int noretry; extern int amdgpu_noretry;
/* /*
* Halt if HWS hang is detected * Halt if HWS hang is detected

3
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
View File

@ -150,6 +150,9 @@ void pqm_uninit(struct process_queue_manager *pqm)
struct process_queue_node *pqn, *next; struct process_queue_node *pqn, *next;
list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) {
if (pqn->q && pqn->q->gws)
amdgpu_amdkfd_remove_gws_from_process(pqm->process->kgd_process_info,
pqn->q->gws);
uninit_queue(pqn->q); uninit_queue(pqn->q);
list_del(&pqn->process_queue_list); list_del(&pqn->process_queue_list);
kfree(pqn); kfree(pqn);

1
drivers/gpu/drm/amd/display/Kconfig
View File

@ -5,6 +5,7 @@ menu "Display Engine Configuration"
config DRM_AMD_DC config DRM_AMD_DC
bool "AMD DC - Enable new display engine" bool "AMD DC - Enable new display engine"
default y default y
select SND_HDA_COMPONENT if SND_HDA_CORE
select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
help help
Choose this option if you want to use the new display engine Choose this option if you want to use the new display engine

222
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -56,6 +56,7 @@
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/firmware.h> #include <linux/firmware.h>
#include <linux/component.h>
#include <drm/drm_atomic.h> #include <drm/drm_atomic.h>
#include <drm/drm_atomic_uapi.h> #include <drm/drm_atomic_uapi.h>
@ -65,6 +66,7 @@
#include <drm/drm_fourcc.h> #include <drm/drm_fourcc.h>
#include <drm/drm_edid.h> #include <drm/drm_edid.h>
#include <drm/drm_vblank.h> #include <drm/drm_vblank.h>
#include <drm/drm_audio_component.h>
#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
@ -508,6 +510,139 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector)
} }
static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
int pipe, bool *enabled,
unsigned char *buf, int max_bytes)
{
struct drm_device *dev = dev_get_drvdata(kdev);
struct amdgpu_device *adev = dev->dev_private;
struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
struct amdgpu_dm_connector *aconnector;
int ret = 0;
*enabled = false;
mutex_lock(&adev->dm.audio_lock);
drm_connector_list_iter_begin(dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
aconnector = to_amdgpu_dm_connector(connector);
if (aconnector->audio_inst != port)
continue;
*enabled = true;
ret = drm_eld_size(connector->eld);
memcpy(buf, connector->eld, min(max_bytes, ret));
break;
}
drm_connector_list_iter_end(&conn_iter);
mutex_unlock(&adev->dm.audio_lock);
DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
return ret;
}
static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
.get_eld = amdgpu_dm_audio_component_get_eld,
};
static int amdgpu_dm_audio_component_bind(struct device *kdev,
struct device *hda_kdev, void *data)
{
struct drm_device *dev = dev_get_drvdata(kdev);
struct amdgpu_device *adev = dev->dev_private;
struct drm_audio_component *acomp = data;
acomp->ops = &amdgpu_dm_audio_component_ops;
acomp->dev = kdev;
adev->dm.audio_component = acomp;
return 0;
}
static void amdgpu_dm_audio_component_unbind(struct device *kdev,
struct device *hda_kdev, void *data)
{
struct drm_device *dev = dev_get_drvdata(kdev);
struct amdgpu_device *adev = dev->dev_private;
struct drm_audio_component *acomp = data;
acomp->ops = NULL;
acomp->dev = NULL;
adev->dm.audio_component = NULL;
}
static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
.bind = amdgpu_dm_audio_component_bind,
.unbind = amdgpu_dm_audio_component_unbind,
};
static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
{
int i, ret;
if (!amdgpu_audio)
return 0;
adev->mode_info.audio.enabled = true;
adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
adev->mode_info.audio.pin[i].channels = -1;
adev->mode_info.audio.pin[i].rate = -1;
adev->mode_info.audio.pin[i].bits_per_sample = -1;
adev->mode_info.audio.pin[i].status_bits = 0;
adev->mode_info.audio.pin[i].category_code = 0;
adev->mode_info.audio.pin[i].connected = false;
adev->mode_info.audio.pin[i].id =
adev->dm.dc->res_pool->audios[i]->inst;
adev->mode_info.audio.pin[i].offset = 0;
}
ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
if (ret < 0)
return ret;
adev->dm.audio_registered = true;
return 0;
}
static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
{
if (!amdgpu_audio)
return;
if (!adev->mode_info.audio.enabled)
return;
if (adev->dm.audio_registered) {
component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
adev->dm.audio_registered = false;
}
/* TODO: Disable audio? */
adev->mode_info.audio.enabled = false;
}
void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
{
struct drm_audio_component *acomp = adev->dm.audio_component;
if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
pin, -1);
}
}
static int amdgpu_dm_init(struct amdgpu_device *adev) static int amdgpu_dm_init(struct amdgpu_device *adev)
{ {
struct dc_init_data init_data; struct dc_init_data init_data;
@ -518,6 +653,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
memset(&init_data, 0, sizeof(init_data)); memset(&init_data, 0, sizeof(init_data));
mutex_init(&adev->dm.dc_lock); mutex_init(&adev->dm.dc_lock);
mutex_init(&adev->dm.audio_lock);
if(amdgpu_dm_irq_init(adev)) { if(amdgpu_dm_irq_init(adev)) {
DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
@ -621,6 +757,8 @@ error:
static void amdgpu_dm_fini(struct amdgpu_device *adev) static void amdgpu_dm_fini(struct amdgpu_device *adev)
{ {
amdgpu_dm_audio_fini(adev);
amdgpu_dm_destroy_drm_device(&adev->dm); amdgpu_dm_destroy_drm_device(&adev->dm);
/* DC Destroy TODO: Replace destroy DAL */ /* DC Destroy TODO: Replace destroy DAL */
@ -641,6 +779,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
adev->dm.freesync_module = NULL; adev->dm.freesync_module = NULL;
} }
mutex_destroy(&adev->dm.audio_lock);
mutex_destroy(&adev->dm.dc_lock); mutex_destroy(&adev->dm.dc_lock);
return; return;
@ -1888,6 +2027,10 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
if (r) if (r)
return r; return r;
r = amdgpu_dm_audio_init(adev);
if (r)
return r;
return 0; return 0;
} }
@ -4834,6 +4977,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
aconnector->base.stereo_allowed = false; aconnector->base.stereo_allowed = false;
aconnector->base.dpms = DRM_MODE_DPMS_OFF; aconnector->base.dpms = DRM_MODE_DPMS_OFF;
aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
aconnector->audio_inst = -1;
mutex_init(&aconnector->hpd_lock); mutex_init(&aconnector->hpd_lock);
/* /*
@ -5728,6 +5872,81 @@ cleanup:
kfree(bundle); kfree(bundle);
} }
static void amdgpu_dm_commit_audio(struct drm_device *dev,
struct drm_atomic_state *state)
{
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_state *old_con_state, *new_con_state;
struct drm_crtc_state *new_crtc_state;
struct dm_crtc_state *new_dm_crtc_state;
const struct dc_stream_status *status;
int i, inst;
/* Notify device removals. */
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
if (old_con_state->crtc != new_con_state->crtc) {
/* CRTC changes require notification. */
goto notify;
}
if (!new_con_state->crtc)
continue;
new_crtc_state = drm_atomic_get_new_crtc_state(
state, new_con_state->crtc);
if (!new_crtc_state)
continue;
if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
continue;
notify:
aconnector = to_amdgpu_dm_connector(connector);
mutex_lock(&adev->dm.audio_lock);
inst = aconnector->audio_inst;
aconnector->audio_inst = -1;
mutex_unlock(&adev->dm.audio_lock);
amdgpu_dm_audio_eld_notify(adev, inst);
}
/* Notify audio device additions. */
for_each_new_connector_in_state(state, connector, new_con_state, i) {
if (!new_con_state->crtc)
continue;
new_crtc_state = drm_atomic_get_new_crtc_state(
state, new_con_state->crtc);
if (!new_crtc_state)
continue;
if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
continue;
new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
if (!new_dm_crtc_state->stream)
continue;
status = dc_stream_get_status(new_dm_crtc_state->stream);
if (!status)
continue;
aconnector = to_amdgpu_dm_connector(connector);
mutex_lock(&adev->dm.audio_lock);
inst = status->audio_inst;
aconnector->audio_inst = inst;
mutex_unlock(&adev->dm.audio_lock);
amdgpu_dm_audio_eld_notify(adev, inst);
}
}
/* /*
* Enable interrupts on CRTCs that are newly active, undergone * Enable interrupts on CRTCs that are newly active, undergone
* a modeset, or have active planes again. * a modeset, or have active planes again.
@ -6106,6 +6325,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
/* Enable interrupts for CRTCs going from 0 to n active planes. */ /* Enable interrupts for CRTCs going from 0 to n active planes. */
amdgpu_dm_enable_crtc_interrupts(dev, state, false); amdgpu_dm_enable_crtc_interrupts(dev, state, false);
/* Update audio instances for each connector. */
amdgpu_dm_commit_audio(dev, state);
/* /*
* send vblank event on all events not handled in flip and * send vblank event on all events not handled in flip and
* mark consumed event for drm_atomic_helper_commit_hw_done * mark consumed event for drm_atomic_helper_commit_hw_done

25
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
View File

@ -143,6 +143,28 @@ struct amdgpu_display_manager {
*/ */
struct mutex dc_lock; struct mutex dc_lock;
/**
* @audio_lock:
*
* Guards access to audio instance changes.
*/
struct mutex audio_lock;
/**
* @audio_component:
*
* Used to notify ELD changes to sound driver.
*/
struct drm_audio_component *audio_component;
/**
* @audio_registered:
*
* True if the audio component has been registered
* successfully, false otherwise.
*/
bool audio_registered;
/** /**
* @irq_handler_list_low_tab: * @irq_handler_list_low_tab:
* *
@ -254,6 +276,9 @@ struct amdgpu_dm_connector {
int max_vfreq ; int max_vfreq ;
int pixel_clock_mhz; int pixel_clock_mhz;
/* Audio instance - protected by audio_lock. */
int audio_inst;
struct mutex hpd_lock; struct mutex hpd_lock;
bool fake_enable; bool fake_enable;

9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
View File

@ -308,7 +308,8 @@ static void pp_to_dc_clock_levels_with_voltage(
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
for (i = 0; i < clk_level_info->num_levels; i++) { for (i = 0; i < clk_level_info->num_levels; i++) {
DRM_INFO("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz); DRM_INFO("DM_PPLIB:\t %d in kHz, %d in mV\n", pp_clks->data[i].clocks_in_khz,
pp_clks->data[i].voltage_in_mv);
clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv; clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
} }
@ -910,11 +911,11 @@ void dm_pp_get_funcs(
/* todo set_pme_wa_enable cause 4k@6ohz display not light up */ /* todo set_pme_wa_enable cause 4k@6ohz display not light up */
funcs->nv_funcs.set_pme_wa_enable = NULL; funcs->nv_funcs.set_pme_wa_enable = NULL;
/* todo debug waring message */ /* todo debug waring message */
funcs->nv_funcs.set_hard_min_uclk_by_freq = NULL; funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq;
/* todo compare data with window driver*/ /* todo compare data with window driver*/
funcs->nv_funcs.get_maximum_sustainable_clocks = NULL; funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks;
/*todo compare data with window driver */ /*todo compare data with window driver */
funcs->nv_funcs.get_uclk_dpm_states = NULL; funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
break; break;
#endif #endif
default: default:

45
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -175,32 +175,22 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
if (res_pool != NULL) { if (res_pool != NULL) {
struct dc_firmware_info fw_info = { { 0 } }; struct dc_firmware_info fw_info = { { 0 } };
if (dc->ctx->dc_bios->funcs->get_firmware_info( if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios,
dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) { &fw_info) == BP_RESULT_OK) {
res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency; res_pool->ref_clocks.xtalin_clock_inKhz =
fw_info.pll_info.crystal_frequency;
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { /* initialize with firmware data first, no all
// On FPGA these dividers are currently not configured by GDB * ASIC have DCCG SW component. FPGA or
res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz; * simulation need initialization of
res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz; * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
} else if (res_pool->dccg && res_pool->hubbub) { * with xtalin_clock_inKhz
// If DCCG reference frequency cannot be determined (usually means not set to xtalin) then this is a critical error */
// as this value must be known for DCHUB programming res_pool->ref_clocks.dccg_ref_clock_inKhz =
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, res_pool->ref_clocks.xtalin_clock_inKhz;
fw_info.pll_info.crystal_frequency, res_pool->ref_clocks.dchub_ref_clock_inKhz =
&res_pool->ref_clocks.dccg_ref_clock_inKhz); res_pool->ref_clocks.xtalin_clock_inKhz;
} else
// Similarly, if DCHUB reference frequency cannot be determined, then it is also a critical error ASSERT_CRITICAL(false);
(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
res_pool->ref_clocks.dccg_ref_clock_inKhz,
&res_pool->ref_clocks.dchub_ref_clock_inKhz);
} else {
// Not all ASICs have DCCG sw component
res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
}
} else
ASSERT_CRITICAL(false);
} }
return res_pool; return res_pool;
@ -2011,6 +2001,9 @@ enum dc_status resource_map_pool_resources(
if (context->streams[i] == stream) { if (context->streams[i] == stream) {
context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id; context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
context->stream_status[i].audio_inst =
pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
return DC_OK; return DC_OK;
} }

1
drivers/gpu/drm/amd/display/dc/dc_stream.h
View File

@ -42,6 +42,7 @@ struct dc_stream_status {
int primary_otg_inst; int primary_otg_inst;
int stream_enc_inst; int stream_enc_inst;
int plane_count; int plane_count;
int audio_inst;
struct timing_sync_info timing_sync_info; struct timing_sync_info timing_sync_info;
struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
}; };

8
drivers/gpu/drm/amd/display/dc/dcn20/Makefile
View File

@ -10,7 +10,13 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
DCN20 += dcn20_dsc.o DCN20 += dcn20_dsc.o
endif endif
CFLAGS_dcn20_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4 ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
cc_stack_align := -mpreferred-stack-boundary=4
else ifneq ($(call cc-option, -mstack-alignment=16),)
cc_stack_align := -mstack-alignment=16
endif
CFLAGS_dcn20_resource.o := -mhard-float -msse $(cc_stack_align)
AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20)) AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))

25
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@ -523,6 +523,7 @@ static void dcn20_init_hw(struct dc *dc)
struct dc_bios *dcb = dc->ctx->dc_bios; struct dc_bios *dcb = dc->ctx->dc_bios;
struct resource_pool *res_pool = dc->res_pool; struct resource_pool *res_pool = dc->res_pool;
struct dc_state *context = dc->current_state; struct dc_state *context = dc->current_state;
struct dc_firmware_info fw_info = { { 0 } };
if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
@ -546,6 +547,30 @@ static void dcn20_init_hw(struct dc *dc)
} else { } else {
if (!dcb->funcs->is_accelerated_mode(dcb)) { if (!dcb->funcs->is_accelerated_mode(dcb)) {
bios_golden_init(dc); bios_golden_init(dc);
if (dc->ctx->dc_bios->funcs->get_firmware_info(
dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (res_pool->dccg && res_pool->hubbub) {
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
fw_info.pll_info.crystal_frequency,
&res_pool->ref_clocks.dccg_ref_clock_inKhz);
(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
res_pool->ref_clocks.dccg_ref_clock_inKhz,
&res_pool->ref_clocks.dchub_ref_clock_inKhz);
} else {
// Not all ASICs have DCCG sw component
res_pool->ref_clocks.dccg_ref_clock_inKhz =
res_pool->ref_clocks.xtalin_clock_inKhz;
res_pool->ref_clocks.dchub_ref_clock_inKhz =
res_pool->ref_clocks.xtalin_clock_inKhz;
}
}
} else
ASSERT_CRITICAL(false);
disable_vga(dc->hwseq); disable_vga(dc->hwseq);
} }

12
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
View File

@ -2415,7 +2415,7 @@ struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
ASSERT(0); ASSERT(0);
if (!idle_pipe) if (!idle_pipe)
return false; return NULL;
idle_pipe->stream = head_pipe->stream; idle_pipe->stream = head_pipe->stream;
idle_pipe->stream_res.tg = head_pipe->stream_res.tg; idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
@ -2576,6 +2576,9 @@ static void cap_soc_clocks(
&& max_clocks.uClockInKhz != 0) && max_clocks.uClockInKhz != 0)
bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
// HACK: Force every uclk to max for now to "disable" uclk switching.
bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
&& max_clocks.fabricClockInKhz != 0) && max_clocks.fabricClockInKhz != 0)
bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
@ -2783,6 +2786,8 @@ static bool init_soc_bounding_box(struct dc *dc,
le32_to_cpu(bb->vmm_page_size_bytes); le32_to_cpu(bb->vmm_page_size_bytes);
dcn2_0_soc.dram_clock_change_latency_us = dcn2_0_soc.dram_clock_change_latency_us =
fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
// HACK!! Lower uclock latency switch time so we don't switch
dcn2_0_soc.dram_clock_change_latency_us = 10;
dcn2_0_soc.writeback_dram_clock_change_latency_us = dcn2_0_soc.writeback_dram_clock_change_latency_us =
fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
dcn2_0_soc.return_bus_width_bytes = dcn2_0_soc.return_bus_width_bytes =
@ -2824,6 +2829,7 @@ static bool init_soc_bounding_box(struct dc *dc,
struct pp_smu_nv_clock_table max_clocks = {0}; struct pp_smu_nv_clock_table max_clocks = {0};
unsigned int uclk_states[8] = {0}; unsigned int uclk_states[8] = {0};
unsigned int num_states = 0; unsigned int num_states = 0;
int i;
enum pp_smu_status status; enum pp_smu_status status;
bool clock_limits_available = false; bool clock_limits_available = false;
bool uclk_states_available = false; bool uclk_states_available = false;
@ -2845,6 +2851,10 @@ static bool init_soc_bounding_box(struct dc *dc,
clock_limits_available = (status == PP_SMU_RESULT_OK); clock_limits_available = (status == PP_SMU_RESULT_OK);
} }
// HACK: Use the max uclk_states value for all elements.
for (i = 0; i < num_states; i++)
uclk_states[i] = uclk_states[num_states - 1];
if (clock_limits_available && uclk_states_available && num_states) if (clock_limits_available && uclk_states_available && num_states)
update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states); update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states);
else if (clock_limits_available) else if (clock_limits_available)

16
drivers/gpu/drm/amd/display/dc/dsc/Makefile
View File

@ -1,10 +1,18 @@
# #
# Makefile for the 'dsc' sub-component of DAL. # Makefile for the 'dsc' sub-component of DAL.
CFLAGS_rc_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4 ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
CFLAGS_rc_calc_dpi.o := -mhard-float -msse -mpreferred-stack-boundary=4 cc_stack_align := -mpreferred-stack-boundary=4
CFLAGS_codec_main_amd.o := -mhard-float -msse -mpreferred-stack-boundary=4 else ifneq ($(call cc-option, -mstack-alignment=16),)
CFLAGS_dc_dsc.o := -mhard-float -msse -mpreferred-stack-boundary=4 cc_stack_align := -mstack-alignment=16
endif
dsc_ccflags := -mhard-float -msse $(cc_stack_align)
CFLAGS_rc_calc.o := $(dsc_ccflags)
CFLAGS_rc_calc_dpi.o := $(dsc_ccflags)
CFLAGS_codec_main_amd.o := $(dsc_ccflags)
CFLAGS_dc_dsc.o := $(dsc_ccflags)
DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o

2
drivers/gpu/drm/amd/include/amd_shared.h
View File

@ -26,7 +26,7 @@
#include <drm/amd_asic_type.h> #include <drm/amd_asic_type.h>
#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ #define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */
/* /*
* Chip flags * Chip flags

75
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
View File

@ -69,6 +69,9 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
if (min <= 0 && max <= 0) if (min <= 0 && max <= 0)
return -EINVAL; return -EINVAL;
if (!smu_clk_dpm_is_enabled(smu, clk_type))
return 0;
clk_id = smu_clk_get_index(smu, clk_type); clk_id = smu_clk_get_index(smu, clk_type);
if (clk_id < 0) if (clk_id < 0)
return clk_id; return clk_id;
@ -102,6 +105,9 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
if (min <= 0 && max <= 0) if (min <= 0 && max <= 0)
return -EINVAL; return -EINVAL;
if (!smu_clk_dpm_is_enabled(smu, clk_type))
return 0;
clk_id = smu_clk_get_index(smu, clk_type); clk_id = smu_clk_get_index(smu, clk_type);
if (clk_id < 0) if (clk_id < 0)
return clk_id; return clk_id;
@ -135,23 +141,8 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
if (!min && !max) if (!min && !max)
return -EINVAL; return -EINVAL;
switch (clk_type) { if (!smu_clk_dpm_is_enabled(smu, clk_type))
case SMU_UCLK: return 0;
if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
pr_warn("uclk dpm is not enabled\n");
return 0;
}
break;
case SMU_GFXCLK:
case SMU_SCLK:
if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
pr_warn("gfxclk dpm is not enabled\n");
return 0;
}
break;
default:
break;
}
mutex_lock(&smu->mutex); mutex_lock(&smu->mutex);
clk_id = smu_clk_get_index(smu, clk_type); clk_id = smu_clk_get_index(smu, clk_type);
@ -194,6 +185,9 @@ int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_typ
if (!value) if (!value)
return -EINVAL; return -EINVAL;
if (!smu_clk_dpm_is_enabled(smu, clk_type))
return 0;
clk_id = smu_clk_get_index(smu, clk_type); clk_id = smu_clk_get_index(smu, clk_type);
if (clk_id < 0) if (clk_id < 0)
return clk_id; return clk_id;
@ -222,6 +216,35 @@ int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value); return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
} }
bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
{
enum smu_feature_mask feature_id = 0;
switch (clk_type) {
case SMU_MCLK:
case SMU_UCLK:
feature_id = SMU_FEATURE_DPM_UCLK_BIT;
break;
case SMU_GFXCLK:
case SMU_SCLK:
feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
break;
case SMU_SOCCLK:
feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
break;
default:
return true;
}
if(!smu_feature_is_enabled(smu, feature_id)) {
pr_warn("smu %d clk dpm feature %d is not enabled\n", clk_type, feature_id);
return false;
}
return true;
}
int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
bool gate) bool gate)
{ {
@ -300,7 +323,7 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
return ret; return ret;
} }
int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
void *table_data, bool drv2smu) void *table_data, bool drv2smu)
{ {
struct smu_table_context *smu_table = &smu->smu_table; struct smu_table_context *smu_table = &smu->smu_table;
@ -327,7 +350,7 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index,
ret = smu_send_smc_msg_with_param(smu, drv2smu ? ret = smu_send_smc_msg_with_param(smu, drv2smu ?
SMU_MSG_TransferTableDram2Smu : SMU_MSG_TransferTableDram2Smu :
SMU_MSG_TransferTableSmu2Dram, SMU_MSG_TransferTableSmu2Dram,
table_id); table_id | ((argument & 0xFFFF) << 16));
if (ret) if (ret)
return ret; return ret;
@ -1372,10 +1395,10 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
break; break;
case AMD_DPM_FORCED_LEVEL_AUTO: case AMD_DPM_FORCED_LEVEL_AUTO:
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
ret = smu_unforce_dpm_levels(smu); ret = smu_unforce_dpm_levels(smu);
break; break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
@ -1385,8 +1408,9 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
&soc_mask); &soc_mask);
if (ret) if (ret)
return ret; return ret;
smu_force_clk_levels(smu, PP_SCLK, 1 << sclk_mask); smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
smu_force_clk_levels(smu, PP_MCLK, 1 << mclk_mask); smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
break; break;
case AMD_DPM_FORCED_LEVEL_MANUAL: case AMD_DPM_FORCED_LEVEL_MANUAL:
@ -1441,17 +1465,16 @@ int smu_handle_task(struct smu_context *smu,
enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu) enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
{ {
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
enum amd_dpm_forced_level level;
if (!smu_dpm_ctx->dpm_context) if (!smu_dpm_ctx->dpm_context)
return -EINVAL; return -EINVAL;
mutex_lock(&(smu->mutex)); mutex_lock(&(smu->mutex));
if (smu_dpm_ctx->dpm_level != smu_dpm_ctx->saved_dpm_level) { level = smu_dpm_ctx->dpm_level;
smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
}
mutex_unlock(&(smu->mutex)); mutex_unlock(&(smu->mutex));
return smu_dpm_ctx->dpm_level; return level;
} }
int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level) int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)

2
drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
View File

@ -1067,8 +1067,6 @@ static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable), PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),
"Failed to allocate hwmgr->pptable!", return -ENOMEM); "Failed to allocate hwmgr->pptable!", return -ENOMEM);
memset(hwmgr->pptable, 0x00, sizeof(struct phm_ppt_v1_information));
powerplay_table = get_powerplay_table(hwmgr); powerplay_table = get_powerplay_table(hwmgr);
PP_ASSERT_WITH_CODE((NULL != powerplay_table), PP_ASSERT_WITH_CODE((NULL != powerplay_table),

3
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
View File

@ -937,7 +937,7 @@ extern int smu_feature_is_supported(struct smu_context *smu,
extern int smu_feature_set_supported(struct smu_context *smu, extern int smu_feature_set_supported(struct smu_context *smu,
enum smu_feature_mask mask, bool enable); enum smu_feature_mask mask, bool enable);
int smu_update_table(struct smu_context *smu, uint32_t table_index, int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
void *table_data, bool drv2smu); void *table_data, bool drv2smu);
bool is_support_sw_smu(struct amdgpu_device *adev); bool is_support_sw_smu(struct amdgpu_device *adev);
@ -973,5 +973,6 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu); enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level); int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
int smu_set_display_count(struct smu_context *smu, uint32_t count); int smu_set_display_count(struct smu_context *smu, uint32_t count);
bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
#endif #endif

6
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
View File

@ -27,7 +27,7 @@
// *** IMPORTANT *** // *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if // SMU TEAM: Always increment the interface version if
// any structure is changed in this file // any structure is changed in this file
#define SMU11_DRIVER_IF_VERSION 0x12 #define SMU11_DRIVER_IF_VERSION 0x13
#define PPTABLE_V20_SMU_VERSION 3 #define PPTABLE_V20_SMU_VERSION 3
@ -615,6 +615,7 @@ typedef struct {
uint16_t UclkAverageLpfTau; uint16_t UclkAverageLpfTau;
uint16_t GfxActivityLpfTau; uint16_t GfxActivityLpfTau;
uint16_t UclkActivityLpfTau; uint16_t UclkActivityLpfTau;
uint16_t SocketPowerLpfTau;
uint32_t MmHubPadding[8]; uint32_t MmHubPadding[8];
@ -665,7 +666,8 @@ typedef struct {
uint32_t ThrottlerStatus ; uint32_t ThrottlerStatus ;
uint8_t LinkDpmLevel; uint8_t LinkDpmLevel;
uint8_t Padding[3]; uint16_t AverageSocketPower;
uint8_t Padding;
uint32_t MmHubPadding[7]; uint32_t MmHubPadding[7];

62
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
View File

@ -331,7 +331,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT) | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
| FEATURE_MASK(FEATURE_BACO_BIT) | FEATURE_MASK(FEATURE_BACO_BIT)
| FEATURE_MASK(FEATURE_ACDC_BIT); | FEATURE_MASK(FEATURE_ACDC_BIT)
| FEATURE_MASK(FEATURE_GFX_SS_BIT)
| FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
| FEATURE_MASK(FEATURE_FW_CTF_BIT);
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
@ -339,8 +342,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
if (adev->pm.pp_feature & PP_GFXOFF_MASK) { if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
| FEATURE_MASK(FEATURE_GFXOFF_BIT);
/* TODO: remove it once fw fix the bug */ /* TODO: remove it once fw fix the bug */
*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT); *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
} }
@ -465,9 +467,6 @@ static int navi10_append_powerplay_table(struct smu_context *smu)
smc_pptable->MvddRatio = smc_dpm_table->MvddRatio; smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
if (adev->pm.pp_feature & PP_GFXOFF_MASK) { if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
*(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
| FEATURE_MASK(FEATURE_GFXOFF_BIT);
/* TODO: remove it once SMU fw fix it */ /* TODO: remove it once SMU fw fix it */
smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN; smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
} }
@ -614,7 +613,7 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
memset(&metrics, 0, sizeof(metrics)); memset(&metrics, 0, sizeof(metrics));
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false); ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
if (ret) if (ret)
return ret; return ret;
@ -709,7 +708,7 @@ static int navi10_force_clk_levels(struct smu_context *smu,
static int navi10_populate_umd_state_clk(struct smu_context *smu) static int navi10_populate_umd_state_clk(struct smu_context *smu)
{ {
int ret = 0; int ret = 0;
uint32_t min_sclk_freq = 0; uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL); ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
if (ret) if (ret)
@ -717,6 +716,12 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
smu->pstate_sclk = min_sclk_freq * 100; smu->pstate_sclk = min_sclk_freq * 100;
ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
if (ret)
return ret;
smu->pstate_mclk = min_mclk_freq * 100;
return ret; return ret;
} }
@ -827,27 +832,20 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
return ret; return ret;
} }
static int navi10_unforce_dpm_levels(struct smu_context *smu) { static int navi10_unforce_dpm_levels(struct smu_context *smu)
{
int ret = 0, i = 0; int ret = 0, i = 0;
uint32_t min_freq, max_freq; uint32_t min_freq, max_freq;
enum smu_clk_type clk_type; enum smu_clk_type clk_type;
struct clk_feature_map { enum smu_clk_type clks[] = {
enum smu_clk_type clk_type; SMU_GFXCLK,
uint32_t feature; SMU_MCLK,
} clk_feature_map[] = { SMU_SOCCLK,
{SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
{SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT},
{SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
}; };
for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { for (i = 0; i < ARRAY_SIZE(clks); i++) {
if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature)) clk_type = clks[i];
continue;
clk_type = clk_feature_map[i].clk_type;
ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq); ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
if (ret) if (ret)
return ret; return ret;
@ -868,7 +866,7 @@ static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
if (!value) if (!value)
return -EINVAL; return -EINVAL;
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics,
false); false);
if (ret) if (ret)
return ret; return ret;
@ -890,7 +888,7 @@ static int navi10_get_current_activity_percent(struct smu_context *smu,
msleep(1); msleep(1);
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
(void *)&metrics, false); (void *)&metrics, false);
if (ret) if (ret)
return ret; return ret;
@ -931,7 +929,7 @@ static int navi10_get_fan_speed(struct smu_context *smu, uint16_t *value)
memset(&metrics, 0, sizeof(metrics)); memset(&metrics, 0, sizeof(metrics));
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
(void *)&metrics, false); (void *)&metrics, false);
if (ret) if (ret)
return ret; return ret;
@ -997,7 +995,7 @@ static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
workload_type = smu_workload_get_type(smu, i); workload_type = smu_workload_get_type(smu, i);
result = smu_update_table(smu, result = smu_update_table(smu,
SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16, SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
(void *)(&activity_monitor), false); (void *)(&activity_monitor), false);
if (result) { if (result) {
pr_err("[%s] Failed to get activity monitor!", __func__); pr_err("[%s] Failed to get activity monitor!", __func__);
@ -1070,7 +1068,7 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
return -EINVAL; return -EINVAL;
ret = smu_update_table(smu, ret = smu_update_table(smu,
SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
(void *)(&activity_monitor), false); (void *)(&activity_monitor), false);
if (ret) { if (ret) {
pr_err("[%s] Failed to get activity monitor!", __func__); pr_err("[%s] Failed to get activity monitor!", __func__);
@ -1114,7 +1112,7 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
} }
ret = smu_update_table(smu, ret = smu_update_table(smu,
SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
(void *)(&activity_monitor), true); (void *)(&activity_monitor), true);
if (ret) { if (ret) {
pr_err("[%s] Failed to set activity monitor!", __func__); pr_err("[%s] Failed to set activity monitor!", __func__);
@ -1157,14 +1155,14 @@ static int navi10_get_profiling_clk_mask(struct smu_context *smu,
ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count); ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
if (ret) if (ret)
return ret; return ret;
*sclk_mask = level_count - 1; *mclk_mask = level_count - 1;
} }
if(soc_mask) { if(soc_mask) {
ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count); ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
if (ret) if (ret)
return ret; return ret;
*sclk_mask = level_count - 1; *soc_mask = level_count - 1;
} }
} }
@ -1280,7 +1278,7 @@ static int navi10_thermal_get_temperature(struct smu_context *smu,
if (!value) if (!value)
return -EINVAL; return -EINVAL;
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false); ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
if (ret) if (ret)
return ret; return ret;

16
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
View File

@ -261,14 +261,20 @@ static int smu_v11_0_check_fw_version(struct smu_context *smu)
smu_minor = (smu_version >> 8) & 0xff; smu_minor = (smu_version >> 8) & 0xff;
smu_debug = (smu_version >> 0) & 0xff; smu_debug = (smu_version >> 0) & 0xff;
/*
* 1. if_version mismatch is not critical as our fw is designed
* to be backward compatible.
* 2. New fw usually brings some optimizations. But that's visible
* only on the paired driver.
* Considering above, we just leave user a warning message instead
* of halt driver loading.
*/
if (if_version != smu->smc_if_version) { if (if_version != smu->smc_if_version) {
pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, " pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
"smu fw version = 0x%08x (%d.%d.%d)\n", "smu fw version = 0x%08x (%d.%d.%d)\n",
smu->smc_if_version, if_version, smu->smc_if_version, if_version,
smu_version, smu_major, smu_minor, smu_debug); smu_version, smu_major, smu_minor, smu_debug);
pr_err("SMU driver if version not matched\n"); pr_warn("SMU driver if version not matched\n");
ret = -EINVAL;
} }
return ret; return ret;
@ -703,7 +709,7 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
struct smu_table_context *table_context = &smu->smu_table; struct smu_table_context *table_context = &smu->smu_table;
int ret = 0; int ret = 0;
ret = smu_update_table(smu, SMU_TABLE_PPTABLE, ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
table_context->driver_pptable, true); table_context->driver_pptable, true);
return ret; return ret;
@ -722,7 +728,7 @@ static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
if (!table->cpu_addr) if (!table->cpu_addr)
return -EINVAL; return -EINVAL;
ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, table->cpu_addr, ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
true); true);
return ret; return ret;

2
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
View File

@ -2705,8 +2705,6 @@ static int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2)); cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
if (0 == result) if (0 == result)

2
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
View File

@ -2634,8 +2634,6 @@ static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2)); cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
if (0 == result) if (0 == result)

2
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
View File

@ -3117,8 +3117,6 @@ static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP,
cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
if (!result) if (!result)

41
drivers/gpu/drm/amd/powerplay/vega20_ppt.c
View File

@ -319,7 +319,7 @@ static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
AMDGPU_GEM_DOMAIN_VRAM); AMDGPU_GEM_DOMAIN_VRAM);
smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
if (smu_table->metrics_table) if (!smu_table->metrics_table)
return -ENOMEM; return -ENOMEM;
smu_table->metrics_time = 0; smu_table->metrics_time = 0;
@ -441,7 +441,6 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
{ {
ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL; ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
struct smu_table_context *table_context = &smu->smu_table; struct smu_table_context *table_context = &smu->smu_table;
int ret;
if (!table_context->power_play_table) if (!table_context->power_play_table)
return -EINVAL; return -EINVAL;
@ -455,9 +454,7 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
table_context->thermal_controller_type = powerplay_table->ucThermalControllerType; table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]); table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
ret = vega20_setup_od8_information(smu); return 0;
return ret;
} }
static int vega20_append_powerplay_table(struct smu_context *smu) static int vega20_append_powerplay_table(struct smu_context *smu)
@ -992,7 +989,7 @@ static int vega20_print_clk_levels(struct smu_context *smu,
break; break;
case SMU_SOCCLK: case SMU_SOCCLK:
ret = smu_get_current_clk_freq(smu, PPCLK_SOCCLK, &now); ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
if (ret) { if (ret) {
pr_err("Attempt to get current socclk Failed!"); pr_err("Attempt to get current socclk Failed!");
return ret; return ret;
@ -1013,7 +1010,7 @@ static int vega20_print_clk_levels(struct smu_context *smu,
break; break;
case SMU_FCLK: case SMU_FCLK:
ret = smu_get_current_clk_freq(smu, PPCLK_FCLK, &now); ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
if (ret) { if (ret) {
pr_err("Attempt to get current fclk Failed!"); pr_err("Attempt to get current fclk Failed!");
return ret; return ret;
@ -1028,7 +1025,7 @@ static int vega20_print_clk_levels(struct smu_context *smu,
break; break;
case SMU_DCEFCLK: case SMU_DCEFCLK:
ret = smu_get_current_clk_freq(smu, PPCLK_DCEFCLK, &now); ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
if (ret) { if (ret) {
pr_err("Attempt to get current dcefclk Failed!"); pr_err("Attempt to get current dcefclk Failed!");
return ret; return ret;
@ -1502,11 +1499,17 @@ static int vega20_set_default_od8_setttings(struct smu_context *smu)
od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL); od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
if (od8_settings) if (!od8_settings)
return -ENOMEM; return -ENOMEM;
smu->od_settings = (void *)od8_settings; smu->od_settings = (void *)od8_settings;
ret = vega20_setup_od8_information(smu);
if (ret) {
pr_err("Retrieve board OD limits failed!\n");
return ret;
}
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] && if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 && od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
@ -1677,7 +1680,7 @@ static int vega20_get_metrics_table(struct smu_context *smu,
int ret = 0; int ret = 0;
if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) { if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
(void *)smu_table->metrics_table, false); (void *)smu_table->metrics_table, false);
if (ret) { if (ret) {
pr_info("Failed to export SMU metrics table!\n"); pr_info("Failed to export SMU metrics table!\n");
@ -1706,7 +1709,7 @@ static int vega20_set_default_od_settings(struct smu_context *smu,
if (!table_context->overdrive_table) if (!table_context->overdrive_table)
return -ENOMEM; return -ENOMEM;
ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
table_context->overdrive_table, false); table_context->overdrive_table, false);
if (ret) { if (ret) {
pr_err("Failed to export over drive table!\n"); pr_err("Failed to export over drive table!\n");
@ -1718,7 +1721,7 @@ static int vega20_set_default_od_settings(struct smu_context *smu,
return ret; return ret;
} }
ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
table_context->overdrive_table, true); table_context->overdrive_table, true);
if (ret) { if (ret) {
pr_err("Failed to import over drive table!\n"); pr_err("Failed to import over drive table!\n");
@ -1802,7 +1805,7 @@ static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
workload_type = smu_workload_get_type(smu, i); workload_type = smu_workload_get_type(smu, i);
result = smu_update_table(smu, result = smu_update_table(smu,
SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16, SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
(void *)(&activity_monitor), false); (void *)(&activity_monitor), false);
if (result) { if (result) {
pr_err("[%s] Failed to get activity monitor!", __func__); pr_err("[%s] Failed to get activity monitor!", __func__);
@ -1888,7 +1891,7 @@ static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, u
if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
ret = smu_update_table(smu, ret = smu_update_table(smu,
SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
(void *)(&activity_monitor), false); (void *)(&activity_monitor), false);
if (ret) { if (ret) {
pr_err("[%s] Failed to get activity monitor!", __func__); pr_err("[%s] Failed to get activity monitor!", __func__);
@ -1943,7 +1946,7 @@ static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, u
} }
ret = smu_update_table(smu, ret = smu_update_table(smu,
SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
(void *)(&activity_monitor), true); (void *)(&activity_monitor), true);
if (ret) { if (ret) {
pr_err("[%s] Failed to set activity monitor!", __func__); pr_err("[%s] Failed to set activity monitor!", __func__);
@ -2492,7 +2495,7 @@ static int vega20_update_od8_settings(struct smu_context *smu,
struct smu_table_context *table_context = &smu->smu_table; struct smu_table_context *table_context = &smu->smu_table;
int ret; int ret;
ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
table_context->overdrive_table, false); table_context->overdrive_table, false);
if (ret) { if (ret) {
pr_err("Failed to export over drive table!\n"); pr_err("Failed to export over drive table!\n");
@ -2503,7 +2506,7 @@ static int vega20_update_od8_settings(struct smu_context *smu,
if (ret) if (ret)
return ret; return ret;
ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
table_context->overdrive_table, true); table_context->overdrive_table, true);
if (ret) { if (ret) {
pr_err("Failed to import over drive table!\n"); pr_err("Failed to import over drive table!\n");
@ -2767,7 +2770,7 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
break; break;
case PP_OD_RESTORE_DEFAULT_TABLE: case PP_OD_RESTORE_DEFAULT_TABLE:
ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, table_context->overdrive_table, false); ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
if (ret) { if (ret) {
pr_err("Failed to export over drive table!\n"); pr_err("Failed to export over drive table!\n");
return ret; return ret;
@ -2776,7 +2779,7 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
break; break;
case PP_OD_COMMIT_DPM_TABLE: case PP_OD_COMMIT_DPM_TABLE:
ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, table_context->overdrive_table, true); ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
if (ret) { if (ret) {
pr_err("Failed to import over drive table!\n"); pr_err("Failed to import over drive table!\n");
return ret; return ret;

63
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
View File

@ -454,24 +454,6 @@ static void komeda_crtc_vblank_disable(struct drm_crtc *crtc)
mdev->funcs->on_off_vblank(mdev, kcrtc->master->id, false); mdev->funcs->on_off_vblank(mdev, kcrtc->master->id, false);
} }
static int
komeda_crtc_atomic_get_property(struct drm_crtc *crtc,
const struct drm_crtc_state *state,
struct drm_property *property, uint64_t *val)
{
struct komeda_crtc *kcrtc = to_kcrtc(crtc);
struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(state);
if (property == kcrtc->clock_ratio_property) {
*val = kcrtc_st->clock_ratio;
} else {
DRM_DEBUG_DRIVER("Unknown property %s\n", property->name);
return -EINVAL;
}
return 0;
}
static const struct drm_crtc_funcs komeda_crtc_funcs = { static const struct drm_crtc_funcs komeda_crtc_funcs = {
.gamma_set = drm_atomic_helper_legacy_gamma_set, .gamma_set = drm_atomic_helper_legacy_gamma_set,
.destroy = drm_crtc_cleanup, .destroy = drm_crtc_cleanup,
@ -482,7 +464,6 @@ static const struct drm_crtc_funcs komeda_crtc_funcs = {
.atomic_destroy_state = komeda_crtc_atomic_destroy_state, .atomic_destroy_state = komeda_crtc_atomic_destroy_state,
.enable_vblank = komeda_crtc_vblank_enable, .enable_vblank = komeda_crtc_vblank_enable,
.disable_vblank = komeda_crtc_vblank_disable, .disable_vblank = komeda_crtc_vblank_disable,
.atomic_get_property = komeda_crtc_atomic_get_property,
}; };
int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms, int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms,
@ -518,42 +499,6 @@ int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms,
return 0; return 0;
} }
static int komeda_crtc_create_clock_ratio_property(struct komeda_crtc *kcrtc)
{
struct drm_crtc *crtc = &kcrtc->base;
struct drm_property *prop;
prop = drm_property_create_range(crtc->dev, DRM_MODE_PROP_ATOMIC,
"CLOCK_RATIO", 0, U64_MAX);
if (!prop)
return -ENOMEM;
drm_object_attach_property(&crtc->base, prop, 0);
kcrtc->clock_ratio_property = prop;
return 0;
}
static int komeda_crtc_create_slave_planes_property(struct komeda_crtc *kcrtc)
{
struct drm_crtc *crtc = &kcrtc->base;
struct drm_property *prop;
if (kcrtc->slave_planes == 0)
return 0;
prop = drm_property_create_range(crtc->dev, DRM_MODE_PROP_IMMUTABLE,
"slave_planes", 0, U32_MAX);
if (!prop)
return -ENOMEM;
drm_object_attach_property(&crtc->base, prop, kcrtc->slave_planes);
kcrtc->slave_planes_property = prop;
return 0;
}
static struct drm_plane * static struct drm_plane *
get_crtc_primary(struct komeda_kms_dev *kms, struct komeda_crtc *crtc) get_crtc_primary(struct komeda_kms_dev *kms, struct komeda_crtc *crtc)
{ {
@ -590,14 +535,6 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms,
crtc->port = kcrtc->master->of_output_port; crtc->port = kcrtc->master->of_output_port;
err = komeda_crtc_create_clock_ratio_property(kcrtc);
if (err)
return err;
err = komeda_crtc_create_slave_planes_property(kcrtc);
if (err)
return err;
return err; return err;
} }

18
drivers/gpu/drm/arm/display/komeda/komeda_kms.h
View File

@ -33,11 +33,6 @@ struct komeda_plane {
* Layers with same capabilities. * Layers with same capabilities.
*/ */
struct komeda_layer *layer; struct komeda_layer *layer;
/** @prop_img_enhancement: for on/off image enhancement */
struct drm_property *prop_img_enhancement;
/** @prop_layer_split: for on/off layer_split */
struct drm_property *prop_layer_split;
}; };
/** /**
@ -52,11 +47,8 @@ struct komeda_plane_state {
/** @zlist_node: zorder list node */ /** @zlist_node: zorder list node */
struct list_head zlist_node; struct list_head zlist_node;
/* @img_enhancement: on/off image enhancement /** @layer_split: on/off layer_split */
* @layer_split: on/off layer_split u8 layer_split : 1;
*/
u8 img_enhancement : 1,
layer_split : 1;
}; };
/** /**
@ -94,12 +86,6 @@ struct komeda_crtc {
/** @disable_done: this flip_done is for tracing the disable */ /** @disable_done: this flip_done is for tracing the disable */
struct completion *disable_done; struct completion *disable_done;
/** @clock_ratio_property: property for ratio of (aclk << 32)/pxlclk */
struct drm_property *clock_ratio_property;
/** @slave_planes_property: property for slaves of the planes */
struct drm_property *slave_planes_property;
}; };
/** /**

3
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
View File

@ -537,7 +537,8 @@ void komeda_pipeline_disable(struct komeda_pipeline *pipe,
void komeda_pipeline_update(struct komeda_pipeline *pipe, void komeda_pipeline_update(struct komeda_pipeline *pipe,
struct drm_atomic_state *old_state); struct drm_atomic_state *old_state);
void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow, void komeda_complete_data_flow_cfg(struct komeda_layer *layer,
struct komeda_data_flow_cfg *dflow,
struct drm_framebuffer *fb); struct drm_framebuffer *fb);
#endif /* _KOMEDA_PIPELINE_H_*/ #endif /* _KOMEDA_PIPELINE_H_*/

15
drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
View File

@ -784,9 +784,11 @@ komeda_timing_ctrlr_validate(struct komeda_timing_ctrlr *ctrlr,
return 0; return 0;
} }
void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow, void komeda_complete_data_flow_cfg(struct komeda_layer *layer,
struct komeda_data_flow_cfg *dflow,
struct drm_framebuffer *fb) struct drm_framebuffer *fb)
{ {
struct komeda_scaler *scaler = layer->base.pipeline->scalers[0];
u32 w = dflow->in_w; u32 w = dflow->in_w;
u32 h = dflow->in_h; u32 h = dflow->in_h;
@ -803,6 +805,17 @@ void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow,
dflow->en_scaling = (w != dflow->out_w) || (h != dflow->out_h); dflow->en_scaling = (w != dflow->out_w) || (h != dflow->out_h);
dflow->is_yuv = fb->format->is_yuv; dflow->is_yuv = fb->format->is_yuv;
/* try to enable image enhancer if data flow is a 2x+ upscaling */
dflow->en_img_enhancement = dflow->out_w >= 2 * w ||
dflow->out_h >= 2 * h;
/* try to enable split if scaling exceed the scaler's acceptable
* input/output range.
*/
if (dflow->en_scaling && scaler)
dflow->en_split = !in_range(&scaler->hsize, dflow->in_w) ||
!in_range(&scaler->hsize, dflow->out_w);
} }
static bool merger_is_available(struct komeda_pipeline *pipe, static bool merger_is_available(struct komeda_pipeline *pipe,

84
drivers/gpu/drm/arm/display/komeda/komeda_plane.c
View File

@ -18,7 +18,6 @@ komeda_plane_init_data_flow(struct drm_plane_state *st,
struct komeda_data_flow_cfg *dflow) struct komeda_data_flow_cfg *dflow)
{ {
struct komeda_plane *kplane = to_kplane(st->plane); struct komeda_plane *kplane = to_kplane(st->plane);
struct komeda_plane_state *kplane_st = to_kplane_st(st);
struct drm_framebuffer *fb = st->fb; struct drm_framebuffer *fb = st->fb;
const struct komeda_format_caps *caps = to_kfb(fb)->format_caps; const struct komeda_format_caps *caps = to_kfb(fb)->format_caps;
struct komeda_pipeline *pipe = kplane->layer->base.pipeline; struct komeda_pipeline *pipe = kplane->layer->base.pipeline;
@ -57,10 +56,7 @@ komeda_plane_init_data_flow(struct drm_plane_state *st,
return -EINVAL; return -EINVAL;
} }
dflow->en_img_enhancement = !!kplane_st->img_enhancement; komeda_complete_data_flow_cfg(kplane->layer, dflow, fb);
dflow->en_split = !!kplane_st->layer_split;
komeda_complete_data_flow_cfg(dflow, fb);
return 0; return 0;
} }
@ -175,8 +171,6 @@ komeda_plane_atomic_duplicate_state(struct drm_plane *plane)
old = to_kplane_st(plane->state); old = to_kplane_st(plane->state);
new->img_enhancement = old->img_enhancement;
return &new->base; return &new->base;
} }
@ -188,44 +182,6 @@ komeda_plane_atomic_destroy_state(struct drm_plane *plane,
kfree(to_kplane_st(state)); kfree(to_kplane_st(state));
} }
static int
komeda_plane_atomic_get_property(struct drm_plane *plane,
const struct drm_plane_state *state,
struct drm_property *property,
uint64_t *val)
{
struct komeda_plane *kplane = to_kplane(plane);
struct komeda_plane_state *st = to_kplane_st(state);
if (property == kplane->prop_img_enhancement)
*val = st->img_enhancement;
else if (property == kplane->prop_layer_split)
*val = st->layer_split;
else
return -EINVAL;
return 0;
}
static int
komeda_plane_atomic_set_property(struct drm_plane *plane,
struct drm_plane_state *state,
struct drm_property *property,
uint64_t val)
{
struct komeda_plane *kplane = to_kplane(plane);
struct komeda_plane_state *st = to_kplane_st(state);
if (property == kplane->prop_img_enhancement)
st->img_enhancement = !!val;
else if (property == kplane->prop_layer_split)
st->layer_split = !!val;
else
return -EINVAL;
return 0;
}
static bool static bool
komeda_plane_format_mod_supported(struct drm_plane *plane, komeda_plane_format_mod_supported(struct drm_plane *plane,
u32 format, u64 modifier) u32 format, u64 modifier)
@ -245,43 +201,9 @@ static const struct drm_plane_funcs komeda_plane_funcs = {
.reset = komeda_plane_reset, .reset = komeda_plane_reset,
.atomic_duplicate_state = komeda_plane_atomic_duplicate_state, .atomic_duplicate_state = komeda_plane_atomic_duplicate_state,
.atomic_destroy_state = komeda_plane_atomic_destroy_state, .atomic_destroy_state = komeda_plane_atomic_destroy_state,
.atomic_get_property = komeda_plane_atomic_get_property,
.atomic_set_property = komeda_plane_atomic_set_property,
.format_mod_supported = komeda_plane_format_mod_supported, .format_mod_supported = komeda_plane_format_mod_supported,
}; };
static int
komeda_plane_create_layer_properties(struct komeda_plane *kplane,
struct komeda_layer *layer)
{
struct drm_device *drm = kplane->base.dev;
struct drm_plane *plane = &kplane->base;
struct drm_property *prop = NULL;
/* property: layer image_enhancement */
if (layer->base.supported_outputs & KOMEDA_PIPELINE_SCALERS) {
prop = drm_property_create_bool(drm, DRM_MODE_PROP_ATOMIC,
"img_enhancement");
if (!prop)
return -ENOMEM;
drm_object_attach_property(&plane->base, prop, 0);
kplane->prop_img_enhancement = prop;
}
/* property: layer split */
if (layer->right) {
prop = drm_property_create_bool(drm, DRM_MODE_PROP_ATOMIC,
"layer_split");
if (!prop)
return -ENOMEM;
kplane->prop_layer_split = prop;
drm_object_attach_property(&plane->base, prop, 0);
}
return 0;
}
/* for komeda, which is pipeline can be share between crtcs */ /* for komeda, which is pipeline can be share between crtcs */
static u32 get_possible_crtcs(struct komeda_kms_dev *kms, static u32 get_possible_crtcs(struct komeda_kms_dev *kms,
struct komeda_pipeline *pipe) struct komeda_pipeline *pipe)
@ -375,10 +297,6 @@ static int komeda_plane_add(struct komeda_kms_dev *kms,
if (err) if (err)
goto cleanup; goto cleanup;
err = komeda_plane_create_layer_properties(kplane, layer);
if (err)
goto cleanup;
err = drm_plane_create_color_properties(plane, err = drm_plane_create_color_properties(plane,
BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT601) |
BIT(DRM_COLOR_YCBCR_BT709) | BIT(DRM_COLOR_YCBCR_BT709) |

10
drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
View File

@ -13,7 +13,6 @@ komeda_wb_init_data_flow(struct komeda_layer *wb_layer,
struct komeda_crtc_state *kcrtc_st, struct komeda_crtc_state *kcrtc_st,
struct komeda_data_flow_cfg *dflow) struct komeda_data_flow_cfg *dflow)
{ {
struct komeda_scaler *scaler = wb_layer->base.pipeline->scalers[0];
struct drm_framebuffer *fb = conn_st->writeback_job->fb; struct drm_framebuffer *fb = conn_st->writeback_job->fb;
memset(dflow, 0, sizeof(*dflow)); memset(dflow, 0, sizeof(*dflow));
@ -28,14 +27,7 @@ komeda_wb_init_data_flow(struct komeda_layer *wb_layer,
dflow->pixel_blend_mode = DRM_MODE_BLEND_PIXEL_NONE; dflow->pixel_blend_mode = DRM_MODE_BLEND_PIXEL_NONE;
dflow->rot = DRM_MODE_ROTATE_0; dflow->rot = DRM_MODE_ROTATE_0;
komeda_complete_data_flow_cfg(dflow, fb); komeda_complete_data_flow_cfg(wb_layer, dflow, fb);
/* if scaling exceed the acceptable scaler input/output range, try to
* enable split.
*/
if (dflow->en_scaling && scaler)
dflow->en_split = !in_range(&scaler->hsize, dflow->in_w) ||
!in_range(&scaler->hsize, dflow->out_w);
return 0; return 0;
} }

2
drivers/gpu/drm/bochs/bochs.h
View File

@ -86,7 +86,7 @@ void bochs_hw_setmode(struct bochs_device *bochs,
void bochs_hw_setformat(struct bochs_device *bochs, void bochs_hw_setformat(struct bochs_device *bochs,
const struct drm_format_info *format); const struct drm_format_info *format);
void bochs_hw_setbase(struct bochs_device *bochs, void bochs_hw_setbase(struct bochs_device *bochs,
int x, int y, u64 addr); int x, int y, int stride, u64 addr);
int bochs_hw_load_edid(struct bochs_device *bochs); int bochs_hw_load_edid(struct bochs_device *bochs);
/* bochs_mm.c */ /* bochs_mm.c */

14
drivers/gpu/drm/bochs/bochs_hw.c
View File

@ -255,16 +255,22 @@ void bochs_hw_setformat(struct bochs_device *bochs,
} }
void bochs_hw_setbase(struct bochs_device *bochs, void bochs_hw_setbase(struct bochs_device *bochs,
int x, int y, u64 addr) int x, int y, int stride, u64 addr)
{ {
unsigned long offset = (unsigned long)addr + unsigned long offset;
unsigned int vx, vy, vwidth;
bochs->stride = stride;
offset = (unsigned long)addr +
y * bochs->stride + y * bochs->stride +
x * (bochs->bpp / 8); x * (bochs->bpp / 8);
int vy = offset / bochs->stride; vy = offset / bochs->stride;
int vx = (offset % bochs->stride) * 8 / bochs->bpp; vx = (offset % bochs->stride) * 8 / bochs->bpp;
vwidth = stride * 8 / bochs->bpp;
DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n", DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n",
x, y, addr, offset, vx, vy); x, y, addr, offset, vx, vy);
bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth);
bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx); bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx);
bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy); bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy);
} }

3
drivers/gpu/drm/bochs/bochs_kms.c
View File

@ -36,7 +36,8 @@ static void bochs_plane_update(struct bochs_device *bochs,
bochs_hw_setbase(bochs, bochs_hw_setbase(bochs,
state->crtc_x, state->crtc_x,
state->crtc_y, state->crtc_y,
gbo->bo.offset); state->fb->pitches[0],
state->fb->offsets[0] + gbo->bo.offset);
bochs_hw_setformat(bochs, state->fb->format); bochs_hw_setformat(bochs, state->fb->format);
} }

3
drivers/gpu/drm/drm_client_modeset.c
View File

@ -180,7 +180,8 @@ again:
create_mode: create_mode:
mode = drm_mode_create_from_cmdline_mode(connector->dev, cmdline_mode); mode = drm_mode_create_from_cmdline_mode(connector->dev, cmdline_mode);
list_add(&mode->head, &connector->modes); if (mode)
list_add(&mode->head, &connector->modes);
return mode; return mode;
} }

2
drivers/gpu/drm/drm_connector.c
View File

@ -141,7 +141,7 @@ static void drm_connector_get_cmdline_mode(struct drm_connector *connector)
DRM_DEBUG_KMS("cmdline mode for connector %s %s %dx%d@%dHz%s%s%s\n", DRM_DEBUG_KMS("cmdline mode for connector %s %s %dx%d@%dHz%s%s%s\n",
connector->name, connector->name,
mode->name ? mode->name : "", mode->name,
mode->xres, mode->yres, mode->xres, mode->yres,
mode->refresh_specified ? mode->refresh : 60, mode->refresh_specified ? mode->refresh : 60,
mode->rb ? " reduced blanking" : "", mode->rb ? " reduced blanking" : "",

14
drivers/gpu/drm/drm_modes.c
View File

@ -158,6 +158,9 @@ struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
int interlace; int interlace;
u64 tmp; u64 tmp;
if (!hdisplay || !vdisplay)
return NULL;
/* allocate the drm_display_mode structure. If failure, we will /* allocate the drm_display_mode structure. If failure, we will
* return directly * return directly
*/ */
@ -392,6 +395,9 @@ drm_gtf_mode_complex(struct drm_device *dev, int hdisplay, int vdisplay,
int hsync, hfront_porch, vodd_front_porch_lines; int hsync, hfront_porch, vodd_front_porch_lines;
unsigned int tmp1, tmp2; unsigned int tmp1, tmp2;
if (!hdisplay || !vdisplay)
return NULL;
drm_mode = drm_mode_create(dev); drm_mode = drm_mode_create(dev);
if (!drm_mode) if (!drm_mode)
return NULL; return NULL;
@ -1448,7 +1454,7 @@ static int drm_mode_parse_cmdline_refresh(const char *str, char **end_ptr,
} }
static int drm_mode_parse_cmdline_extra(const char *str, int length, static int drm_mode_parse_cmdline_extra(const char *str, int length,
struct drm_connector *connector, const struct drm_connector *connector,
struct drm_cmdline_mode *mode) struct drm_cmdline_mode *mode)
{ {
int i; int i;
@ -1493,7 +1499,7 @@ static int drm_mode_parse_cmdline_extra(const char *str, int length,
static int drm_mode_parse_cmdline_res_mode(const char *str, unsigned int length, static int drm_mode_parse_cmdline_res_mode(const char *str, unsigned int length,
bool extras, bool extras,
struct drm_connector *connector, const struct drm_connector *connector,
struct drm_cmdline_mode *mode) struct drm_cmdline_mode *mode)
{ {
const char *str_start = str; const char *str_start = str;
@ -1555,7 +1561,7 @@ static int drm_mode_parse_cmdline_res_mode(const char *str, unsigned int length,
} }
static int drm_mode_parse_cmdline_options(char *str, size_t len, static int drm_mode_parse_cmdline_options(char *str, size_t len,
struct drm_connector *connector, const struct drm_connector *connector,
struct drm_cmdline_mode *mode) struct drm_cmdline_mode *mode)
{ {
unsigned int rotation = 0; unsigned int rotation = 0;
@ -1689,7 +1695,7 @@ static int drm_mode_parse_cmdline_options(char *str, size_t len,
* True if a valid modeline has been parsed, false otherwise. * True if a valid modeline has been parsed, false otherwise.
*/ */
bool drm_mode_parse_command_line_for_connector(const char *mode_option, bool drm_mode_parse_command_line_for_connector(const char *mode_option,
struct drm_connector *connector, const struct drm_connector *connector,
struct drm_cmdline_mode *mode) struct drm_cmdline_mode *mode)
{ {
const char *name; const char *name;

12
drivers/gpu/drm/drm_panel_orientation_quirks.c
View File

@ -90,6 +90,12 @@ static const struct drm_dmi_panel_orientation_data itworks_tw891 = {
.orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
}; };
static const struct drm_dmi_panel_orientation_data lcd720x1280_rightside_up = {
.width = 720,
.height = 1280,
.orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
};
static const struct drm_dmi_panel_orientation_data lcd800x1280_rightside_up = { static const struct drm_dmi_panel_orientation_data lcd800x1280_rightside_up = {
.width = 800, .width = 800,
.height = 1280, .height = 1280,
@ -123,6 +129,12 @@ static const struct dmi_system_id orientation_data[] = {
DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"), DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"),
}, },
.driver_data = (void *)&gpd_micropc, .driver_data = (void *)&gpd_micropc,
}, { /* GPD MicroPC (later BIOS versions with proper DMI strings) */
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "GPD"),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "MicroPC"),
},
.driver_data = (void *)&lcd720x1280_rightside_up,
}, { /* }, { /*
* GPD Pocket, note that the the DMI data is less generic then * GPD Pocket, note that the the DMI data is less generic then
* it seems, devices with a board-vendor of "AMI Corporation" * it seems, devices with a board-vendor of "AMI Corporation"

2
drivers/gpu/drm/nouveau/Kbuild
View File

@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: MIT
ccflags-y += -I $(srctree)/$(src)/include ccflags-y += -I $(srctree)/$(src)/include
ccflags-y += -I $(srctree)/$(src)/include/nvkm ccflags-y += -I $(srctree)/$(src)/include/nvkm
ccflags-y += -I $(srctree)/$(src)/nvkm ccflags-y += -I $(srctree)/$(src)/nvkm

2
drivers/gpu/drm/nouveau/dispnv04/Kbuild
View File

@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: MIT
nouveau-y += dispnv04/arb.o nouveau-y += dispnv04/arb.o
nouveau-y += dispnv04/crtc.o nouveau-y += dispnv04/crtc.o
nouveau-y += dispnv04/cursor.o nouveau-y += dispnv04/cursor.o

2
drivers/gpu/drm/nouveau/dispnv04/cursor.c
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: MIT
#include <drm/drmP.h> #include <drm/drmP.h>
#include <drm/drm_mode.h> #include <drm/drm_mode.h>
#include "nouveau_drv.h" #include "nouveau_drv.h"

2
drivers/gpu/drm/nouveau/dispnv04/disp.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NV04_DISPLAY_H__ #ifndef __NV04_DISPLAY_H__
#define __NV04_DISPLAY_H__ #define __NV04_DISPLAY_H__
#include <subdev/bios.h> #include <subdev/bios.h>

2
drivers/gpu/drm/nouveau/dispnv50/Kbuild
View File

@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: MIT
nouveau-y += dispnv50/disp.o nouveau-y += dispnv50/disp.o
nouveau-y += dispnv50/lut.o nouveau-y += dispnv50/lut.o

9
drivers/gpu/drm/nouveau/dispnv50/disp.c
View File

@ -322,8 +322,13 @@ nv50_outp_atomic_check_view(struct drm_encoder *encoder,
switch (connector->connector_type) { switch (connector->connector_type) {
case DRM_MODE_CONNECTOR_LVDS: case DRM_MODE_CONNECTOR_LVDS:
case DRM_MODE_CONNECTOR_eDP: case DRM_MODE_CONNECTOR_eDP:
/* Force use of scaler for non-EDID modes. */ /* Don't force scaler for EDID modes with
if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) * same size as the native one (e.g. different
* refresh rate)
*/
if (adjusted_mode->hdisplay == native_mode->hdisplay &&
adjusted_mode->vdisplay == native_mode->vdisplay &&
adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
break; break;
mode = native_mode; mode = native_mode;
asyc->scaler.full = true; asyc->scaler.full = true;

28
drivers/gpu/drm/nouveau/dispnv50/head.c
View File

@ -169,14 +169,34 @@ nv50_head_atomic_check_view(struct nv50_head_atom *armh,
*/ */
switch (mode) { switch (mode) {
case DRM_MODE_SCALE_CENTER: case DRM_MODE_SCALE_CENTER:
asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW); /* NOTE: This will cause scaling when the input is
asyh->view.oH = min((u16)umode_vdisplay, asyh->view.oH); * larger than the output.
/* fall-through */ */
asyh->view.oW = min(asyh->view.iW, asyh->view.oW);
asyh->view.oH = min(asyh->view.iH, asyh->view.oH);
break;
case DRM_MODE_SCALE_ASPECT: case DRM_MODE_SCALE_ASPECT:
if (asyh->view.oH < asyh->view.oW) { /* Determine whether the scaling should be on width or on
* height. This is done by comparing the aspect ratios of the
* sizes. If the output AR is larger than input AR, that means
* we want to change the width (letterboxed on the
* left/right), otherwise on the height (letterboxed on the
* top/bottom).
*
* E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR
* screen will have letterboxes on the left/right. However a
* 16:9 (1.777) AR image on that same screen will have
* letterboxes on the top/bottom.
*
* inputAR = iW / iH; outputAR = oW / oH
* outputAR > inputAR is equivalent to oW * iH > iW * oH
*/
if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) {
/* Recompute output width, i.e. left/right letterbox */
u32 r = (asyh->view.iW << 19) / asyh->view.iH; u32 r = (asyh->view.iW << 19) / asyh->view.iH;
asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19; asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
} else { } else {
/* Recompute output height, i.e. top/bottom letterbox */
u32 r = (asyh->view.iH << 19) / asyh->view.iW; u32 r = (asyh->view.iH << 19) / asyh->view.iW;
asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
} }

2
drivers/gpu/drm/nouveau/include/nvif/cl0002.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL0002_H__ #ifndef __NVIF_CL0002_H__
#define __NVIF_CL0002_H__ #define __NVIF_CL0002_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl0046.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL0046_H__ #ifndef __NVIF_CL0046_H__
#define __NVIF_CL0046_H__ #define __NVIF_CL0046_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl006b.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL006B_H__ #ifndef __NVIF_CL006B_H__
#define __NVIF_CL006B_H__ #define __NVIF_CL006B_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl0080.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL0080_H__ #ifndef __NVIF_CL0080_H__
#define __NVIF_CL0080_H__ #define __NVIF_CL0080_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl506e.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL506E_H__ #ifndef __NVIF_CL506E_H__
#define __NVIF_CL506E_H__ #define __NVIF_CL506E_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl506f.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL506F_H__ #ifndef __NVIF_CL506F_H__
#define __NVIF_CL506F_H__ #define __NVIF_CL506F_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl5070.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL5070_H__ #ifndef __NVIF_CL5070_H__
#define __NVIF_CL5070_H__ #define __NVIF_CL5070_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl507a.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL507A_H__ #ifndef __NVIF_CL507A_H__
#define __NVIF_CL507A_H__ #define __NVIF_CL507A_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl507b.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL507B_H__ #ifndef __NVIF_CL507B_H__
#define __NVIF_CL507B_H__ #define __NVIF_CL507B_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl507c.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL507C_H__ #ifndef __NVIF_CL507C_H__
#define __NVIF_CL507C_H__ #define __NVIF_CL507C_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl507d.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL507D_H__ #ifndef __NVIF_CL507D_H__
#define __NVIF_CL507D_H__ #define __NVIF_CL507D_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl507e.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL507E_H__ #ifndef __NVIF_CL507E_H__
#define __NVIF_CL507E_H__ #define __NVIF_CL507E_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl826e.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL826E_H__ #ifndef __NVIF_CL826E_H__
#define __NVIF_CL826E_H__ #define __NVIF_CL826E_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl826f.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL826F_H__ #ifndef __NVIF_CL826F_H__
#define __NVIF_CL826F_H__ #define __NVIF_CL826F_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl906f.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL906F_H__ #ifndef __NVIF_CL906F_H__
#define __NVIF_CL906F_H__ #define __NVIF_CL906F_H__

2
drivers/gpu/drm/nouveau/include/nvif/cl9097.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL9097_H__ #ifndef __NVIF_CL9097_H__
#define __NVIF_CL9097_H__ #define __NVIF_CL9097_H__

2
drivers/gpu/drm/nouveau/include/nvif/cla06f.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CLA06F_H__ #ifndef __NVIF_CLA06F_H__
#define __NVIF_CLA06F_H__ #define __NVIF_CLA06F_H__

2
drivers/gpu/drm/nouveau/include/nvif/class.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CLASS_H__ #ifndef __NVIF_CLASS_H__
#define __NVIF_CLASS_H__ #define __NVIF_CLASS_H__

2
drivers/gpu/drm/nouveau/include/nvif/clc36f.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CLC36F_H__ #ifndef __NVIF_CLC36F_H__
#define __NVIF_CLC36F_H__ #define __NVIF_CLC36F_H__

2
drivers/gpu/drm/nouveau/include/nvif/clc37b.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CLC37B_H__ #ifndef __NVIF_CLC37B_H__
#define __NVIF_CLC37B_H__ #define __NVIF_CLC37B_H__

2
drivers/gpu/drm/nouveau/include/nvif/clc37e.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CLC37E_H__ #ifndef __NVIF_CLC37E_H__
#define __NVIF_CLC37E_H__ #define __NVIF_CLC37E_H__

2
drivers/gpu/drm/nouveau/include/nvif/client.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CLIENT_H__ #ifndef __NVIF_CLIENT_H__
#define __NVIF_CLIENT_H__ #define __NVIF_CLIENT_H__

2
drivers/gpu/drm/nouveau/include/nvif/device.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_DEVICE_H__ #ifndef __NVIF_DEVICE_H__
#define __NVIF_DEVICE_H__ #define __NVIF_DEVICE_H__

2
drivers/gpu/drm/nouveau/include/nvif/driver.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_DRIVER_H__ #ifndef __NVIF_DRIVER_H__
#define __NVIF_DRIVER_H__ #define __NVIF_DRIVER_H__
#include <nvif/os.h> #include <nvif/os.h>

2
drivers/gpu/drm/nouveau/include/nvif/event.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_EVENT_H__ #ifndef __NVIF_EVENT_H__
#define __NVIF_EVENT_H__ #define __NVIF_EVENT_H__

2
drivers/gpu/drm/nouveau/include/nvif/if0000.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0000_H__ #ifndef __NVIF_IF0000_H__
#define __NVIF_IF0000_H__ #define __NVIF_IF0000_H__

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