[POWERPC] pasemi: iommu support
I/O TLB support for PA6T-1682M. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Olof Johansson
Paul Mackerras
parent
f9fba5b72d
commit
31c56d820e
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@ -720,6 +720,7 @@ source arch/powerpc/platforms/86xx/Kconfig
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source arch/powerpc/platforms/8xx/Kconfig
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source arch/powerpc/platforms/cell/Kconfig
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source arch/powerpc/platforms/ps3/Kconfig
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source arch/powerpc/platforms/pasemi/Kconfig
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menu "Kernel options"
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@ -0,0 +1,10 @@
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menu "PA Semi PWRficient options"
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depends on PPC_PASEMI
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config PPC_PASEMI_IOMMU
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bool "PA Semi IOMMU support"
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depends on PPC_PASEMI
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help
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IOMMU support for PA6T-1682M
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endmenu
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@ -1,2 +1,2 @@
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obj-y += setup.o pci.o time.o idle.o powersave.o
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obj-y += setup.o pci.o time.o idle.o powersave.o iommu.o
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@ -0,0 +1,281 @@
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/*
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* Copyright (C) 2005-2007, PA Semi, Inc
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*
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* Maintained by: Olof Johansson <olof@lixom.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#undef DEBUG
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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#include <asm/iommu.h>
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#include <asm/machdep.h>
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#include <asm/abs_addr.h>
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#define IOBMAP_PAGE_SHIFT 12
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#define IOBMAP_PAGE_SIZE (1 << IOBMAP_PAGE_SHIFT)
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#define IOBMAP_PAGE_MASK (IOBMAP_PAGE_SIZE - 1)
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#define IOBMAP_PAGE_FACTOR (PAGE_SHIFT - IOBMAP_PAGE_SHIFT)
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#define IOB_BASE 0xe0000000
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#define IOB_SIZE 0x3000
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/* Configuration registers */
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#define IOBCAP_REG 0x10
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#define IOBCOM_REG 0x40
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/* Enable IOB address translation */
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#define IOBCOM_ATEN 0x00000100
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/* Address decode configuration register */
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#define IOB_AD_REG 0x53
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/* IOBCOM_AD_REG fields */
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#define IOB_AD_VGPRT 0x00000e00
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#define IOB_AD_VGAEN 0x00000100
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/* Direct mapping settings */
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#define IOB_AD_MPSEL_MASK 0x00000030
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#define IOB_AD_MPSEL_B38 0x00000000
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#define IOB_AD_MPSEL_B40 0x00000010
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#define IOB_AD_MPSEL_B42 0x00000020
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/* Translation window size / enable */
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#define IOB_AD_TRNG_MASK 0x00000003
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#define IOB_AD_TRNG_256M 0x00000000
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#define IOB_AD_TRNG_2G 0x00000001
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#define IOB_AD_TRNG_128G 0x00000003
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#define IOB_TABLEBASE_REG 0x55
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/* Base of the 64 4-byte L1 registers */
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#define IOB_XLT_L1_REGBASE 0xac0
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/* Register to invalidate TLB entries */
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#define IOB_AT_INVAL_TLB_REG 0xb40
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/* The top two bits of the level 1 entry contains valid and type flags */
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#define IOBMAP_L1E_V 0x40000000
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#define IOBMAP_L1E_V_B 0x80000000
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/* For big page entries, the bottom two bits contains flags */
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#define IOBMAP_L1E_BIG_CACHED 0x00000002
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#define IOBMAP_L1E_BIG_PRIORITY 0x00000001
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/* For regular level 2 entries, top 2 bits contain valid and cache flags */
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#define IOBMAP_L2E_V 0x80000000
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#define IOBMAP_L2E_V_CACHED 0xc0000000
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static u32 *iob;
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static u32 iob_l1_emptyval;
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static u32 iob_l2_emptyval;
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static u32 *iob_l2_base;
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static struct iommu_table iommu_table_iobmap;
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static int iommu_table_iobmap_inited;
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static void iobmap_build(struct iommu_table *tbl, long index,
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long npages, unsigned long uaddr,
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enum dma_data_direction direction)
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{
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u32 *ip;
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u32 rpn;
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unsigned long bus_addr;
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pr_debug("iobmap: build at: %lx, %lx, addr: %lx\n", index, npages, uaddr);
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bus_addr = (tbl->it_offset + index) << PAGE_SHIFT;
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npages <<= IOBMAP_PAGE_FACTOR;
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index <<= IOBMAP_PAGE_FACTOR;
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ip = ((u32 *)tbl->it_base) + index;
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while (npages--) {
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rpn = virt_to_abs(uaddr) >> IOBMAP_PAGE_SHIFT;
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*(ip++) = IOBMAP_L2E_V | rpn;
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/* invalidate tlb, can be optimized more */
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out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14);
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uaddr += IOBMAP_PAGE_SIZE;
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bus_addr += IOBMAP_PAGE_SIZE;
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}
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}
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static void iobmap_free(struct iommu_table *tbl, long index,
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long npages)
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{
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u32 *ip;
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unsigned long bus_addr;
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pr_debug("iobmap: free at: %lx, %lx\n", index, npages);
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bus_addr = (tbl->it_offset + index) << PAGE_SHIFT;
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npages <<= IOBMAP_PAGE_FACTOR;
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index <<= IOBMAP_PAGE_FACTOR;
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ip = ((u32 *)tbl->it_base) + index;
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while (npages--) {
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*(ip++) = iob_l2_emptyval;
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/* invalidate tlb, can be optimized more */
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out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14);
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bus_addr += IOBMAP_PAGE_SIZE;
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}
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}
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static void iommu_table_iobmap_setup(void)
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{
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pr_debug(" -> %s\n", __func__);
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iommu_table_iobmap.it_busno = 0;
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iommu_table_iobmap.it_offset = 0;
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/* it_size is in number of entries */
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iommu_table_iobmap.it_size = 0x80000000 >> PAGE_SHIFT;
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/* Initialize the common IOMMU code */
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iommu_table_iobmap.it_base = (unsigned long)iob_l2_base;
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iommu_table_iobmap.it_index = 0;
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/* XXXOJN tune this to avoid IOB cache invals.
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* Should probably be 8 (64 bytes)
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*/
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iommu_table_iobmap.it_blocksize = 4;
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iommu_init_table(&iommu_table_iobmap, 0);
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pr_debug(" <- %s\n", __func__);
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}
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static void pci_dma_bus_setup_pasemi(struct pci_bus *bus)
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{
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struct device_node *dn;
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pr_debug("pci_dma_bus_setup, bus %p, bus->self %p\n", bus, bus->self);
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if (!iommu_table_iobmap_inited) {
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iommu_table_iobmap_inited = 1;
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iommu_table_iobmap_setup();
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}
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dn = pci_bus_to_OF_node(bus);
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if (dn)
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PCI_DN(dn)->iommu_table = &iommu_table_iobmap;
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}
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static void pci_dma_dev_setup_pasemi(struct pci_dev *dev)
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{
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pr_debug("pci_dma_dev_setup, dev %p (%s)\n", dev, pci_name(dev));
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/* DMA device is untranslated, but all other PCI-e goes through
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* the IOMMU
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*/
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if (dev->vendor == 0x1959 && dev->device == 0xa007)
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dev->dev.archdata.dma_ops = &dma_direct_ops;
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else
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dev->dev.archdata.dma_data = &iommu_table_iobmap;
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}
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static void pci_dma_bus_setup_null(struct pci_bus *b) { }
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static void pci_dma_dev_setup_null(struct pci_dev *d) { }
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int iob_init(struct device_node *dn)
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{
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unsigned long tmp;
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u32 regword;
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int i;
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pr_debug(" -> %s\n", __func__);
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/* Allocate a spare page to map all invalid IOTLB pages. */
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tmp = lmb_alloc(IOBMAP_PAGE_SIZE, IOBMAP_PAGE_SIZE);
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if (!tmp)
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panic("IOBMAP: Cannot allocate spare page!");
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/* Empty l1 is marked invalid */
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iob_l1_emptyval = 0;
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/* Empty l2 is mapped to dummy page */
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iob_l2_emptyval = IOBMAP_L2E_V | (tmp >> IOBMAP_PAGE_SHIFT);
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iob = ioremap(IOB_BASE, IOB_SIZE);
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if (!iob)
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panic("IOBMAP: Cannot map registers!");
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/* setup direct mapping of the L1 entries */
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for (i = 0; i < 64; i++) {
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/* Each L1 covers 32MB, i.e. 8K entries = 32K of ram */
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regword = IOBMAP_L1E_V | (__pa(iob_l2_base + i*0x2000) >> 12);
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out_le32(iob+IOB_XLT_L1_REGBASE+i, regword);
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}
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/* set 2GB translation window, based at 0 */
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regword = in_le32(iob+IOB_AD_REG);
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regword &= ~IOB_AD_TRNG_MASK;
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regword |= IOB_AD_TRNG_2G;
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out_le32(iob+IOB_AD_REG, regword);
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/* Enable translation */
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regword = in_le32(iob+IOBCOM_REG);
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regword |= IOBCOM_ATEN;
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out_le32(iob+IOBCOM_REG, regword);
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pr_debug(" <- %s\n", __func__);
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return 0;
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}
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/* These are called very early. */
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void iommu_init_early_pasemi(void)
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{
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int iommu_off;
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#ifndef CONFIG_PPC_PASEMI_IOMMU
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iommu_off = 1;
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#else
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iommu_off = of_chosen &&
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get_property(of_chosen, "linux,iommu-off", NULL);
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#endif
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if (iommu_off) {
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/* Direct I/O, IOMMU off */
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ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_null;
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ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_null;
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pci_dma_ops = &dma_direct_ops;
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return;
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}
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iob_init(NULL);
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ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pasemi;
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ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pasemi;
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ppc_md.tce_build = iobmap_build;
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ppc_md.tce_free = iobmap_free;
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pci_dma_ops = &dma_iommu_ops;
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}
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void __init alloc_iobmap_l2(void)
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{
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#ifndef CONFIG_PPC_PASEMI_IOMMU
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return;
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#endif
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/* For 2G space, 8x64 pages (2^21 bytes) is max total l2 size */
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iob_l2_base = (u32 *)abs_to_virt(lmb_alloc_base(1UL<<21, 1UL<<21, 0x80000000));
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printk(KERN_INFO "IOBMAP L2 allocated at: %p\n", iob_l2_base);
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}
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@ -4,6 +4,9 @@
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extern unsigned long pas_get_boot_time(void);
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extern void pas_pci_init(void);
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extern void __devinit pas_pci_irq_fixup(struct pci_dev *dev);
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extern void __devinit pas_pci_dma_dev_setup(struct pci_dev *dev);
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extern void __init alloc_iobmap_l2(void);
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extern void __init pasemi_idle_init(void);
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@ -12,4 +15,5 @@ extern void idle_spin(void);
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extern void idle_doze(void);
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#endif /* _PASEMI_PASEMI_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2006 PA Semi, Inc
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* Copyright (C) 2006-2007 PA Semi, Inc
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*
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* Authors: Kip Walker, PA Semi
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* Olof Johansson, PA Semi
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@ -87,9 +87,6 @@ void __init pas_setup_arch(void)
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/* Setup SMP callback */
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smp_ops = &pas_smp_ops;
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#endif
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/* no iommu yet */
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pci_dma_ops = &dma_direct_ops;
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/* Lookup PCI hosts */
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pas_pci_init();
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@ -207,6 +204,11 @@ static int pas_machine_check_handler(struct pt_regs *regs)
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return !!(srr1 & 0x2);
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}
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static void __init pas_init_early(void)
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{
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iommu_init_early_pasemi();
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}
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/*
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* Called very early, MMU is off, device-tree isn't unflattened
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@ -220,6 +222,8 @@ static int __init pas_probe(void)
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hpte_init_native();
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alloc_iobmap_l2();
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return 1;
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}
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@ -227,6 +231,7 @@ define_machine(pas) {
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.name = "PA Semi PA6T-1682M",
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.probe = pas_probe,
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.setup_arch = pas_setup_arch,
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.init_early = pas_init_early,
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.init_IRQ = pas_init_IRQ,
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.get_irq = mpic_get_irq,
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.restart = pas_restart,
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@ -99,6 +99,7 @@ extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
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extern void iommu_init_early_pSeries(void);
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extern void iommu_init_early_iSeries(void);
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extern void iommu_init_early_dart(void);
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extern void iommu_init_early_pasemi(void);
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#ifdef CONFIG_PCI
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extern void pci_iommu_init(void);
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