From 31a2d5113e53a308a2b7a124f97db984d223c06f Mon Sep 17 00:00:00 2001 From: Jolly Shah Date: Wed, 27 Feb 2019 12:51:09 -0800 Subject: [PATCH] include: dt-binding: clock: Rename zynqmp header file Rename file name of ZynqMP clk dt-bindings to align with file name of reset and power dt-bindings. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Signed-off-by: Michal Simek --- .../firmware/xilinx/xlnx,zynqmp-firmware.txt | 2 +- .../{xlnx,zynqmp-clk.h => xlnx-zynqmp-clk.h} | 26 +++++++++++++------ 2 files changed, 19 insertions(+), 9 deletions(-) rename include/dt-bindings/clock/{xlnx,zynqmp-clk.h => xlnx-zynqmp-clk.h} (85%) diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt index 614bac55df86..45d259cfc0b2 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt @@ -62,7 +62,7 @@ order to provide an optional (E)MIO clock source: Output clocks are registered based on clock information received from firmware. Output clocks indexes are mentioned in -include/dt-bindings/clock/xlnx,zynqmp-clk.h. +include/dt-bindings/clock/xlnx-zynqmp-clk.h. ------- Example diff --git a/include/dt-bindings/clock/xlnx,zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h similarity index 85% rename from include/dt-bindings/clock/xlnx,zynqmp-clk.h rename to include/dt-bindings/clock/xlnx-zynqmp-clk.h index 4aebe6e2049e..cdc4c0b9a374 100644 --- a/include/dt-bindings/clock/xlnx,zynqmp-clk.h +++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -54,14 +54,14 @@ #define IOU_SWITCH 42 #define GEM_TSU_REF 43 #define GEM_TSU 44 -#define GEM0_REF 45 -#define GEM1_REF 46 -#define GEM2_REF 47 -#define GEM3_REF 48 -#define GEM0_TX 49 -#define GEM1_TX 50 -#define GEM2_TX 51 -#define GEM3_TX 52 +#define GEM0_TX 45 +#define GEM1_TX 46 +#define GEM2_TX 47 +#define GEM3_TX 48 +#define GEM0_RX 49 +#define GEM1_RX 50 +#define GEM2_RX 51 +#define GEM3_RX 52 #define QSPI_REF 53 #define SDIO0_REF 54 #define SDIO1_REF 55 @@ -112,5 +112,15 @@ #define VPLL_POST_SRC 100 #define CAN0_MIO 101 #define CAN1_MIO 102 +#define ACPU_FULL 103 +#define GEM0_REF 104 +#define GEM1_REF 105 +#define GEM2_REF 106 +#define GEM3_REF 107 +#define GEM0_REF_UNG 108 +#define GEM1_REF_UNG 109 +#define GEM2_REF_UNG 110 +#define GEM3_REF_UNG 111 +#define LPD_WDT 112 #endif