KVM: arm/arm64: Separate guest and uaccess writes to dist {sc}active
Factor out the core register modifier functionality from the entry points from the register description table, and only call the prepare/finish functions from the guest path, not the uaccess path. Signed-off-by: Christoffer Dall <cdall@linaro.org> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
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2602087ef4
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3197191e55
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@ -311,10 +311,12 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = {
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vgic_mmio_read_pending, vgic_mmio_write_cpending, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
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vgic_mmio_read_active, vgic_mmio_write_sactive, NULL, NULL, 1,
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vgic_mmio_read_active, vgic_mmio_write_sactive,
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NULL, vgic_mmio_uaccess_write_sactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
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vgic_mmio_read_active, vgic_mmio_write_cactive, NULL, NULL, 1,
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vgic_mmio_read_active, vgic_mmio_write_cactive,
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NULL, vgic_mmio_uaccess_write_cactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
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vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
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@ -456,11 +456,13 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = {
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vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
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vgic_mmio_read_active, vgic_mmio_write_sactive, NULL, NULL, 1,
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vgic_mmio_read_active, vgic_mmio_write_sactive,
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NULL, vgic_mmio_uaccess_write_sactive, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
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vgic_mmio_read_active, vgic_mmio_write_cactive, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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vgic_mmio_read_active, vgic_mmio_write_cactive,
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NULL, vgic_mmio_uaccess_write_cactive,
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1, VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
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vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
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8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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@ -251,38 +251,74 @@ static void vgic_change_active_finish(struct kvm_vcpu *vcpu, u32 intid)
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kvm_arm_resume_guest(vcpu->kvm);
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}
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void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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static void __vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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int i;
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vgic_change_active_prepare(vcpu, intid);
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for_each_set_bit(i, &val, len * 8) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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vgic_mmio_change_active(vcpu, irq, false);
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vgic_put_irq(vcpu->kvm, irq);
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}
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}
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void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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vgic_change_active_prepare(vcpu, intid);
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__vgic_mmio_write_cactive(vcpu, addr, len, val);
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vgic_change_active_finish(vcpu, intid);
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}
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void vgic_mmio_uaccess_write_cactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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__vgic_mmio_write_cactive(vcpu, addr, len, val);
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}
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static void __vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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int i;
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for_each_set_bit(i, &val, len * 8) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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vgic_mmio_change_active(vcpu, irq, true);
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vgic_put_irq(vcpu->kvm, irq);
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}
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}
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void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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int i;
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vgic_change_active_prepare(vcpu, intid);
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for_each_set_bit(i, &val, len * 8) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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vgic_mmio_change_active(vcpu, irq, true);
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vgic_put_irq(vcpu->kvm, irq);
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}
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__vgic_mmio_write_sactive(vcpu, addr, len, val);
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vgic_change_active_finish(vcpu, intid);
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}
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void vgic_mmio_uaccess_write_sactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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__vgic_mmio_write_sactive(vcpu, addr, len, val);
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}
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unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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@ -167,6 +167,14 @@ void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val);
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void vgic_mmio_uaccess_write_cactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val);
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void vgic_mmio_uaccess_write_sactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val);
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unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len);
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