Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 4278/1: configure pxa27x I2C SCL as "input"
  [ARM] 4272/1: Missing symbol h1940_pm_return fix
  [ARM] 4235/1: ns9xxx: declare the clock functions as "const"
  [ARM] 4271/1: iop32x: fix ep80219 detection (support iq80219 platforms)
  [ARM] 4270/2: mach-s3c2443/irq.c off by one error in dma irqs
This commit is contained in:
Linus Torvalds 2007-03-24 17:01:45 -07:00
commit 317ec6cd00
7 changed files with 68 additions and 13 deletions

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@ -4,6 +4,9 @@ menu "IOP32x Implementation Options"
comment "IOP32x Platform Types" comment "IOP32x Platform Types"
config MACH_EP80219
bool
config MACH_GLANTANK config MACH_GLANTANK
bool "Enable support for the IO-Data GLAN Tank" bool "Enable support for the IO-Data GLAN Tank"
help help
@ -19,6 +22,7 @@ config ARCH_IQ80321
config ARCH_IQ31244 config ARCH_IQ31244
bool "Enable support for EP80219/IQ31244" bool "Enable support for EP80219/IQ31244"
select MACH_EP80219
help help
Say Y here if you want to run your kernel on the Intel EP80219 Say Y here if you want to run your kernel on the Intel EP80219
evaluation kit for the Intel 80219 processor (a IOP321 variant) evaluation kit for the Intel 80219 processor (a IOP321 variant)

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@ -39,22 +39,35 @@
#include <asm/arch/time.h> #include <asm/arch/time.h>
/* /*
* The EP80219 and IQ31244 use the same machine ID. To find out * Until March of 2007 iq31244 platforms and ep80219 platforms shared the
* which of the two we're running on, we look at the processor ID. * same machine id, and the processor type was used to select board type.
* However this assumption breaks for an iq80219 board which is an iop219
* processor on an iq31244 board. The force_ep80219 flag has been added
* for old boot loaders using the iq31244 machine id for an ep80219 platform.
*/ */
static int force_ep80219;
static int is_80219(void) static int is_80219(void)
{ {
extern int processor_id; extern int processor_id;
return !!((processor_id & 0xffffffe0) == 0x69052e20); return !!((processor_id & 0xffffffe0) == 0x69052e20);
} }
static int is_ep80219(void)
{
if (machine_is_ep80219() || force_ep80219)
return 1;
else
return 0;
}
/* /*
* EP80219/IQ31244 timer tick configuration. * EP80219/IQ31244 timer tick configuration.
*/ */
static void __init iq31244_timer_init(void) static void __init iq31244_timer_init(void)
{ {
if (is_80219()) { if (is_ep80219()) {
/* 33.333 MHz crystal. */ /* 33.333 MHz crystal. */
iop_init_time(200000000); iop_init_time(200000000);
} else { } else {
@ -165,12 +178,18 @@ static struct hw_pci iq31244_pci __initdata = {
static int __init iq31244_pci_init(void) static int __init iq31244_pci_init(void)
{ {
if (machine_is_iq31244()) { if (is_ep80219())
pci_common_init(&ep80219_pci);
else if (machine_is_iq31244()) {
if (is_80219()) { if (is_80219()) {
pci_common_init(&ep80219_pci); printk("note: iq31244 board type has been selected\n");
} else { printk("note: to select ep80219 operation:\n");
pci_common_init(&iq31244_pci); printk("\t1/ specify \"force_ep80219\" on the kernel"
" command line\n");
printk("\t2/ update boot loader to pass"
" the ep80219 id: %d\n", MACH_TYPE_EP80219);
} }
pci_common_init(&iq31244_pci);
} }
return 0; return 0;
@ -277,10 +296,18 @@ static void __init iq31244_init_machine(void)
platform_device_register(&iq31244_flash_device); platform_device_register(&iq31244_flash_device);
platform_device_register(&iq31244_serial_device); platform_device_register(&iq31244_serial_device);
if (is_80219()) if (is_ep80219())
pm_power_off = ep80219_power_off; pm_power_off = ep80219_power_off;
} }
static int __init force_ep80219_setup(char *str)
{
force_ep80219 = 1;
return 1;
}
__setup("force_ep80219", force_ep80219_setup);
MACHINE_START(IQ31244, "Intel IQ31244") MACHINE_START(IQ31244, "Intel IQ31244")
/* Maintainer: Intel Corp. */ /* Maintainer: Intel Corp. */
.phys_io = IQ31244_UART, .phys_io = IQ31244_UART,
@ -291,3 +318,19 @@ MACHINE_START(IQ31244, "Intel IQ31244")
.timer = &iq31244_timer, .timer = &iq31244_timer,
.init_machine = iq31244_init_machine, .init_machine = iq31244_init_machine,
MACHINE_END MACHINE_END
/* There should have been an ep80219 machine identifier from the beginning.
* Boot roms older than March 2007 do not know the ep80219 machine id. Pass
* "force_ep80219" on the kernel command line, otherwise iq31244 operation
* will be selected.
*/
MACHINE_START(EP80219, "Intel EP80219")
/* Maintainer: Intel Corp. */
.phys_io = IQ31244_UART,
.io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = iq31244_map_io,
.init_irq = iop32x_init_irq,
.timer = &iq31244_timer,
.init_machine = iq31244_init_machine,
MACHINE_END

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@ -202,7 +202,9 @@ static void __init h1940_map_io(void)
/* setup PM */ /* setup PM */
#ifdef CONFIG_PM_H1940
memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
#endif
s3c2410_pm_init(); s3c2410_pm_init();
} }

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@ -224,7 +224,9 @@ static void __init rx3715_init_irq(void)
static void __init rx3715_init_machine(void) static void __init rx3715_init_machine(void)
{ {
#ifdef CONFIG_PM_H1940
memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
#endif
s3c2410_pm_init(); s3c2410_pm_init();
s3c24xx_fb_set_platdata(&rx3715_lcdcfg); s3c24xx_fb_set_platdata(&rx3715_lcdcfg);

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@ -137,7 +137,7 @@ static struct irq_chip s3c2443_irq_lcd = {
static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc) static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
{ {
s3c2443_irq_demux(IRQ_S3C2443_DMA1, 6); s3c2443_irq_demux(IRQ_S3C2443_DMA0, 6);
} }
#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0)) #define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))

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@ -11,6 +11,7 @@
#ifndef __ASM_ARCH_CLOCK_H #ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H
static inline u32 ns9xxx_systemclock(void) __attribute__((const));
static inline u32 ns9xxx_systemclock(void) static inline u32 ns9xxx_systemclock(void)
{ {
/* /*
@ -19,17 +20,20 @@ static inline u32 ns9xxx_systemclock(void)
return 353894400; return 353894400;
} }
static inline const u32 ns9xxx_cpuclock(void) static inline u32 ns9xxx_cpuclock(void) __attribute__((const));
static inline u32 ns9xxx_cpuclock(void)
{ {
return ns9xxx_systemclock() / 2; return ns9xxx_systemclock() / 2;
} }
static inline const u32 ns9xxx_ahbclock(void) static inline u32 ns9xxx_ahbclock(void) __attribute__((const));
static inline u32 ns9xxx_ahbclock(void)
{ {
return ns9xxx_systemclock() / 4; return ns9xxx_systemclock() / 4;
} }
static inline const u32 ns9xxx_bbusclock(void) static inline u32 ns9xxx_bbusclock(void) __attribute__((const));
static inline u32 ns9xxx_bbusclock(void)
{ {
return ns9xxx_systemclock() / 8; return ns9xxx_systemclock() / 8;
} }

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@ -1476,7 +1476,7 @@
#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT) #define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)
#define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT) #define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT)
#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT) #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_OUT) #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN)
#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
/* /*