ice: Do not check INTEVENT bit for OICR interrupts
According to the hardware spec, checking the INTEVENT bit isn't a
reliable way to detect if an OICR interrupt has occurred. This is
because this bit can be cleared by the hardware/firmware before the
interrupt service routine has run. So instead, just check for OICR
events every time.
Fixes: 940b61af02
("ice: Initialize PF and setup miscellaneous interrupt")
Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com>
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: Tony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
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@ -121,8 +121,6 @@
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#define PFINT_FW_CTL_CAUSE_ENA_S 30
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#define PFINT_FW_CTL_CAUSE_ENA_M BIT(PFINT_FW_CTL_CAUSE_ENA_S)
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#define PFINT_OICR 0x0016CA00
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#define PFINT_OICR_INTEVENT_S 0
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#define PFINT_OICR_INTEVENT_M BIT(PFINT_OICR_INTEVENT_S)
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#define PFINT_OICR_HLP_RDY_S 14
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#define PFINT_OICR_HLP_RDY_M BIT(PFINT_OICR_HLP_RDY_S)
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#define PFINT_OICR_CPM_RDY_S 15
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@ -1722,9 +1722,6 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)
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oicr = rd32(hw, PFINT_OICR);
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ena_mask = rd32(hw, PFINT_OICR_ENA);
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if (!(oicr & PFINT_OICR_INTEVENT_M))
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goto ena_intr;
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if (oicr & PFINT_OICR_GRST_M) {
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u32 reset;
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/* we have a reset warning */
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@ -1782,7 +1779,6 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)
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}
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ret = IRQ_HANDLED;
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ena_intr:
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/* re-enable interrupt causes that are not handled during this pass */
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wr32(hw, PFINT_OICR_ENA, ena_mask);
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if (!test_bit(__ICE_DOWN, pf->state)) {
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