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Merge branch 'remotes/lorenzo/pci/meson' 

- Fix meson PERST# GPIO polarity problem (Remi Pommarel)

  - Add DT bindings for Amlogic Meson G12A (Neil Armstrong)

  - Fix meson clock names to match DT bindings (Neil Armstrong)

  - Add meson support for Amlogic G12A SoC with separate shared PHY (Neil
    Armstrong)

  - Add meson extended PCIe PHY functions for Amlogic G12A USB3+PCIe combo
    PHY (Neil Armstrong)

  - Add arm64 DT for Amlogic G12A PCIe controller node (Neil Armstrong)

  - Add commented-out description of VIM3 USB3/PCIe mux in arm64 DT (Neil
    Armstrong)

* remotes/lorenzo/pci/meson:
  arm64: dts: khadas-vim3: add commented support for PCIe
  arm64: dts: meson-g12a: Add PCIe node
  phy: meson-g12a-usb3-pcie: Add support for PCIe mode
  PCI: amlogic: meson: Add support for G12A
  PCI: amlogic: Fix probed clock names
  dt-bindings: pci: amlogic, meson-pcie: Add G12A bindings
  PCI: amlogic: Fix reset assertion via gpio descriptor
This commit is contained in:
Bjorn Helgaas 2019-11-28 08:54:46 -06:00
parent e63758e279 ba1f8af7f7
commit 30c50d3a26
9 changed files with 293 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
View File

@ -9,13 +9,16 @@ Additional properties are described here:
Required properties:
- compatible:
should contain "amlogic,axg-pcie" to identify the core.
should contain :
- "amlogic,axg-pcie" for AXG SoC Family
- "amlogic,g12a-pcie" for G12A SoC Family
to identify the core.
- reg:
should contain the configuration address space.
- reg-names: Must be
- "elbi" External local bus interface registers
- "cfg" Meson specific registers
- "phy" Meson PCIE PHY registers
- "phy" Meson PCIE PHY registers for AXG SoC Family
- "config" PCIe configuration space
- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
- clocks: Must contain an entry for each entry in clock-names.
@ -23,12 +26,13 @@ Required properties:
- "pclk" PCIe GEN 100M PLL clock
- "port" PCIe_x(A or B) RC clock gate
- "general" PCIe Phy clock
- "mipi" PCIe_x(A or B) 100M ref clock gate
- "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family
- resets: phandle to the reset lines.
- reset-names: must contain "phy" "port" and "apb"
- "phy" Share PHY reset
- "phy" Share PHY reset for AXG SoC Family
- "port" Port A or B reset
- "apb" Share APB reset
- phys: should contain a phandle to the shared phy for G12A SoC Family
- device_type:
should be "pci". As specified in designware-pcie.txt

33
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
View File

@ -95,6 +95,39 @@
#size-cells = <2>;
ranges;
pcie: pcie@fc000000 {
compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
reg = <0x0 0xfc000000 0x0 0x400000
0x0 0xff648000 0x0 0x2000
0x0 0xfc400000 0x0 0x200000>;
reg-names = "elbi", "cfg", "config";
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x0 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
clocks = <&clkc CLKID_PCIE_PHY
&clkc CLKID_PCIE_COMB
&clkc CLKID_PCIE_PLL>;
clock-names = "general",
"pclk",
"port";
resets = <&reset RESET_PCIE_CTRL_A>,
<&reset RESET_PCIE_APB>;
reset-names = "port",
"apb";
num-lanes = <1>;
phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
phy-names = "pcie";
status = "disabled";
};
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-axg-dwmac",
"snps,dwmac-3.70a",

25
arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
View File

@ -14,3 +14,28 @@
/ {
compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b";
};
/*
* The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
* lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
* an USB3.0 Type A connector and a M.2 Key M slot.
* The PHY driving these differential lines is shared between
* the USB3.0 controller and the PCIe Controller, thus only
* a single controller can use it.
* If the MCU is configured to mux the PCIe/USB3.0 differential lines
* to the M.2 Key M slot, uncomment the following block to disable
* USB3.0 from the USB Complex and enable the PCIe controller.
* The End User is not expected to uncomment the following except for
* testing purposes, but instead rely on the firmware/bootloader to
* update these nodes accordingly if PCIe mode is selected by the MCU.
*/
/*
&pcie {
status = "okay";
};
&usb {
phys = <&usb2_phy0>, <&usb2_phy1>;
phy-names = "usb2-phy0", "usb2-phy1";
};
*/

25
arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts
View File

@ -14,3 +14,28 @@
/ {
compatible = "khadas,vim3", "amlogic,s922x", "amlogic,g12b";
};
/*
* The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
* lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
* an USB3.0 Type A connector and a M.2 Key M slot.
* The PHY driving these differential lines is shared between
* the USB3.0 controller and the PCIe Controller, thus only
* a single controller can use it.
* If the MCU is configured to mux the PCIe/USB3.0 differential lines
* to the M.2 Key M slot, uncomment the following block to disable
* USB3.0 from the USB Complex and enable the PCIe controller.
* The End User is not expected to uncomment the following except for
* testing purposes, but instead rely on the firmware/bootloader to
* update these nodes accordingly if PCIe mode is selected by the MCU.
*/
/*
&pcie {
status = "okay";
};
&usb {
phys = <&usb2_phy0>, <&usb2_phy1>;
phy-names = "usb2-phy0", "usb2-phy1";
};
*/

4
arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
View File

@ -246,6 +246,10 @@
linux,rc-map-name = "rc-khadas";
};
&pcie {
reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>;
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;

25
arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
View File

@ -68,3 +68,28 @@
clock-names = "clkin1";
status = "okay";
};
/*
* The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
* lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
* an USB3.0 Type A connector and a M.2 Key M slot.
* The PHY driving these differential lines is shared between
* the USB3.0 controller and the PCIe Controller, thus only
* a single controller can use it.
* If the MCU is configured to mux the PCIe/USB3.0 differential lines
* to the M.2 Key M slot, uncomment the following block to disable
* USB3.0 from the USB Complex and enable the PCIe controller.
* The End User is not expected to uncomment the following except for
* testing purposes, but instead rely on the firmware/bootloader to
* update these nodes accordingly if PCIe mode is selected by the MCU.
*/
/*
&pcie {
status = "okay";
};
&usb {
phys = <&usb2_phy0>, <&usb2_phy1>;
phy-names = "usb2-phy0", "usb2-phy1";
};
*/

4
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
View File

@ -134,6 +134,10 @@
power-domains = <&pwrc PWRC_SM1_ETH_ID>;
};
&pcie {
power-domains = <&pwrc PWRC_SM1_PCIE_ID>;
};
&pwrc {
compatible = "amlogic,meson-sm1-pwrc";
};

134
drivers/pci/controller/dwc/pci-meson.c
View File

@ -16,6 +16,7 @@
#include <linux/reset.h>
#include <linux/resource.h>
#include <linux/types.h>
#include <linux/phy/phy.h>
#include "pcie-designware.h"
@ -96,12 +97,18 @@ struct meson_pcie_rc_reset {
struct reset_control *apb;
};
struct meson_pcie_param {
bool has_shared_phy;
};
struct meson_pcie {
struct dw_pcie pci;
struct meson_pcie_mem_res mem_res;
struct meson_pcie_clk_res clk_res;
struct meson_pcie_rc_reset mrst;
struct gpio_desc *reset_gpio;
struct phy *phy;
const struct meson_pcie_param *param;
};
static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
@ -123,10 +130,12 @@ static int meson_pcie_get_resets(struct meson_pcie *mp)
{
struct meson_pcie_rc_reset *mrst = &mp->mrst;
mrst->phy = meson_pcie_get_reset(mp, "phy", PCIE_SHARED_RESET);
if (IS_ERR(mrst->phy))
return PTR_ERR(mrst->phy);
reset_control_deassert(mrst->phy);
if (!mp->param->has_shared_phy) {
mrst->phy = meson_pcie_get_reset(mp, "phy", PCIE_SHARED_RESET);
if (IS_ERR(mrst->phy))
return PTR_ERR(mrst->phy);
reset_control_deassert(mrst->phy);
}
mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
if (IS_ERR(mrst->port))
@ -180,27 +189,52 @@ static int meson_pcie_get_mems(struct platform_device *pdev,
if (IS_ERR(mp->mem_res.cfg_base))
return PTR_ERR(mp->mem_res.cfg_base);
/* Meson SoC has two PCI controllers use same phy register*/
mp->mem_res.phy_base = meson_pcie_get_mem_shared(pdev, mp, "phy");
if (IS_ERR(mp->mem_res.phy_base))
return PTR_ERR(mp->mem_res.phy_base);
/* Meson AXG SoC has two PCI controllers use same phy register */
if (!mp->param->has_shared_phy) {
mp->mem_res.phy_base =
meson_pcie_get_mem_shared(pdev, mp, "phy");
if (IS_ERR(mp->mem_res.phy_base))
return PTR_ERR(mp->mem_res.phy_base);
}
return 0;
}
static void meson_pcie_power_on(struct meson_pcie *mp)
static int meson_pcie_power_on(struct meson_pcie *mp)
{
writel(MESON_PCIE_PHY_POWERUP, mp->mem_res.phy_base);
int ret = 0;
if (mp->param->has_shared_phy) {
ret = phy_init(mp->phy);
if (ret)
return ret;
ret = phy_power_on(mp->phy);
if (ret) {
phy_exit(mp->phy);
return ret;
}
} else
writel(MESON_PCIE_PHY_POWERUP, mp->mem_res.phy_base);
return 0;
}
static void meson_pcie_reset(struct meson_pcie *mp)
static int meson_pcie_reset(struct meson_pcie *mp)
{
struct meson_pcie_rc_reset *mrst = &mp->mrst;
int ret = 0;
reset_control_assert(mrst->phy);
udelay(PCIE_RESET_DELAY);
reset_control_deassert(mrst->phy);
udelay(PCIE_RESET_DELAY);
if (mp->param->has_shared_phy) {
ret = phy_reset(mp->phy);
if (ret)
return ret;
} else {
reset_control_assert(mrst->phy);
udelay(PCIE_RESET_DELAY);
reset_control_deassert(mrst->phy);
udelay(PCIE_RESET_DELAY);
}
reset_control_assert(mrst->port);
reset_control_assert(mrst->apb);
@ -208,6 +242,8 @@ static void meson_pcie_reset(struct meson_pcie *mp)
reset_control_deassert(mrst->port);
reset_control_deassert(mrst->apb);
udelay(PCIE_RESET_DELAY);
return 0;
}
static inline struct clk *meson_pcie_probe_clock(struct device *dev,
@ -250,15 +286,17 @@ static int meson_pcie_probe_clocks(struct meson_pcie *mp)
if (IS_ERR(res->port_clk))
return PTR_ERR(res->port_clk);
res->mipi_gate = meson_pcie_probe_clock(dev, "pcie_mipi_en", 0);
if (IS_ERR(res->mipi_gate))
return PTR_ERR(res->mipi_gate);
if (!mp->param->has_shared_phy) {
res->mipi_gate = meson_pcie_probe_clock(dev, "mipi", 0);
if (IS_ERR(res->mipi_gate))
return PTR_ERR(res->mipi_gate);
}
res->general_clk = meson_pcie_probe_clock(dev, "pcie_general", 0);
res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
if (IS_ERR(res->general_clk))
return PTR_ERR(res->general_clk);
res->clk = meson_pcie_probe_clock(dev, "pcie", 0);
res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
if (IS_ERR(res->clk))
return PTR_ERR(res->clk);
@ -287,9 +325,9 @@ static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
static void meson_pcie_assert_reset(struct meson_pcie *mp)
{
gpiod_set_value_cansleep(mp->reset_gpio, 0);
udelay(500);
gpiod_set_value_cansleep(mp->reset_gpio, 1);
udelay(500);
gpiod_set_value_cansleep(mp->reset_gpio, 0);
}
static void meson_pcie_init_dw(struct meson_pcie *mp)
@ -524,6 +562,7 @@ static const struct dw_pcie_ops dw_pcie_ops = {
static int meson_pcie_probe(struct platform_device *pdev)
{
const struct meson_pcie_param *match_data;
struct device *dev = &pdev->dev;
struct dw_pcie *pci;
struct meson_pcie *mp;
@ -537,6 +576,19 @@ static int meson_pcie_probe(struct platform_device *pdev)
pci->dev = dev;
pci->ops = &dw_pcie_ops;
match_data = of_device_get_match_data(dev);
if (!match_data) {
dev_err(dev, "failed to get match data\n");
return -ENODEV;
}
mp->param = match_data;
if (mp->param->has_shared_phy) {
mp->phy = devm_phy_get(dev, "pcie");
if (IS_ERR(mp->phy))
return PTR_ERR(mp->phy);
}
mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(mp->reset_gpio)) {
dev_err(dev, "get reset gpio failed\n");
@ -555,13 +607,22 @@ static int meson_pcie_probe(struct platform_device *pdev)
return ret;
}
meson_pcie_power_on(mp);
meson_pcie_reset(mp);
ret = meson_pcie_power_on(mp);
if (ret) {
dev_err(dev, "phy power on failed, %d\n", ret);
return ret;
}
ret = meson_pcie_reset(mp);
if (ret) {
dev_err(dev, "reset failed, %d\n", ret);
goto err_phy;
}
ret = meson_pcie_probe_clocks(mp);
if (ret) {
dev_err(dev, "init clock resources failed, %d\n", ret);
return ret;
goto err_phy;
}
platform_set_drvdata(pdev, mp);
@ -569,15 +630,36 @@ static int meson_pcie_probe(struct platform_device *pdev)
ret = meson_add_pcie_port(mp, pdev);
if (ret < 0) {
dev_err(dev, "Add PCIe port failed, %d\n", ret);
return ret;
goto err_phy;
}
return 0;
err_phy:
if (mp->param->has_shared_phy) {
phy_power_off(mp->phy);
phy_exit(mp->phy);
}
return ret;
}
static struct meson_pcie_param meson_pcie_axg_param = {
.has_shared_phy = false,
};
static struct meson_pcie_param meson_pcie_g12a_param = {
.has_shared_phy = true,
};
static const struct of_device_id meson_pcie_of_match[] = {
{
.compatible = "amlogic,axg-pcie",
.data = &meson_pcie_axg_param,
},
{
.compatible = "amlogic,g12a-pcie",
.data = &meson_pcie_g12a_param,
},
{},
};

70
drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
View File

@ -50,6 +50,8 @@
#define PHY_R5_PHY_CR_ACK BIT(16)
#define PHY_R5_PHY_BS_OUT BIT(17)
#define PCIE_RESET_DELAY 500
struct phy_g12a_usb3_pcie_priv {
struct regmap *regmap;
struct regmap *regmap_cr;
@ -196,6 +198,10 @@ static int phy_g12a_usb3_init(struct phy *phy)
struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
int data, ret;
ret = reset_control_reset(priv->reset);
if (ret)
return ret;
/* Switch PHY to USB3 */
/* TODO figure out how to handle when PCIe was set in the bootloader */
regmap_update_bits(priv->regmap, PHY_R0,
@ -272,24 +278,64 @@ static int phy_g12a_usb3_init(struct phy *phy)
return 0;
}
static int phy_g12a_usb3_pcie_init(struct phy *phy)
static int phy_g12a_usb3_pcie_power_on(struct phy *phy)
{
struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
if (priv->mode == PHY_TYPE_USB3)
return 0;
regmap_update_bits(priv->regmap, PHY_R0,
PHY_R0_PCIE_POWER_STATE,
FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
return 0;
}
static int phy_g12a_usb3_pcie_power_off(struct phy *phy)
{
struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
if (priv->mode == PHY_TYPE_USB3)
return 0;
regmap_update_bits(priv->regmap, PHY_R0,
PHY_R0_PCIE_POWER_STATE,
FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d));
return 0;
}
static int phy_g12a_usb3_pcie_reset(struct phy *phy)
{
struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
int ret;
ret = reset_control_reset(priv->reset);
if (priv->mode == PHY_TYPE_USB3)
return 0;
ret = reset_control_assert(priv->reset);
if (ret)
return ret;
udelay(PCIE_RESET_DELAY);
ret = reset_control_deassert(priv->reset);
if (ret)
return ret;
udelay(PCIE_RESET_DELAY);
return 0;
}
static int phy_g12a_usb3_pcie_init(struct phy *phy)
{
struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
if (priv->mode == PHY_TYPE_USB3)
return phy_g12a_usb3_init(phy);
/* Power UP PCIE */
/* TODO figure out when the bootloader has set USB3 mode before */
regmap_update_bits(priv->regmap, PHY_R0,
PHY_R0_PCIE_POWER_STATE,
FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
return 0;
}
@ -297,7 +343,10 @@ static int phy_g12a_usb3_pcie_exit(struct phy *phy)
{
struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
return reset_control_reset(priv->reset);
if (priv->mode == PHY_TYPE_USB3)
return reset_control_reset(priv->reset);
return 0;
}
static struct phy *phy_g12a_usb3_pcie_xlate(struct device *dev,
@ -326,6 +375,9 @@ static struct phy *phy_g12a_usb3_pcie_xlate(struct device *dev,
static const struct phy_ops phy_g12a_usb3_pcie_ops = {
.init = phy_g12a_usb3_pcie_init,
.exit = phy_g12a_usb3_pcie_exit,
.power_on = phy_g12a_usb3_pcie_power_on,
.power_off = phy_g12a_usb3_pcie_power_off,
.reset = phy_g12a_usb3_pcie_reset,
.owner = THIS_MODULE,
};