pinctrl: sh-pfc: r8a7795: Add EtherAVB pins, groups and function
Add pins, groups, and a function for EtherAVB on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -1576,6 +1576,93 @@ static const struct sh_pfc_pin pinmux_pins[] = {
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
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};
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/* - EtherAVB --------------------------------------------------------------- */
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static const unsigned int avb_link_pins[] = {
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/* AVB_LINK */
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RCAR_GP_PIN(2, 12),
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};
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static const unsigned int avb_link_mux[] = {
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AVB_LINK_MARK,
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};
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static const unsigned int avb_magic_pins[] = {
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/* AVB_MAGIC_ */
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RCAR_GP_PIN(2, 10),
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};
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static const unsigned int avb_magic_mux[] = {
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AVB_MAGIC_MARK,
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};
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static const unsigned int avb_phy_int_pins[] = {
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/* AVB_PHY_INT */
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RCAR_GP_PIN(2, 11),
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};
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static const unsigned int avb_phy_int_mux[] = {
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AVB_PHY_INT_MARK,
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};
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static const unsigned int avb_mdc_pins[] = {
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/* AVB_MDC, AVB_MDIO */
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RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
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};
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static const unsigned int avb_mdc_mux[] = {
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AVB_MDC_MARK, AVB_MDIO_MARK,
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};
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static const unsigned int avb_mii_pins[] = {
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/*
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* AVB_TX_CTL, AVB_TXC, AVB_TD0,
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* AVB_TD1, AVB_TD2, AVB_TD3,
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* AVB_RX_CTL, AVB_RXC, AVB_RD0,
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* AVB_RD1, AVB_RD2, AVB_RD3,
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* AVB_TXCREFCLK
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*/
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PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
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PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
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PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
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PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
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PIN_NUMBER('A', 12),
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};
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static const unsigned int avb_mii_mux[] = {
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AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
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AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
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AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
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AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
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AVB_TXCREFCLK_MARK,
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};
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static const unsigned int avb_avtp_pps_pins[] = {
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/* AVB_AVTP_PPS */
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RCAR_GP_PIN(2, 6),
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};
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static const unsigned int avb_avtp_pps_mux[] = {
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AVB_AVTP_PPS_MARK,
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};
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static const unsigned int avb_avtp_match_a_pins[] = {
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/* AVB_AVTP_MATCH_A */
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RCAR_GP_PIN(2, 13),
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};
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static const unsigned int avb_avtp_match_a_mux[] = {
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AVB_AVTP_MATCH_A_MARK,
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};
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static const unsigned int avb_avtp_capture_a_pins[] = {
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/* AVB_AVTP_CAPTURE_A */
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RCAR_GP_PIN(2, 14),
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};
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static const unsigned int avb_avtp_capture_a_mux[] = {
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AVB_AVTP_CAPTURE_A_MARK,
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};
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static const unsigned int avb_avtp_match_b_pins[] = {
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/* AVB_AVTP_MATCH_B */
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RCAR_GP_PIN(1, 8),
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};
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static const unsigned int avb_avtp_match_b_mux[] = {
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AVB_AVTP_MATCH_B_MARK,
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};
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static const unsigned int avb_avtp_capture_b_pins[] = {
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/* AVB_AVTP_CAPTURE_B */
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RCAR_GP_PIN(1, 11),
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};
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static const unsigned int avb_avtp_capture_b_mux[] = {
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AVB_AVTP_CAPTURE_B_MARK,
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};
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/* - SCIF0 ------------------------------------------------------------------ */
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static const unsigned int scif0_data_pins[] = {
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/* RX, TX */
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@ -1790,6 +1877,16 @@ static const unsigned int scif_clk_b_mux[] = {
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};
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static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(avb_link),
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SH_PFC_PIN_GROUP(avb_magic),
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SH_PFC_PIN_GROUP(avb_phy_int),
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SH_PFC_PIN_GROUP(avb_mdc),
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SH_PFC_PIN_GROUP(avb_mii),
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SH_PFC_PIN_GROUP(avb_avtp_pps),
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SH_PFC_PIN_GROUP(avb_avtp_match_a),
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SH_PFC_PIN_GROUP(avb_avtp_capture_a),
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SH_PFC_PIN_GROUP(avb_avtp_match_b),
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SH_PFC_PIN_GROUP(avb_avtp_capture_b),
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SH_PFC_PIN_GROUP(scif0_data),
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SH_PFC_PIN_GROUP(scif0_clk),
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SH_PFC_PIN_GROUP(scif0_ctrl),
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@ -1821,6 +1918,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(scif_clk_b),
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};
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static const char * const avb_groups[] = {
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"avb_link",
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"avb_magic",
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"avb_phy_int",
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"avb_mdc",
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"avb_mii",
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"avb_avtp_pps",
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"avb_avtp_match_a",
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"avb_avtp_capture_a",
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"avb_avtp_match_b",
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"avb_avtp_capture_b",
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};
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static const char * const scif0_groups[] = {
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"scif0_data",
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"scif0_clk",
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@ -1872,6 +1982,7 @@ static const char * const scif_clk_groups[] = {
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};
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static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(avb),
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SH_PFC_FUNCTION(scif0),
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SH_PFC_FUNCTION(scif1),
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SH_PFC_FUNCTION(scif2),
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