intel_idle: Relocate definitions of cpuidle callbacks
Move the definitions of intel_idle() and intel_idle_s2idle() before the definitions of cpuidle_state structures referring to them to avoid having to use additional declarations of them (and drop those declarations). No functional impact. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -83,10 +83,6 @@ struct idle_cpu {
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static const struct idle_cpu *icpu;
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static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
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static int intel_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index);
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static void intel_idle_s2idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index);
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static struct cpuidle_state *cpuidle_state_table;
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/*
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@ -112,6 +108,81 @@ static struct cpuidle_state *cpuidle_state_table;
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#define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
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#define MWAIT2flg(eax) ((eax & 0xFF) << 24)
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/**
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* intel_idle - Ask the processor to enter the given idle state.
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* @dev: cpuidle device of the target CPU.
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* @drv: cpuidle driver (assumed to point to intel_idle_driver).
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* @index: Target idle state index.
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*
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* Use the MWAIT instruction to notify the processor that the CPU represented by
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* @dev is idle and it can try to enter the idle state corresponding to @index.
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*
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* If the local APIC timer is not known to be reliable in the target idle state,
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* enable one-shot tick broadcasting for the target CPU before executing MWAIT.
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*
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* Optionally call leave_mm() for the target CPU upfront to avoid wakeups due to
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* flushing user TLBs.
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*
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* Must be called under local_irq_disable().
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*/
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static __cpuidle int intel_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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struct cpuidle_state *state = &drv->states[index];
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unsigned long eax = flg2MWAIT(state->flags);
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unsigned long ecx = 1; /* break on interrupt flag */
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bool uninitialized_var(tick);
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int cpu = smp_processor_id();
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/*
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* leave_mm() to avoid costly and often unnecessary wakeups
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* for flushing the user TLB's associated with the active mm.
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*/
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if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
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leave_mm(cpu);
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if (!static_cpu_has(X86_FEATURE_ARAT) && !lapic_timer_always_reliable) {
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/*
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* Switch over to one-shot tick broadcast if the target C-state
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* is deeper than C1.
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*/
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if ((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) {
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tick = true;
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tick_broadcast_enter();
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} else {
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tick = false;
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}
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}
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mwait_idle_with_hints(eax, ecx);
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if (!static_cpu_has(X86_FEATURE_ARAT) && tick)
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tick_broadcast_exit();
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return index;
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}
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/**
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* intel_idle_s2idle - Ask the processor to enter the given idle state.
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* @dev: cpuidle device of the target CPU.
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* @drv: cpuidle driver (assumed to point to intel_idle_driver).
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* @index: Target idle state index.
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*
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* Use the MWAIT instruction to notify the processor that the CPU represented by
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* @dev is idle and it can try to enter the idle state corresponding to @index.
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*
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* Invoked as a suspend-to-idle callback routine with frozen user space, frozen
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* scheduler tick and suspended scheduler clock on the target CPU.
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*/
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static __cpuidle void intel_idle_s2idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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unsigned long eax = flg2MWAIT(drv->states[index].flags);
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unsigned long ecx = 1; /* break on interrupt flag */
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mwait_idle_with_hints(eax, ecx);
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}
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/*
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* States are indexed by the cstate number,
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* which is also the index into the MWAIT hint array.
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@ -891,81 +962,6 @@ static struct cpuidle_state dnv_cstates[] = {
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.enter = NULL }
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};
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/**
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* intel_idle - Ask the processor to enter the given idle state.
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* @dev: cpuidle device of the target CPU.
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* @drv: cpuidle driver (assumed to point to intel_idle_driver).
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* @index: Target idle state index.
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*
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* Use the MWAIT instruction to notify the processor that the CPU represented by
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* @dev is idle and it can try to enter the idle state corresponding to @index.
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*
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* If the local APIC timer is not known to be reliable in the target idle state,
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* enable one-shot tick broadcasting for the target CPU before executing MWAIT.
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*
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* Optionally call leave_mm() for the target CPU upfront to avoid wakeups due to
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* flushing user TLBs.
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*
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* Must be called under local_irq_disable().
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*/
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static __cpuidle int intel_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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struct cpuidle_state *state = &drv->states[index];
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unsigned long eax = flg2MWAIT(state->flags);
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unsigned long ecx = 1; /* break on interrupt flag */
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bool uninitialized_var(tick);
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int cpu = smp_processor_id();
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/*
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* leave_mm() to avoid costly and often unnecessary wakeups
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* for flushing the user TLB's associated with the active mm.
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*/
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if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
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leave_mm(cpu);
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if (!static_cpu_has(X86_FEATURE_ARAT) && !lapic_timer_always_reliable) {
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/*
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* Switch over to one-shot tick broadcast if the target C-state
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* is deeper than C1.
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*/
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if ((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) {
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tick = true;
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tick_broadcast_enter();
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} else {
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tick = false;
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}
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}
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mwait_idle_with_hints(eax, ecx);
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if (!static_cpu_has(X86_FEATURE_ARAT) && tick)
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tick_broadcast_exit();
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return index;
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}
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/**
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* intel_idle_s2idle - Ask the processor to enter the given idle state.
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* @dev: cpuidle device of the target CPU.
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* @drv: cpuidle driver (assumed to point to intel_idle_driver).
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* @index: Target idle state index.
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*
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* Use the MWAIT instruction to notify the processor that the CPU represented by
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* @dev is idle and it can try to enter the idle state corresponding to @index.
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*
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* Invoked as a suspend-to-idle callback routine with frozen user space, frozen
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* scheduler tick and suspended scheduler clock on the target CPU.
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*/
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static __cpuidle void intel_idle_s2idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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unsigned long eax = flg2MWAIT(drv->states[index].flags);
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unsigned long ecx = 1; /* break on interrupt flag */
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mwait_idle_with_hints(eax, ecx);
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}
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static const struct idle_cpu idle_cpu_nehalem = {
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.state_table = nehalem_cstates,
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.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
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