Blackfin: add a GPIO_DEFAULT_BOOT_SPI_CS
This is parallel to the existing P_DEFAULT_BOOT_SPI_CS, but in terms of the GPIO value so it can be used with the normal gpio API. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -109,6 +109,7 @@
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#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
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#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
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#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
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#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
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#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
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/* SPORT Port Mux */
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/* SPORT Port Mux */
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@ -79,6 +79,7 @@
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#define P_HWAIT (P_DONTCARE)
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#define P_HWAIT (P_DONTCARE)
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#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
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#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
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#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
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@ -60,6 +60,7 @@
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#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
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#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
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#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
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#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
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#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
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#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
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#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
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#define P_TMR2 (P_DONTCARE)
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#define P_TMR2 (P_DONTCARE)
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@ -37,6 +37,7 @@
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#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
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#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
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#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
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#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
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#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
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#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
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#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
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#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
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#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
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@ -108,6 +108,7 @@
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#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
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#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
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#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
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#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
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#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
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#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
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#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
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#endif /* _MACH_PORTMUX_H_ */
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#endif /* _MACH_PORTMUX_H_ */
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@ -131,6 +131,7 @@
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#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
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#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
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#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
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#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
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#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
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#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
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#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
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#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
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#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
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@ -91,6 +91,7 @@
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#define P_SPI0_MOSI (P_DONTCARE)
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#define P_SPI0_MOSI (P_DONTCARE)
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#define P_SPI0_MISO (P_DONTCARE)
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#define P_SPI0_MISO (P_DONTCARE)
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#define P_SPI0_SCK (P_DONTCARE)
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#define P_SPI0_SCK (P_DONTCARE)
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#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
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#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
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#endif /* _MACH_PORTMUX_H_ */
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#endif /* _MACH_PORTMUX_H_ */
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