dmaengine: Add Synopsys eDMA IP version 0 debugfs support
Add Synopsys eDMA IP version 0 debugfs support to assist any debug in the future. Creates a file system structure composed by folders and files that mimic the IP register map (this files are read only) to ease any debug. To enable this feature is necessary to select DEBUG_FS option on kernel configuration. Small output example: (eDMA IP version 0, unroll, 1 write + 1 read channels) % mount -t debugfs none /sys/kernel/debug/ % tree /sys/kernel/debug/dw-edma-core:0/ dw-edma/ ├── version ├── mode ├── wr_ch_cnt ├── rd_ch_cnt └── registers ├── ctrl_data_arb_prior ├── ctrl ├── write │ ├── engine_en │ ├── doorbell │ ├── ch_arb_weight_low │ ├── ch_arb_weight_high │ ├── int_status │ ├── int_mask │ ├── int_clear │ ├── err_status │ ├── done_imwr_low │ ├── done_imwr_high │ ├── abort_imwr_low │ ├── abort_imwr_high │ ├── ch01_imwr_data │ ├── ch23_imwr_data │ ├── ch45_imwr_data │ ├── ch67_imwr_data │ ├── linked_list_err_en │ ├── engine_chgroup │ ├── engine_hshake_cnt_low │ ├── engine_hshake_cnt_high │ ├── ch0_pwr_en │ ├── ch1_pwr_en │ ├── ch2_pwr_en │ ├── ch3_pwr_en │ ├── ch4_pwr_en │ ├── ch5_pwr_en │ ├── ch6_pwr_en │ ├── ch7_pwr_en │ └── channel:0 │ ├── ch_control1 │ ├── ch_control2 │ ├── transfer_size │ ├── sar_low │ ├── sar_high │ ├── dar_high │ ├── llp_low │ └── llp_high └── read ├── engine_en ├── doorbell ├── ch_arb_weight_low ├── ch_arb_weight_high ├── int_status ├── int_mask ├── int_clear ├── err_status_low ├── err_status_high ├── done_imwr_low ├── done_imwr_high ├── abort_imwr_low ├── abort_imwr_high ├── ch01_imwr_data ├── ch23_imwr_data ├── ch45_imwr_data ├── ch67_imwr_data ├── linked_list_err_en ├── engine_chgroup ├── engine_hshake_cnt_low ├── engine_hshake_cnt_high ├── ch0_pwr_en ├── ch1_pwr_en ├── ch2_pwr_en ├── ch3_pwr_en ├── ch4_pwr_en ├── ch5_pwr_en ├── ch6_pwr_en ├── ch7_pwr_en └── channel:0 ├── ch_control1 ├── ch_control2 ├── transfer_size ├── sar_low ├── sar_high ├── dar_high ├── llp_low └── llp_high Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Gustavo Pimentel
Vinod Koul
parent
7e4b8a4fbe
commit
305aebeff8
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@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_DW_EDMA) += dw-edma.o
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dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o
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dw-edma-objs := dw-edma-core.o \
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dw-edma-v0-core.o
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dw-edma-v0-core.o $(dw-edma-y)
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@ -345,8 +345,10 @@ int dw_edma_v0_core_device_config(struct dw_edma_chan *chan)
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/* eDMA debugfs callbacks */
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void dw_edma_v0_core_debugfs_on(struct dw_edma_chip *chip)
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{
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dw_edma_v0_debugfs_on(chip);
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}
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void dw_edma_v0_core_debugfs_off(void)
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{
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dw_edma_v0_debugfs_off();
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}
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@ -0,0 +1,310 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare eDMA v0 core
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*
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* Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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*/
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#include <linux/debugfs.h>
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#include <linux/bitfield.h>
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#include "dw-edma-v0-debugfs.h"
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#include "dw-edma-v0-regs.h"
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#include "dw-edma-core.h"
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#define REGS_ADDR(name) \
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((dma_addr_t *)®s->name)
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#define REGISTER(name) \
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{ #name, REGS_ADDR(name) }
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#define WR_REGISTER(name) \
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{ #name, REGS_ADDR(wr_##name) }
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#define RD_REGISTER(name) \
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{ #name, REGS_ADDR(rd_##name) }
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#define WR_REGISTER_LEGACY(name) \
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{ #name, REGS_ADDR(type.legacy.wr_##name) }
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#define RD_REGISTER_LEGACY(name) \
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{ #name, REGS_ADDR(type.legacy.rd_##name) }
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#define WR_REGISTER_UNROLL(name) \
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{ #name, REGS_ADDR(type.unroll.wr_##name) }
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#define RD_REGISTER_UNROLL(name) \
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{ #name, REGS_ADDR(type.unroll.rd_##name) }
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#define WRITE_STR "write"
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#define READ_STR "read"
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#define CHANNEL_STR "channel"
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#define REGISTERS_STR "registers"
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static struct dentry *base_dir;
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static struct dw_edma *dw;
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static struct dw_edma_v0_regs *regs;
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static struct {
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void *start;
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void *end;
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} lim[2][EDMA_V0_MAX_NR_CH];
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struct debugfs_entries {
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char name[24];
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dma_addr_t *reg;
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};
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static int dw_edma_debugfs_u32_get(void *data, u64 *val)
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{
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if (dw->mode == EDMA_MODE_LEGACY &&
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data >= (void *)®s->type.legacy.ch) {
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void *ptr = (void *)®s->type.legacy.ch;
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u32 viewport_sel = 0;
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unsigned long flags;
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u16 ch;
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for (ch = 0; ch < dw->wr_ch_cnt; ch++)
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if (lim[0][ch].start >= data && data < lim[0][ch].end) {
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ptr += (data - lim[0][ch].start);
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goto legacy_sel_wr;
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}
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for (ch = 0; ch < dw->rd_ch_cnt; ch++)
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if (lim[1][ch].start >= data && data < lim[1][ch].end) {
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ptr += (data - lim[1][ch].start);
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goto legacy_sel_rd;
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}
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return 0;
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legacy_sel_rd:
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viewport_sel = BIT(31);
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legacy_sel_wr:
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viewport_sel |= FIELD_PREP(EDMA_V0_VIEWPORT_MASK, ch);
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raw_spin_lock_irqsave(&dw->lock, flags);
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writel(viewport_sel, ®s->type.legacy.viewport_sel);
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*val = readl(ptr);
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raw_spin_unlock_irqrestore(&dw->lock, flags);
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} else {
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*val = readl(data);
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}
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_edma_debugfs_u32_get, NULL, "0x%08llx\n");
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static void dw_edma_debugfs_create_x32(const struct debugfs_entries entries[],
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int nr_entries, struct dentry *dir)
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{
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int i;
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for (i = 0; i < nr_entries; i++) {
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if (!debugfs_create_file_unsafe(entries[i].name, 0444, dir,
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entries[i].reg, &fops_x32))
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break;
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}
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}
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static void dw_edma_debugfs_regs_ch(struct dw_edma_v0_ch_regs *regs,
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struct dentry *dir)
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{
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int nr_entries;
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const struct debugfs_entries debugfs_regs[] = {
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REGISTER(ch_control1),
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REGISTER(ch_control2),
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REGISTER(transfer_size),
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REGISTER(sar_low),
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REGISTER(sar_high),
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REGISTER(dar_low),
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REGISTER(dar_high),
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REGISTER(llp_low),
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REGISTER(llp_high),
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};
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nr_entries = ARRAY_SIZE(debugfs_regs);
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dw_edma_debugfs_create_x32(debugfs_regs, nr_entries, dir);
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}
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static void dw_edma_debugfs_regs_wr(struct dentry *dir)
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{
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const struct debugfs_entries debugfs_regs[] = {
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/* eDMA global registers */
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WR_REGISTER(engine_en),
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WR_REGISTER(doorbell),
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WR_REGISTER(ch_arb_weight_low),
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WR_REGISTER(ch_arb_weight_high),
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/* eDMA interrupts registers */
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WR_REGISTER(int_status),
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WR_REGISTER(int_mask),
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WR_REGISTER(int_clear),
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WR_REGISTER(err_status),
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WR_REGISTER(done_imwr_low),
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WR_REGISTER(done_imwr_high),
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WR_REGISTER(abort_imwr_low),
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WR_REGISTER(abort_imwr_high),
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WR_REGISTER(ch01_imwr_data),
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WR_REGISTER(ch23_imwr_data),
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WR_REGISTER(ch45_imwr_data),
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WR_REGISTER(ch67_imwr_data),
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WR_REGISTER(linked_list_err_en),
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};
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const struct debugfs_entries debugfs_unroll_regs[] = {
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/* eDMA channel context grouping */
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WR_REGISTER_UNROLL(engine_chgroup),
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WR_REGISTER_UNROLL(engine_hshake_cnt_low),
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WR_REGISTER_UNROLL(engine_hshake_cnt_high),
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WR_REGISTER_UNROLL(ch0_pwr_en),
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WR_REGISTER_UNROLL(ch1_pwr_en),
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WR_REGISTER_UNROLL(ch2_pwr_en),
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WR_REGISTER_UNROLL(ch3_pwr_en),
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WR_REGISTER_UNROLL(ch4_pwr_en),
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WR_REGISTER_UNROLL(ch5_pwr_en),
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WR_REGISTER_UNROLL(ch6_pwr_en),
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WR_REGISTER_UNROLL(ch7_pwr_en),
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};
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struct dentry *regs_dir, *ch_dir;
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int nr_entries, i;
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char name[16];
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regs_dir = debugfs_create_dir(WRITE_STR, dir);
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if (!regs_dir)
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return;
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nr_entries = ARRAY_SIZE(debugfs_regs);
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dw_edma_debugfs_create_x32(debugfs_regs, nr_entries, regs_dir);
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if (dw->mode == EDMA_MODE_UNROLL) {
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nr_entries = ARRAY_SIZE(debugfs_unroll_regs);
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dw_edma_debugfs_create_x32(debugfs_unroll_regs, nr_entries,
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regs_dir);
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}
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for (i = 0; i < dw->wr_ch_cnt; i++) {
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snprintf(name, sizeof(name), "%s:%d", CHANNEL_STR, i);
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ch_dir = debugfs_create_dir(name, regs_dir);
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if (!ch_dir)
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return;
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dw_edma_debugfs_regs_ch(®s->type.unroll.ch[i].wr, ch_dir);
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lim[0][i].start = ®s->type.unroll.ch[i].wr;
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lim[0][i].end = ®s->type.unroll.ch[i].padding_1[0];
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}
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}
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static void dw_edma_debugfs_regs_rd(struct dentry *dir)
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{
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const struct debugfs_entries debugfs_regs[] = {
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/* eDMA global registers */
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RD_REGISTER(engine_en),
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RD_REGISTER(doorbell),
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RD_REGISTER(ch_arb_weight_low),
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RD_REGISTER(ch_arb_weight_high),
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/* eDMA interrupts registers */
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RD_REGISTER(int_status),
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RD_REGISTER(int_mask),
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RD_REGISTER(int_clear),
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RD_REGISTER(err_status_low),
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RD_REGISTER(err_status_high),
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RD_REGISTER(linked_list_err_en),
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RD_REGISTER(done_imwr_low),
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RD_REGISTER(done_imwr_high),
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RD_REGISTER(abort_imwr_low),
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RD_REGISTER(abort_imwr_high),
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RD_REGISTER(ch01_imwr_data),
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RD_REGISTER(ch23_imwr_data),
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RD_REGISTER(ch45_imwr_data),
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RD_REGISTER(ch67_imwr_data),
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};
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const struct debugfs_entries debugfs_unroll_regs[] = {
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/* eDMA channel context grouping */
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RD_REGISTER_UNROLL(engine_chgroup),
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RD_REGISTER_UNROLL(engine_hshake_cnt_low),
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RD_REGISTER_UNROLL(engine_hshake_cnt_high),
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RD_REGISTER_UNROLL(ch0_pwr_en),
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RD_REGISTER_UNROLL(ch1_pwr_en),
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RD_REGISTER_UNROLL(ch2_pwr_en),
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RD_REGISTER_UNROLL(ch3_pwr_en),
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RD_REGISTER_UNROLL(ch4_pwr_en),
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RD_REGISTER_UNROLL(ch5_pwr_en),
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RD_REGISTER_UNROLL(ch6_pwr_en),
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RD_REGISTER_UNROLL(ch7_pwr_en),
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};
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struct dentry *regs_dir, *ch_dir;
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int nr_entries, i;
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char name[16];
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regs_dir = debugfs_create_dir(READ_STR, dir);
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if (!regs_dir)
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return;
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nr_entries = ARRAY_SIZE(debugfs_regs);
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dw_edma_debugfs_create_x32(debugfs_regs, nr_entries, regs_dir);
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if (dw->mode == EDMA_MODE_UNROLL) {
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nr_entries = ARRAY_SIZE(debugfs_unroll_regs);
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dw_edma_debugfs_create_x32(debugfs_unroll_regs, nr_entries,
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regs_dir);
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}
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for (i = 0; i < dw->rd_ch_cnt; i++) {
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snprintf(name, sizeof(name), "%s:%d", CHANNEL_STR, i);
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ch_dir = debugfs_create_dir(name, regs_dir);
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if (!ch_dir)
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return;
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dw_edma_debugfs_regs_ch(®s->type.unroll.ch[i].rd, ch_dir);
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lim[1][i].start = ®s->type.unroll.ch[i].rd;
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lim[1][i].end = ®s->type.unroll.ch[i].padding_2[0];
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}
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}
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static void dw_edma_debugfs_regs(void)
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{
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const struct debugfs_entries debugfs_regs[] = {
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REGISTER(ctrl_data_arb_prior),
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REGISTER(ctrl),
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};
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struct dentry *regs_dir;
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int nr_entries;
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regs_dir = debugfs_create_dir(REGISTERS_STR, base_dir);
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if (!regs_dir)
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return;
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nr_entries = ARRAY_SIZE(debugfs_regs);
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dw_edma_debugfs_create_x32(debugfs_regs, nr_entries, regs_dir);
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dw_edma_debugfs_regs_wr(regs_dir);
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dw_edma_debugfs_regs_rd(regs_dir);
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}
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void dw_edma_v0_debugfs_on(struct dw_edma_chip *chip)
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{
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dw = chip->dw;
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if (!dw)
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return;
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regs = (struct dw_edma_v0_regs *)dw->rg_region.vaddr;
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if (!regs)
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return;
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base_dir = debugfs_create_dir(dw->name, 0);
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if (!base_dir)
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return;
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debugfs_create_u32("version", 0444, base_dir, &dw->version);
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debugfs_create_u32("mode", 0444, base_dir, &dw->mode);
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debugfs_create_u16("wr_ch_cnt", 0444, base_dir, &dw->wr_ch_cnt);
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debugfs_create_u16("rd_ch_cnt", 0444, base_dir, &dw->rd_ch_cnt);
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dw_edma_debugfs_regs();
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}
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void dw_edma_v0_debugfs_off(void)
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{
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debugfs_remove_recursive(base_dir);
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}
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@ -0,0 +1,27 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare eDMA v0 core
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*
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* Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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*/
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#ifndef _DW_EDMA_V0_DEBUG_FS_H
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#define _DW_EDMA_V0_DEBUG_FS_H
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#include <linux/dma/edma.h>
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#ifdef CONFIG_DEBUG_FS
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void dw_edma_v0_debugfs_on(struct dw_edma_chip *chip);
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void dw_edma_v0_debugfs_off(void);
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#else
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static inline void dw_edma_v0_debugfs_on(struct dw_edma_chip *chip)
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{
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}
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static inline void dw_edma_v0_debugfs_off(void)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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#endif /* _DW_EDMA_V0_DEBUG_FS_H */
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