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drm/nva3/clk: Pause the GPU before reclocking 

V2: always call post correctly even if pre fails
V3: move function prototype to nva3.h

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
This commit is contained in:
Roy Spliet 2014-08-29 12:27:42 +02:00 committed by Ben Skeggs
parent b485a7005f
commit 2fe7eaa0d4
3 changed files with 66 additions and 26 deletions
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52
drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
View File

@ -23,6 +23,7 @@
* Roy Spliet * Roy Spliet
*/ */
#include <engine/fifo.h>
#include <subdev/bios.h> #include <subdev/bios.h>
#include <subdev/bios/pll.h> #include <subdev/bios/pll.h>
#include <subdev/timer.h> #include <subdev/timer.h>
@ -293,6 +294,41 @@ calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate)
return ret; return ret;
} }
int
nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags)
{
struct nouveau_fifo *pfifo = nouveau_fifo(clk);
/* halt and idle execution engines */
nv_mask(clk, 0x020060, 0x00070000, 0x00000000);
nv_mask(clk, 0x002504, 0x00000001, 0x00000001);
/* Wait until the interrupt handler is finished */
if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000))
return -EBUSY;
if (pfifo)
pfifo->pause(pfifo, flags);
if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010))
return -EIO;
if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f))
return -EIO;
return 0;
}
void
nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags)
{
struct nouveau_fifo *pfifo = nouveau_fifo(clk);
if (pfifo && flags)
pfifo->start(pfifo, flags);
nv_mask(clk, 0x002504, 0x00000001, 0x00000000);
nv_mask(clk, 0x020060, 0x00070000, 0x00040000);
}
static void static void
disable_clk_src(struct nva3_clock_priv *priv, u32 src) disable_clk_src(struct nva3_clock_priv *priv, u32 src)
{ {
@ -421,6 +457,13 @@ nva3_clock_prog(struct nouveau_clock *clk)
{ {
struct nva3_clock_priv *priv = (void *)clk; struct nva3_clock_priv *priv = (void *)clk;
struct nva3_clock_info *core = &priv->eng[nv_clk_src_core]; struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
int ret = 0;
unsigned long flags;
unsigned long *f = &flags;
ret = nva3_clock_pre(clk, f);
if (ret)
goto out;
if (core->pll) if (core->pll)
prog_core(priv, nv_clk_src_core_intm); prog_core(priv, nv_clk_src_core_intm);
@ -430,7 +473,14 @@ nva3_clock_prog(struct nouveau_clock *clk)
prog_clk(priv, 0x20, nv_clk_src_disp); prog_clk(priv, 0x20, nv_clk_src_disp);
prog_clk(priv, 0x21, nv_clk_src_vdec); prog_clk(priv, 0x21, nv_clk_src_vdec);
prog_host(priv); prog_host(priv);
return 0;
out:
if (ret == -EBUSY)
f = NULL;
nva3_clock_post(clk, f);
return ret;
} }
static void static void

3
drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h
View File

@ -15,5 +15,6 @@ struct nva3_clock_info {
int nva3_pll_info(struct nouveau_clock *, int, u32, u32, int nva3_pll_info(struct nouveau_clock *, int, u32, u32,
struct nva3_clock_info *); struct nva3_clock_info *);
int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags);
void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags);
#endif #endif

37
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c
View File

@ -28,6 +28,7 @@
#include <subdev/timer.h> #include <subdev/timer.h>
#include <subdev/clock.h> #include <subdev/clock.h>
#include "nva3.h"
#include "pll.h" #include "pll.h"
struct nvaa_clock_priv { struct nvaa_clock_priv {
@ -299,25 +300,14 @@ static int
nvaa_clock_prog(struct nouveau_clock *clk) nvaa_clock_prog(struct nouveau_clock *clk)
{ {
struct nvaa_clock_priv *priv = (void *)clk; struct nvaa_clock_priv *priv = (void *)clk;
struct nouveau_fifo *pfifo = nouveau_fifo(clk); u32 pllmask = 0, mast;
unsigned long flags; unsigned long flags;
u32 pllmask = 0, mast, ptherm_gate; unsigned long *f = &flags;
int ret = -EBUSY; int ret = 0;
/* halt and idle execution engines */ ret = nva3_clock_pre(clk, f);
ptherm_gate = nv_mask(clk, 0x020060, 0x00070000, 0x00000000); if (ret)
nv_mask(clk, 0x002504, 0x00000001, 0x00000001); goto out;
/* Wait until the interrupt handler is finished */
if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000))
goto resume;
if (pfifo)
pfifo->pause(pfifo, &flags);
if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010))
goto resume;
if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f))
goto resume;
/* First switch to safe clocks: href */ /* First switch to safe clocks: href */
mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640); mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640);
@ -375,15 +365,8 @@ nvaa_clock_prog(struct nouveau_clock *clk)
} }
nv_wr32(clk, 0xc054, mast); nv_wr32(clk, 0xc054, mast);
ret = 0;
resume: resume:
if (pfifo)
pfifo->start(pfifo, &flags);
nv_mask(clk, 0x002504, 0x00000001, 0x00000000);
nv_wr32(clk, 0x020060, ptherm_gate);
/* Disable some PLLs and dividers when unused */ /* Disable some PLLs and dividers when unused */
if (priv->csrc != nv_clk_src_core) { if (priv->csrc != nv_clk_src_core) {
nv_wr32(clk, 0x4040, 0x00000000); nv_wr32(clk, 0x4040, 0x00000000);
@ -395,6 +378,12 @@ resume:
nv_mask(clk, 0x4020, 0x80000000, 0x00000000); nv_mask(clk, 0x4020, 0x80000000, 0x00000000);
} }
out:
if (ret == -EBUSY)
f = NULL;
nva3_clock_post(clk, f);
return ret; return ret;
} }