More .set push/pop encapsulation, more eyefriendly code formatting.
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thiemo Seufer
Ralf Baechle
parent
f8670e66dc
commit
2fe25f67a5
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@ -21,7 +21,7 @@
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*
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* - The MIPS32 and MIPS64 specs permit an implementation to directly derive
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* the index bits from the virtual address. This breaks with tradition
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* set by the R4000. To keep unpleassant surprises from happening we pick
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* set by the R4000. To keep unpleasant surprises from happening we pick
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* an address in KSEG0 / CKSEG0.
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* - We need a properly sign extended address for 64-bit code. To get away
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* without ifdefs we let the compiler do it by a type cast.
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@ -30,11 +30,11 @@
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3\n\t \n" \
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" cache %0, %1 \n" \
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" .set mips0 \n" \
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" .set reorder" \
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" .set pop \n" \
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: \
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: "i" (op), "m" (*(unsigned char *)(addr)))
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@ -84,14 +84,14 @@ static inline void flush_scache_line(unsigned long addr)
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static inline void protected_flush_icache_line(unsigned long addr)
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{
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__asm__ __volatile__(
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".set noreorder\n\t"
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".set mips3\n"
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"1:\tcache %0,(%1)\n"
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"2:\t.set mips0\n\t"
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".set reorder\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b,2b\n\t"
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".previous"
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" .set push \n"
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" .set noreorder \n"
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" .set mips3 \n"
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"1: cache %0, (%1) \n"
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"2: .set pop \n"
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" .section __ex_table,\"a\" \n"
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" "STR(PTR)" 1b, 2b \n"
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" .previous"
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:
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: "i" (Hit_Invalidate_I), "r" (addr));
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}
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@ -100,19 +100,19 @@ static inline void protected_flush_icache_line(unsigned long addr)
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* R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
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* cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
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* caches. We're talking about one cacheline unnecessarily getting invalidated
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* here so the penaltiy isn't overly hard.
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* here so the penalty isn't overly hard.
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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__asm__ __volatile__(
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".set noreorder\n\t"
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".set mips3\n"
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"1:\tcache %0,(%1)\n"
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"2:\t.set mips0\n\t"
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".set reorder\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b,2b\n\t"
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".previous"
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" .set push \n"
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" .set noreorder \n"
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" .set mips3 \n"
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"1: cache %0, (%1) \n"
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"2: .set pop \n"
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" .section __ex_table,\"a\" \n"
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" "STR(PTR)" 1b, 2b \n"
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" .previous"
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:
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: "i" (Hit_Writeback_Inv_D), "r" (addr));
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}
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@ -120,14 +120,14 @@ static inline void protected_writeback_dcache_line(unsigned long addr)
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static inline void protected_writeback_scache_line(unsigned long addr)
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{
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__asm__ __volatile__(
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".set noreorder\n\t"
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".set mips3\n"
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"1:\tcache %0,(%1)\n"
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"2:\t.set mips0\n\t"
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".set reorder\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b,2b\n\t"
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".previous"
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" .set push \n"
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" .set noreorder \n"
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" .set mips3 \n"
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"1: cache %0, (%1) \n"
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"2: .set pop \n"
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" .section __ex_table,\"a\" \n"
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" "STR(PTR)" 1b, 2b \n"
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" .previous"
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:
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: "i" (Hit_Writeback_Inv_SD), "r" (addr));
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}
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@ -142,6 +142,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
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#define cache16_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
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@ -160,8 +161,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
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" cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
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" cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
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" cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
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" .set mips0 \n" \
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" .set reorder \n" \
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" .set pop \n" \
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: \
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: "r" (base), \
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"i" (op));
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@ -285,6 +285,7 @@ static inline void blast_scache16_page_indexed(unsigned long page)
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#define cache32_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \
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@ -303,8 +304,7 @@ static inline void blast_scache16_page_indexed(unsigned long page)
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" cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \
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" cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \
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" cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \
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" .set mips0 \n" \
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" .set reorder \n" \
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" .set pop \n" \
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: \
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: "r" (base), \
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"i" (op));
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@ -428,6 +428,7 @@ static inline void blast_scache32_page_indexed(unsigned long page)
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#define cache64_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \
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@ -446,8 +447,7 @@ static inline void blast_scache32_page_indexed(unsigned long page)
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" cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \
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" cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \
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" cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \
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" .set mips0 \n" \
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" .set reorder \n" \
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" .set pop \n" \
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: \
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: "r" (base), \
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"i" (op));
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@ -532,6 +532,7 @@ static inline void blast_scache64_page_indexed(unsigned long page)
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#define cache128_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \
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@ -550,8 +551,7 @@ static inline void blast_scache64_page_indexed(unsigned long page)
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" cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \
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" cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \
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" cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \
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" .set mips0 \n" \
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" .set reorder \n" \
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" .set pop \n" \
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: \
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: "r" (base), \
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"i" (op));
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