soundwire: cdns: Add cadence library
Cadence IP implements SoundWire Master. Add base cadence library initialization and interrupt handling Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com> Signed-off-by: Sanyog Kale <sanyog.r.kale@intel.com> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Acked-By: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Vinod Koul
Greg Kroah-Hartman
parent
b0a9c37b01
commit
2f52a5177c
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@ -19,4 +19,7 @@ comment "SoundWire Devices"
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config SOUNDWIRE_BUS
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tristate
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config SOUNDWIRE_CADENCE
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tristate
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endif
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@ -5,3 +5,7 @@
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#Bus Objs
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soundwire-bus-objs := bus_type.o bus.o slave.o mipi_disco.o
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obj-$(CONFIG_SOUNDWIRE_BUS) += soundwire-bus.o
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#Cadence Objs
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soundwire-cadence-objs := cadence_master.o
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obj-$(CONFIG_SOUNDWIRE_CADENCE) += soundwire-cadence.o
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@ -0,0 +1,431 @@
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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// Copyright(c) 2015-17 Intel Corporation.
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/*
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* Cadence SoundWire Master module
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* Used by Master driver
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/soundwire/sdw_registers.h>
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#include <linux/soundwire/sdw.h>
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#include "bus.h"
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#include "cadence_master.h"
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#define CDNS_MCP_CONFIG 0x0
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#define CDNS_MCP_CONFIG_MCMD_RETRY GENMASK(27, 24)
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#define CDNS_MCP_CONFIG_MPREQ_DELAY GENMASK(20, 16)
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#define CDNS_MCP_CONFIG_MMASTER BIT(7)
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#define CDNS_MCP_CONFIG_BUS_REL BIT(6)
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#define CDNS_MCP_CONFIG_SNIFFER BIT(5)
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#define CDNS_MCP_CONFIG_SSPMOD BIT(4)
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#define CDNS_MCP_CONFIG_CMD BIT(3)
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#define CDNS_MCP_CONFIG_OP GENMASK(2, 0)
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#define CDNS_MCP_CONFIG_OP_NORMAL 0
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#define CDNS_MCP_CONTROL 0x4
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#define CDNS_MCP_CONTROL_RST_DELAY GENMASK(10, 8)
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#define CDNS_MCP_CONTROL_CMD_RST BIT(7)
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#define CDNS_MCP_CONTROL_SOFT_RST BIT(6)
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#define CDNS_MCP_CONTROL_SW_RST BIT(5)
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#define CDNS_MCP_CONTROL_HW_RST BIT(4)
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#define CDNS_MCP_CONTROL_CLK_PAUSE BIT(3)
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#define CDNS_MCP_CONTROL_CLK_STOP_CLR BIT(2)
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#define CDNS_MCP_CONTROL_CMD_ACCEPT BIT(1)
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#define CDNS_MCP_CONTROL_BLOCK_WAKEUP BIT(0)
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#define CDNS_MCP_CMDCTRL 0x8
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#define CDNS_MCP_SSPSTAT 0xC
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#define CDNS_MCP_FRAME_SHAPE 0x10
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#define CDNS_MCP_FRAME_SHAPE_INIT 0x14
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#define CDNS_MCP_CONFIG_UPDATE 0x18
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#define CDNS_MCP_CONFIG_UPDATE_BIT BIT(0)
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#define CDNS_MCP_PHYCTRL 0x1C
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#define CDNS_MCP_SSP_CTRL0 0x20
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#define CDNS_MCP_SSP_CTRL1 0x28
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#define CDNS_MCP_CLK_CTRL0 0x30
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#define CDNS_MCP_CLK_CTRL1 0x38
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#define CDNS_MCP_STAT 0x40
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#define CDNS_MCP_STAT_ACTIVE_BANK BIT(20)
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#define CDNS_MCP_STAT_CLK_STOP BIT(16)
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#define CDNS_MCP_INTSTAT 0x44
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#define CDNS_MCP_INTMASK 0x48
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#define CDNS_MCP_INT_IRQ BIT(31)
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#define CDNS_MCP_INT_WAKEUP BIT(16)
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#define CDNS_MCP_INT_SLAVE_RSVD BIT(15)
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#define CDNS_MCP_INT_SLAVE_ALERT BIT(14)
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#define CDNS_MCP_INT_SLAVE_ATTACH BIT(13)
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#define CDNS_MCP_INT_SLAVE_NATTACH BIT(12)
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#define CDNS_MCP_INT_SLAVE_MASK GENMASK(15, 12)
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#define CDNS_MCP_INT_DPINT BIT(11)
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#define CDNS_MCP_INT_CTRL_CLASH BIT(10)
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#define CDNS_MCP_INT_DATA_CLASH BIT(9)
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#define CDNS_MCP_INT_CMD_ERR BIT(7)
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#define CDNS_MCP_INT_RX_WL BIT(2)
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#define CDNS_MCP_INT_TXE BIT(1)
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#define CDNS_MCP_INTSET 0x4C
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#define CDNS_SDW_SLAVE_STAT 0x50
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#define CDNS_MCP_SLAVE_STAT_MASK BIT(1, 0)
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#define CDNS_MCP_SLAVE_INTSTAT0 0x54
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#define CDNS_MCP_SLAVE_INTSTAT1 0x58
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#define CDNS_MCP_SLAVE_INTSTAT_NPRESENT BIT(0)
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#define CDNS_MCP_SLAVE_INTSTAT_ATTACHED BIT(1)
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#define CDNS_MCP_SLAVE_INTSTAT_ALERT BIT(2)
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#define CDNS_MCP_SLAVE_INTSTAT_RESERVED BIT(3)
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#define CDNS_MCP_SLAVE_STATUS_BITS GENMASK(3, 0)
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#define CDNS_MCP_SLAVE_STATUS_NUM 4
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#define CDNS_MCP_SLAVE_INTMASK0 0x5C
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#define CDNS_MCP_SLAVE_INTMASK1 0x60
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#define CDNS_MCP_SLAVE_INTMASK0_MASK GENMASK(30, 0)
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#define CDNS_MCP_SLAVE_INTMASK1_MASK GENMASK(16, 0)
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#define CDNS_MCP_PORT_INTSTAT 0x64
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#define CDNS_MCP_PDI_STAT 0x6C
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#define CDNS_MCP_FIFOLEVEL 0x78
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#define CDNS_MCP_FIFOSTAT 0x7C
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#define CDNS_MCP_RX_FIFO_AVAIL GENMASK(5, 0)
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#define CDNS_MCP_CMD_BASE 0x80
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#define CDNS_MCP_RESP_BASE 0x80
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#define CDNS_MCP_CMD_LEN 0x20
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#define CDNS_MCP_CMD_WORD_LEN 0x4
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#define CDNS_MCP_CMD_SSP_TAG BIT(31)
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#define CDNS_MCP_CMD_COMMAND GENMASK(30, 28)
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#define CDNS_MCP_CMD_DEV_ADDR GENMASK(27, 24)
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#define CDNS_MCP_CMD_REG_ADDR_H GENMASK(23, 16)
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#define CDNS_MCP_CMD_REG_ADDR_L GENMASK(15, 8)
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#define CDNS_MCP_CMD_REG_DATA GENMASK(7, 0)
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#define CDNS_MCP_CMD_READ 2
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#define CDNS_MCP_CMD_WRITE 3
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#define CDNS_MCP_RESP_RDATA GENMASK(15, 8)
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#define CDNS_MCP_RESP_ACK BIT(0)
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#define CDNS_MCP_RESP_NACK BIT(1)
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#define CDNS_DP_SIZE 128
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#define CDNS_DPN_B0_CONFIG(n) (0x100 + CDNS_DP_SIZE * (n))
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#define CDNS_DPN_B0_CH_EN(n) (0x104 + CDNS_DP_SIZE * (n))
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#define CDNS_DPN_B0_SAMPLE_CTRL(n) (0x108 + CDNS_DP_SIZE * (n))
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#define CDNS_DPN_B0_OFFSET_CTRL(n) (0x10C + CDNS_DP_SIZE * (n))
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#define CDNS_DPN_B0_HCTRL(n) (0x110 + CDNS_DP_SIZE * (n))
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#define CDNS_DPN_B0_ASYNC_CTRL(n) (0x114 + CDNS_DP_SIZE * (n))
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#define CDNS_DPN_B1_CONFIG(n) (0x118 + CDNS_DP_SIZE * (n))
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#define CDNS_DPN_B1_CH_EN(n) (0x11C + CDNS_DP_SIZE * (n))
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#define CDNS_DPN_B1_SAMPLE_CTRL(n) (0x120 + CDNS_DP_SIZE * (n))
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#define CDNS_DPN_B1_OFFSET_CTRL(n) (0x124 + CDNS_DP_SIZE * (n))
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#define CDNS_DPN_B1_HCTRL(n) (0x128 + CDNS_DP_SIZE * (n))
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#define CDNS_DPN_B1_ASYNC_CTRL(n) (0x12C + CDNS_DP_SIZE * (n))
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#define CDNS_DPN_CONFIG_BPM BIT(18)
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#define CDNS_DPN_CONFIG_BGC GENMASK(17, 16)
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#define CDNS_DPN_CONFIG_WL GENMASK(12, 8)
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#define CDNS_DPN_CONFIG_PORT_DAT GENMASK(3, 2)
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#define CDNS_DPN_CONFIG_PORT_FLOW GENMASK(1, 0)
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#define CDNS_DPN_SAMPLE_CTRL_SI GENMASK(15, 0)
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#define CDNS_DPN_OFFSET_CTRL_1 GENMASK(7, 0)
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#define CDNS_DPN_OFFSET_CTRL_2 GENMASK(15, 8)
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#define CDNS_DPN_HCTRL_HSTOP GENMASK(3, 0)
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#define CDNS_DPN_HCTRL_HSTART GENMASK(7, 4)
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#define CDNS_DPN_HCTRL_LCTRL GENMASK(10, 8)
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#define CDNS_PORTCTRL 0x130
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#define CDNS_PORTCTRL_DIRN BIT(7)
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#define CDNS_PORTCTRL_BANK_INVERT BIT(8)
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#define CDNS_PORT_OFFSET 0x80
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#define CDNS_PDI_CONFIG(n) (0x1100 + (n) * 16)
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#define CDNS_PDI_CONFIG_SOFT_RESET BIT(24)
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#define CDNS_PDI_CONFIG_CHANNEL GENMASK(15, 8)
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#define CDNS_PDI_CONFIG_PORT GENMASK(4, 0)
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/* Driver defaults */
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#define CDNS_DEFAULT_CLK_DIVIDER 0
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#define CDNS_DEFAULT_FRAME_SHAPE 0x30
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#define CDNS_DEFAULT_SSP_INTERVAL 0x18
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#define CDNS_TX_TIMEOUT 2000
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#define CDNS_PCM_PDI_OFFSET 0x2
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#define CDNS_PDM_PDI_OFFSET 0x6
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#define CDNS_SCP_RX_FIFOLEVEL 0x2
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/*
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* register accessor helpers
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*/
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static inline u32 cdns_readl(struct sdw_cdns *cdns, int offset)
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{
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return readl(cdns->registers + offset);
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}
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static inline void cdns_writel(struct sdw_cdns *cdns, int offset, u32 value)
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{
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writel(value, cdns->registers + offset);
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}
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static inline void cdns_updatel(struct sdw_cdns *cdns,
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int offset, u32 mask, u32 val)
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{
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u32 tmp;
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tmp = cdns_readl(cdns, offset);
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tmp = (tmp & ~mask) | val;
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cdns_writel(cdns, offset, tmp);
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}
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static int cdns_clear_bit(struct sdw_cdns *cdns, int offset, u32 value)
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{
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int timeout = 10;
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u32 reg_read;
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writel(value, cdns->registers + offset);
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/* Wait for bit to be self cleared */
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do {
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reg_read = readl(cdns->registers + offset);
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if ((reg_read & value) == 0)
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return 0;
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timeout--;
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udelay(50);
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} while (timeout != 0);
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return -EAGAIN;
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}
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/*
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* IRQ handling
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*/
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static int cdns_update_slave_status(struct sdw_cdns *cdns,
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u32 slave0, u32 slave1)
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{
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enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
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bool is_slave = false;
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u64 slave, mask;
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int i, set_status;
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/* combine the two status */
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slave = ((u64)slave1 << 32) | slave0;
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memset(status, 0, sizeof(status));
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for (i = 0; i <= SDW_MAX_DEVICES; i++) {
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mask = (slave >> (i * CDNS_MCP_SLAVE_STATUS_NUM)) &
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CDNS_MCP_SLAVE_STATUS_BITS;
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if (!mask)
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continue;
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is_slave = true;
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set_status = 0;
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if (mask & CDNS_MCP_SLAVE_INTSTAT_RESERVED) {
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status[i] = SDW_SLAVE_RESERVED;
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set_status++;
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}
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if (mask & CDNS_MCP_SLAVE_INTSTAT_ATTACHED) {
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status[i] = SDW_SLAVE_ATTACHED;
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set_status++;
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}
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if (mask & CDNS_MCP_SLAVE_INTSTAT_ALERT) {
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status[i] = SDW_SLAVE_ALERT;
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set_status++;
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}
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if (mask & CDNS_MCP_SLAVE_INTSTAT_NPRESENT) {
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status[i] = SDW_SLAVE_UNATTACHED;
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set_status++;
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}
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/* first check if Slave reported multiple status */
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if (set_status > 1) {
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dev_warn(cdns->dev,
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"Slave reported multiple Status: %d\n",
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status[i]);
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/*
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* TODO: we need to reread the status here by
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* issuing a PING cmd
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*/
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}
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}
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if (is_slave)
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return sdw_handle_slave_status(&cdns->bus, status);
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return 0;
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}
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/**
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* sdw_cdns_irq() - Cadence interrupt handler
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* @irq: irq number
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* @dev_id: irq context
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*/
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irqreturn_t sdw_cdns_irq(int irq, void *dev_id)
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{
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struct sdw_cdns *cdns = dev_id;
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u32 int_status;
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int ret = IRQ_HANDLED;
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/* Check if the link is up */
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if (!cdns->link_up)
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return IRQ_NONE;
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int_status = cdns_readl(cdns, CDNS_MCP_INTSTAT);
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if (!(int_status & CDNS_MCP_INT_IRQ))
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return IRQ_NONE;
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if (int_status & CDNS_MCP_INT_CTRL_CLASH) {
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/* Slave is driving bit slot during control word */
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dev_err_ratelimited(cdns->dev, "Bus clash for control word\n");
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int_status |= CDNS_MCP_INT_CTRL_CLASH;
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}
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if (int_status & CDNS_MCP_INT_DATA_CLASH) {
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/*
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* Multiple slaves trying to drive bit slot, or issue with
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* ownership of data bits or Slave gone bonkers
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*/
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dev_err_ratelimited(cdns->dev, "Bus clash for data word\n");
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int_status |= CDNS_MCP_INT_DATA_CLASH;
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}
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if (int_status & CDNS_MCP_INT_SLAVE_MASK) {
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/* Mask the Slave interrupt and wake thread */
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cdns_updatel(cdns, CDNS_MCP_INTMASK,
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CDNS_MCP_INT_SLAVE_MASK, 0);
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int_status &= ~CDNS_MCP_INT_SLAVE_MASK;
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ret = IRQ_WAKE_THREAD;
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}
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cdns_writel(cdns, CDNS_MCP_INTSTAT, int_status);
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return ret;
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}
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EXPORT_SYMBOL(sdw_cdns_irq);
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/**
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* sdw_cdns_thread() - Cadence irq thread handler
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* @irq: irq number
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* @dev_id: irq context
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*/
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irqreturn_t sdw_cdns_thread(int irq, void *dev_id)
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{
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struct sdw_cdns *cdns = dev_id;
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u32 slave0, slave1;
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dev_dbg(cdns->dev, "Slave status change\n");
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slave0 = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT0);
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slave1 = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT1);
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cdns_update_slave_status(cdns, slave0, slave1);
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cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT0, slave0);
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cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT1, slave1);
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/* clear and unmask Slave interrupt now */
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cdns_writel(cdns, CDNS_MCP_INTSTAT, CDNS_MCP_INT_SLAVE_MASK);
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cdns_updatel(cdns, CDNS_MCP_INTMASK,
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CDNS_MCP_INT_SLAVE_MASK, CDNS_MCP_INT_SLAVE_MASK);
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL(sdw_cdns_thread);
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/*
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* init routines
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*/
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/**
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* sdw_cdns_init() - Cadence initialization
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* @cdns: Cadence instance
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*/
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int sdw_cdns_init(struct sdw_cdns *cdns)
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{
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u32 val;
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int ret;
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/* Exit clock stop */
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ret = cdns_clear_bit(cdns, CDNS_MCP_CONTROL,
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CDNS_MCP_CONTROL_CLK_STOP_CLR);
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if (ret < 0) {
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dev_err(cdns->dev, "Couldn't exit from clock stop\n");
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return ret;
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}
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/* Set clock divider */
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val = cdns_readl(cdns, CDNS_MCP_CLK_CTRL0);
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val |= CDNS_DEFAULT_CLK_DIVIDER;
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cdns_writel(cdns, CDNS_MCP_CLK_CTRL0, val);
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/* Set the default frame shape */
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cdns_writel(cdns, CDNS_MCP_FRAME_SHAPE_INIT, CDNS_DEFAULT_FRAME_SHAPE);
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/* Set SSP interval to default value */
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cdns_writel(cdns, CDNS_MCP_SSP_CTRL0, CDNS_DEFAULT_SSP_INTERVAL);
|
||||
cdns_writel(cdns, CDNS_MCP_SSP_CTRL1, CDNS_DEFAULT_SSP_INTERVAL);
|
||||
|
||||
/* Set cmd accept mode */
|
||||
cdns_updatel(cdns, CDNS_MCP_CONTROL, CDNS_MCP_CONTROL_CMD_ACCEPT,
|
||||
CDNS_MCP_CONTROL_CMD_ACCEPT);
|
||||
|
||||
/* Configure mcp config */
|
||||
val = cdns_readl(cdns, CDNS_MCP_CONFIG);
|
||||
|
||||
/* Set Max cmd retry to 15 */
|
||||
val |= CDNS_MCP_CONFIG_MCMD_RETRY;
|
||||
|
||||
/* Set frame delay between PREQ and ping frame to 15 frames */
|
||||
val |= 0xF << SDW_REG_SHIFT(CDNS_MCP_CONFIG_MPREQ_DELAY);
|
||||
|
||||
/* Disable auto bus release */
|
||||
val &= ~CDNS_MCP_CONFIG_BUS_REL;
|
||||
|
||||
/* Disable sniffer mode */
|
||||
val &= ~CDNS_MCP_CONFIG_SNIFFER;
|
||||
|
||||
/* Set cmd mode for Tx and Rx cmds */
|
||||
val &= ~CDNS_MCP_CONFIG_CMD;
|
||||
|
||||
/* Set operation to normal */
|
||||
val &= ~CDNS_MCP_CONFIG_OP;
|
||||
val |= CDNS_MCP_CONFIG_OP_NORMAL;
|
||||
|
||||
cdns_writel(cdns, CDNS_MCP_CONFIG, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(sdw_cdns_init);
|
||||
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
MODULE_DESCRIPTION("Cadence Soundwire Library");
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
|
||||
// Copyright(c) 2015-17 Intel Corporation.
|
||||
|
||||
#ifndef __SDW_CADENCE_H
|
||||
#define __SDW_CADENCE_H
|
||||
|
||||
/**
|
||||
* struct sdw_cdns - Cadence driver context
|
||||
* @dev: Linux device
|
||||
* @bus: Bus handle
|
||||
* @instance: instance number
|
||||
* @registers: Cadence registers
|
||||
* @link_up: Link status
|
||||
*/
|
||||
struct sdw_cdns {
|
||||
struct device *dev;
|
||||
struct sdw_bus bus;
|
||||
unsigned int instance;
|
||||
|
||||
void __iomem *registers;
|
||||
|
||||
bool link_up;
|
||||
};
|
||||
|
||||
#define bus_to_cdns(_bus) container_of(_bus, struct sdw_cdns, bus)
|
||||
|
||||
/* Exported symbols */
|
||||
|
||||
irqreturn_t sdw_cdns_irq(int irq, void *dev_id);
|
||||
irqreturn_t sdw_cdns_thread(int irq, void *dev_id);
|
||||
|
||||
int sdw_cdns_init(struct sdw_cdns *cdns);
|
||||
|
||||
#endif /* __SDW_CADENCE_H */
|
||||
Loading…
Reference in New Issue