mmc: sdhci-of-esdhc: support ESDHC_CAPABILITIES_1 accessing
eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1 register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1) for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -54,6 +54,9 @@
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#define ESDHC_CLOCK_HCKEN 0x00000002
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#define ESDHC_CLOCK_IPGEN 0x00000001
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/* Host Controller Capabilities Register 2 */
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#define ESDHC_CAPABILITIES_1 0x114
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/* Tuning Block Control Register */
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#define ESDHC_TBCTL 0x120
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#define ESDHC_TB_EN 0x00000004
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@ -86,6 +86,17 @@ static u32 esdhc_readl_fixup(struct sdhci_host *host,
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return ret;
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}
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/*
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* DTS properties of mmc host are used to enable each speed mode
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* according to soc and board capability. So clean up
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* SDR50/SDR104/DDR50 support bits here.
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*/
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if (spec_reg == SDHCI_CAPABILITIES_1) {
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ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
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SDHCI_SUPPORT_DDR50);
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return ret;
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}
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ret = value;
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return ret;
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}
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@ -249,7 +260,11 @@ static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
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u32 ret;
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u32 value;
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if (reg == SDHCI_CAPABILITIES_1)
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value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
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else
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value = ioread32be(host->ioaddr + reg);
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ret = esdhc_readl_fixup(host, reg, value);
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return ret;
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@ -260,7 +275,11 @@ static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
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u32 ret;
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u32 value;
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if (reg == SDHCI_CAPABILITIES_1)
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value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
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else
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value = ioread32(host->ioaddr + reg);
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ret = esdhc_readl_fixup(host, reg, value);
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return ret;
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