[ARM] 4503/1: nommu: Add noMMU support for ARMv7
This patch adds the necessary ifdef's to the proc-v7.S code and defines the v7wbi_tlb_fns macro in pgtable-nommu.h Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -377,7 +377,7 @@ config CPU_V7
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select CPU_CACHE_V7
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select CPU_CACHE_VIPT
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select CPU_CP15_MMU
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select CPU_HAS_ASID
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select CPU_HAS_ASID if MMU
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select CPU_COPY_V6 if MMU
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select CPU_TLB_V7 if MMU
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@ -77,6 +77,7 @@ ENTRY(cpu_v7_dcache_clean_area)
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* - we are not using split page tables
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*/
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ENTRY(cpu_v7_switch_mm)
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#ifdef CONFIG_MMU
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mov r2, #0
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ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
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orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
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@ -86,6 +87,7 @@ ENTRY(cpu_v7_switch_mm)
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isb
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mcr p15, 0, r1, c13, c0, 1 @ set context ID
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isb
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#endif
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mov pc, lr
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/*
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@ -109,6 +111,7 @@ ENTRY(cpu_v7_switch_mm)
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* 1111 0 1 1 r/w r/w
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*/
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ENTRY(cpu_v7_set_pte_ext)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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bic r3, r1, #0x000003f0
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@ -136,6 +139,7 @@ ENTRY(cpu_v7_set_pte_ext)
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str r3, [r0]
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mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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#endif
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mov pc, lr
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cpu_v7_name:
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@ -169,6 +173,7 @@ __v7_setup:
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mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
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#endif
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dsb
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#ifdef CONFIG_MMU
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mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r10, c2, c0, 2 @ TTB control register
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orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
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@ -176,11 +181,12 @@ __v7_setup:
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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mov r10, #0x1f @ domains 0, 1 = manager
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mcr p15, 0, r10, c3, c0, 0 @ load domain access register
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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ldr r10, cr1_clear @ get mask for bits to clear
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bic r0, r0, r10 @ clear bits them
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ldr r10, cr1_set @ get mask for bits to set
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orr r0, r0, r10 @ set them
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#endif
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adr r5, v7_crval
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ldmia r5, {r5, r6}
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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bic r0, r0, r5 @ clear bits them
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orr r0, r0, r6 @ set them
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mov pc, lr @ return to head.S:__ret
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/*
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@ -189,12 +195,9 @@ __v7_setup:
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* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
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* 0 110 0011 1.00 .111 1101 < we want
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*/
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.type cr1_clear, #object
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.type cr1_set, #object
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cr1_clear:
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.word 0x0120c302
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cr1_set:
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.word 0x00c0387d
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.type v7_crval, #object
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v7_crval:
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crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c
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__v7_setup_stack:
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.space 4 * 11 @ 11 registers
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@ -103,6 +103,7 @@ extern int is_in_rom(unsigned long);
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#define v4wb_tlb_fns (0)
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#define v4wbi_tlb_fns (0)
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#define v6wbi_tlb_fns (0)
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#define v7wbi_tlb_fns (0)
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#define v3_user_fns (0)
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#define v4_user_fns (0)
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